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Searched defs:SDMA0_PHASE0_QUANTUM__VALUE__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h596 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h597 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
H A Dsdma0_4_2_sh_mask.h599 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
H A Dsdma0_4_2_2_sh_mask.h605 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1014 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
H A Doss_2_4_sh_mask.h1104 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
H A Doss_3_0_1_sh_mask.h1124 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
H A Doss_3_0_sh_mask.h1630 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_0_sh_mask.h292 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
/openbsd/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_sh_mask.h311 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h312 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro