xref: /openbsd/sys/dev/sdmmc/sdmmcreg.h (revision d3ec1c86)
1 /*	$OpenBSD: sdmmcreg.h,v 1.13 2020/08/24 15:06:10 kettenis Exp $	*/
2 
3 /*
4  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5  *
6  * Permission to use, copy, modify, and distribute this software for any
7  * purpose with or without fee is hereby granted, provided that the above
8  * copyright notice and this permission notice appear in all copies.
9  *
10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17  */
18 
19 #ifndef _SDMMCREG_H_
20 #define _SDMMCREG_H_
21 
22 /* MMC commands */				/* response type */
23 #define MMC_GO_IDLE_STATE		0	/* R0 */
24 #define MMC_SEND_OP_COND		1	/* R3 */
25 #define MMC_ALL_SEND_CID		2	/* R2 */
26 #define MMC_SET_RELATIVE_ADDR   	3	/* R1 */
27 #define MMC_SWITCH			6	/* R1B */
28 #define MMC_SELECT_CARD			7	/* R1 */
29 #define MMC_SEND_EXT_CSD		8	/* R1 */
30 #define MMC_SEND_CSD			9	/* R2 */
31 #define MMC_STOP_TRANSMISSION		12	/* R1B */
32 #define MMC_SEND_STATUS			13	/* R1 */
33 #define MMC_SET_BLOCKLEN		16	/* R1 */
34 #define MMC_READ_BLOCK_SINGLE		17	/* R1 */
35 #define MMC_READ_BLOCK_MULTIPLE		18	/* R1 */
36 #define MMC_SEND_TUNING_BLOCK		19	/* R1 */
37 #define MMC_SEND_TUNING_BLOCK_HS200	21	/* R1 */
38 #define MMC_SET_BLOCK_COUNT		23	/* R1 */
39 #define MMC_WRITE_BLOCK_SINGLE		24	/* R1 */
40 #define MMC_WRITE_BLOCK_MULTIPLE	25	/* R1 */
41 #define MMC_APP_CMD			55	/* R1 */
42 
43 /* SD commands */				/* response type */
44 #define SD_SEND_RELATIVE_ADDR		3	/* R6 */
45 #define SD_SEND_SWITCH_FUNC		6	/* R1 */
46 #define SD_SEND_IF_COND			8	/* R7 */
47 #define SD_VOLTAGE_SWITCH		11	/* R1 */
48 
49 /* SD application commands */			/* response type */
50 #define SD_APP_SET_BUS_WIDTH		6	/* R1 */
51 #define SD_APP_OP_COND			41	/* R3 */
52 #define SD_APP_SEND_SCR			51	/* R1 */
53 
54 /* OCR bits */
55 #define MMC_OCR_MEM_READY		(1<<31)	/* memory power-up status bit */
56 #define MMC_OCR_HCS			(1<<30)	/* SD only */
57 #define MMC_OCR_ACCESS_MODE_MASK	(3<<29)	/* MMC only */
58 #define MMC_OCR_ACCESS_MODE_BYTE	(0<<29)	/* MMC only */
59 #define MMC_OCR_ACCESS_MODE_SECTOR	(2<<29)	/* MMC only */
60 #define MMC_OCR_S18A			(1<<24)
61 #define MMC_OCR_3_5V_3_6V		(1<<23)
62 #define MMC_OCR_3_4V_3_5V		(1<<22)
63 #define MMC_OCR_3_3V_3_4V		(1<<21)
64 #define MMC_OCR_3_2V_3_3V		(1<<20)
65 #define MMC_OCR_3_1V_3_2V		(1<<19)
66 #define MMC_OCR_3_0V_3_1V		(1<<18)
67 #define MMC_OCR_2_9V_3_0V		(1<<17)
68 #define MMC_OCR_2_8V_2_9V		(1<<16)
69 #define MMC_OCR_2_7V_2_8V		(1<<15)
70 #define MMC_OCR_2_6V_2_7V		(1<<14)
71 #define MMC_OCR_2_5V_2_6V		(1<<13)
72 #define MMC_OCR_2_4V_2_5V		(1<<12)
73 #define MMC_OCR_2_3V_2_4V		(1<<11)
74 #define MMC_OCR_2_2V_2_3V		(1<<10)
75 #define MMC_OCR_2_1V_2_2V		(1<<9)
76 #define MMC_OCR_2_0V_2_1V		(1<<8)
77 #define MMC_OCR_1_65V_1_95V		(1<<7)
78 
79 #define SD_OCR_VOL_MASK			0xFF8000 /* bits 23:15 */
80 
81 /* R1 response type bits */
82 #define MMC_R1_READY_FOR_DATA		(1<<8)	/* ready for next transfer */
83 #define MMC_R1_APP_CMD			(1<<5)	/* app. commands supported */
84 
85 /* 48-bit response decoding (32 bits w/o CRC) */
86 #define MMC_R1(resp)			((resp)[0])
87 #define MMC_R3(resp)			((resp)[0])
88 #define SD_R6(resp)			((resp)[0])
89 
90 /* RCA argument and response */
91 #define MMC_ARG_RCA(rca)		((rca) << 16)
92 #define SD_R6_RCA(resp)			(SD_R6((resp)) >> 16)
93 
94 /* bus width argument */
95 #define SD_ARG_BUS_WIDTH_1		0
96 #define SD_ARG_BUS_WIDTH_4		2
97 
98 /* EXT_CSD fields */
99 #define EXT_CSD_BUS_WIDTH		183	/* WO */
100 #define EXT_CSD_HS_TIMING		185	/* R/W */
101 #define EXT_CSD_REV			192	/* RO */
102 #define EXT_CSD_STRUCTURE		194	/* RO */
103 #define EXT_CSD_CARD_TYPE		196	/* RO */
104 #define EXT_CSD_SEC_COUNT		212	/* RO */
105 
106 /* EXT_CSD field definitions */
107 #define EXT_CSD_CMD_SET_NORMAL		(1U << 0)
108 #define EXT_CSD_CMD_SET_SECURE		(1U << 1)
109 #define EXT_CSD_CMD_SET_CPSECURE	(1U << 2)
110 
111 /* EXT_CSD_HS_TIMING */
112 #define EXT_CSD_HS_TIMING_BC		0
113 #define EXT_CSD_HS_TIMING_HS		1
114 #define EXT_CSD_HS_TIMING_HS200		2
115 #define EXT_CSD_HS_TIMING_HS400		3
116 
117 /* EXT_CSD_BUS_WIDTH  */
118 #define EXT_CSD_BUS_WIDTH_1		0
119 #define EXT_CSD_BUS_WIDTH_4		1
120 #define EXT_CSD_BUS_WIDTH_8		2
121 #define EXT_CSD_BUS_WIDTH_4_DDR		5
122 #define EXT_CSD_BUS_WIDTH_8_DDR		6
123 
124 /* EXT_CSD_CARD_TYPE */
125 /* The only currently valid values for this field are 0x01, 0x03, 0x07,
126  * 0x0B and 0x0F. */
127 #define EXT_CSD_CARD_TYPE_F_26M		(1 << 0)
128 #define EXT_CSD_CARD_TYPE_F_52M		(1 << 1)
129 #define EXT_CSD_CARD_TYPE_F_DDR52_1_8V	(1 << 2)
130 #define EXT_CSD_CARD_TYPE_F_DDR52_1_2V	(1 << 3)
131 #define EXT_CSD_CARD_TYPE_F_HS200_1_8V	(1 << 4)
132 #define EXT_CSD_CARD_TYPE_F_HS200_1_2V	(1 << 5)
133 #define EXT_CSD_CARD_TYPE_F_HS400_1_8V	(1 << 6)
134 #define EXT_CSD_CARD_TYPE_F_HS400_1_2V	(1 << 7)
135 
136 /* MMC_SWITCH access mode */
137 #define MMC_SWITCH_MODE_CMD_SET		0x00	/* Change the command set */
138 #define MMC_SWITCH_MODE_SET_BITS	0x01	/* Set bits in value */
139 #define MMC_SWITCH_MODE_CLEAR_BITS	0x02	/* Clear bits in value */
140 #define MMC_SWITCH_MODE_WRITE_BYTE	0x03	/* Set target to value */
141 
142 /* MMC R2 response (CSD) */
143 #define MMC_CSD_CSDVER(resp)		MMC_RSP_BITS((resp), 126, 2)
144 #define  MMC_CSD_CSDVER_1_0		1
145 #define  MMC_CSD_CSDVER_2_0		2
146 #define  MMC_CSD_CSDVER_EXT_CSD		3
147 #define MMC_CSD_MMCVER(resp)		MMC_RSP_BITS((resp), 122, 4)
148 #define  MMC_CSD_MMCVER_1_0		0 /* MMC 1.0 - 1.2 */
149 #define  MMC_CSD_MMCVER_1_4		1 /* MMC 1.4 */
150 #define  MMC_CSD_MMCVER_2_0		2 /* MMC 2.0 - 2.2 */
151 #define  MMC_CSD_MMCVER_3_1		3 /* MMC 3.1 - 3.3 */
152 #define  MMC_CSD_MMCVER_4_0		4 /* MMC 4 */
153 #define MMC_CSD_READ_BL_LEN(resp)	MMC_RSP_BITS((resp), 80, 4)
154 #define MMC_CSD_C_SIZE(resp)		MMC_RSP_BITS((resp), 62, 12)
155 #define MMC_CSD_CAPACITY(resp)		((MMC_CSD_C_SIZE((resp))+1) << \
156 					 (MMC_CSD_C_SIZE_MULT((resp))+2))
157 #define MMC_CSD_C_SIZE_MULT(resp)	MMC_RSP_BITS((resp), 47, 3)
158 
159 /* MMC v1 R2 response (CID) */
160 #define MMC_CID_MID_V1(resp)		MMC_RSP_BITS((resp), 104, 24)
161 #define MMC_CID_PNM_V1_CPY(resp, pnm)					\
162 	do {								\
163 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
164 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
165 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
166 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
167 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
168 		(pnm)[5] = MMC_RSP_BITS((resp), 56, 8);			\
169 		(pnm)[6] = MMC_RSP_BITS((resp), 48, 8);			\
170 		(pnm)[7] = '\0';					\
171 	} while (0)
172 #define MMC_CID_REV_V1(resp)		MMC_RSP_BITS((resp), 40, 8)
173 #define MMC_CID_PSN_V1(resp)		MMC_RSP_BITS((resp), 16, 24)
174 #define MMC_CID_MDT_V1(resp)		MMC_RSP_BITS((resp), 8, 8)
175 
176 /* MMC v2 R2 response (CID) */
177 #define MMC_CID_MID_V2(resp)		MMC_RSP_BITS((resp), 120, 8)
178 #define MMC_CID_OID_V2(resp)		MMC_RSP_BITS((resp), 104, 16)
179 #define MMC_CID_PNM_V2_CPY(resp, pnm)					\
180 	do {								\
181 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
182 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
183 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
184 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
185 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
186 		(pnm)[5] = MMC_RSP_BITS((resp), 56, 8);			\
187 		(pnm)[6] = '\0';					\
188 	} while (0)
189 #define MMC_CID_PSN_V2(resp)		MMC_RSP_BITS((resp), 16, 32)
190 
191 /* SD R2 response (CSD) */
192 #define SD_CSD_CSDVER(resp)		MMC_RSP_BITS((resp), 126, 2)
193 #define  SD_CSD_CSDVER_1_0		0
194 #define  SD_CSD_CSDVER_2_0		1
195 #define SD_CSD_TAAC(resp)		MMC_RSP_BITS((resp), 112, 8)
196 #define  SD_CSD_TAAC_1_5_MSEC		0x26
197 #define SD_CSD_NSAC(resp)		MMC_RSP_BITS((resp), 104, 8)
198 #define SD_CSD_SPEED(resp)		MMC_RSP_BITS((resp), 96, 8)
199 #define  SD_CSD_SPEED_25_MHZ		0x32
200 #define  SD_CSD_SPEED_50_MHZ		0x5a
201 #define SD_CSD_CCC(resp)		MMC_RSP_BITS((resp), 84, 12)
202 #define  SD_CSD_CCC_BASIC		(1 << 0)	/* basic */
203 #define  SD_CSD_CCC_BR			(1 << 2)	/* block read */
204 #define  SD_CSD_CCC_BW			(1 << 4)	/* block write */
205 #define  SD_CSD_CCC_ERACE		(1 << 5)	/* erase */
206 #define  SD_CSD_CCC_WP			(1 << 6)	/* write protection */
207 #define  SD_CSD_CCC_LC			(1 << 7)	/* lock card */
208 #define  SD_CSD_CCC_AS			(1 << 8)	/*application specific*/
209 #define  SD_CSD_CCC_IOM			(1 << 9)	/* I/O mode */
210 #define  SD_CSD_CCC_SWITCH		(1 << 10)	/* switch */
211 #define SD_CSD_READ_BL_LEN(resp)	MMC_RSP_BITS((resp), 80, 4)
212 #define SD_CSD_READ_BL_PARTIAL(resp)	MMC_RSP_BITS((resp), 79, 1)
213 #define SD_CSD_WRITE_BLK_MISALIGN(resp)	MMC_RSP_BITS((resp), 78, 1)
214 #define SD_CSD_READ_BLK_MISALIGN(resp)	MMC_RSP_BITS((resp), 77, 1)
215 #define SD_CSD_DSR_IMP(resp)		MMC_RSP_BITS((resp), 76, 1)
216 #define SD_CSD_C_SIZE(resp)		MMC_RSP_BITS((resp), 62, 12)
217 #define SD_CSD_CAPACITY(resp)		((SD_CSD_C_SIZE((resp))+1) << \
218 					 (SD_CSD_C_SIZE_MULT((resp))+2))
219 #define SD_CSD_V2_C_SIZE(resp)		MMC_RSP_BITS((resp), 48, 22)
220 #define SD_CSD_V2_CAPACITY(resp)	((SD_CSD_V2_C_SIZE((resp))+1) << 10)
221 #define SD_CSD_V2_BL_LEN		0x9	/* 512 */
222 #define SD_CSD_VDD_R_CURR_MIN(resp)	MMC_RSP_BITS((resp), 59, 3)
223 #define SD_CSD_VDD_R_CURR_MAX(resp)	MMC_RSP_BITS((resp), 56, 3)
224 #define SD_CSD_VDD_W_CURR_MIN(resp)	MMC_RSP_BITS((resp), 53, 3)
225 #define SD_CSD_VDD_W_CURR_MAX(resp)	MMC_RSP_BITS((resp), 50, 3)
226 #define  SD_CSD_VDD_RW_CURR_100mA	0x7
227 #define  SD_CSD_VDD_RW_CURR_80mA	0x6
228 #define SD_CSD_C_SIZE_MULT(resp)	MMC_RSP_BITS((resp), 47, 3)
229 #define SD_CSD_ERASE_BLK_EN(resp)	MMC_RSP_BITS((resp), 46, 1)
230 #define SD_CSD_SECTOR_SIZE(resp)	MMC_RSP_BITS((resp), 39, 7) /* +1 */
231 #define SD_CSD_WP_GRP_SIZE(resp)	MMC_RSP_BITS((resp), 32, 7) /* +1 */
232 #define SD_CSD_WP_GRP_ENABLE(resp)	MMC_RSP_BITS((resp), 31, 1)
233 #define SD_CSD_R2W_FACTOR(resp)		MMC_RSP_BITS((resp), 26, 3)
234 #define SD_CSD_WRITE_BL_LEN(resp)	MMC_RSP_BITS((resp), 22, 4)
235 #define  SD_CSD_RW_BL_LEN_2G		0xa
236 #define  SD_CSD_RW_BL_LEN_1G		0x9
237 #define SD_CSD_WRITE_BL_PARTIAL(resp)	MMC_RSP_BITS((resp), 21, 1)
238 #define SD_CSD_FILE_FORMAT_GRP(resp)	MMC_RSP_BITS((resp), 15, 1)
239 #define SD_CSD_COPY(resp)		MMC_RSP_BITS((resp), 14, 1)
240 #define SD_CSD_PERM_WRITE_PROTECT(resp)	MMC_RSP_BITS((resp), 13, 1)
241 #define SD_CSD_TMP_WRITE_PROTECT(resp)	MMC_RSP_BITS((resp), 12, 1)
242 #define SD_CSD_FILE_FORMAT(resp)	MMC_RSP_BITS((resp), 10, 2)
243 
244 /* SD R2 response (CID) */
245 #define SD_CID_MID(resp)		MMC_RSP_BITS((resp), 120, 8)
246 #define SD_CID_OID(resp)		MMC_RSP_BITS((resp), 104, 16)
247 #define SD_CID_PNM_CPY(resp, pnm)					\
248 	do {								\
249 		(pnm)[0] = MMC_RSP_BITS((resp), 96, 8);			\
250 		(pnm)[1] = MMC_RSP_BITS((resp), 88, 8);			\
251 		(pnm)[2] = MMC_RSP_BITS((resp), 80, 8);			\
252 		(pnm)[3] = MMC_RSP_BITS((resp), 72, 8);			\
253 		(pnm)[4] = MMC_RSP_BITS((resp), 64, 8);			\
254 		(pnm)[5] = '\0';					\
255 	} while (0)
256 #define SD_CID_REV(resp)		MMC_RSP_BITS((resp), 56, 8)
257 #define SD_CID_PSN(resp)		MMC_RSP_BITS((resp), 24, 32)
258 #define SD_CID_MDT(resp)		MMC_RSP_BITS((resp), 8, 12)
259 
260 /* SCR (SD Configuration Register) */
261 #define SCR_STRUCTURE(scr)		MMC_RSP_BITS((scr), 60, 4)
262 #define  SCR_STRUCTURE_VER_1_0		0 /* Version 1.0 */
263 #define SCR_SD_SPEC(scr)		MMC_RSP_BITS((scr), 56, 4)
264 #define  SCR_SD_SPEC_VER_1_0		0 /* Version 1.0 and 1.01 */
265 #define  SCR_SD_SPEC_VER_1_10		1 /* Version 1.10 */
266 #define  SCR_SD_SPEC_VER_2		2 /* Version 2.00 or Version 3.0X */
267 #define SCR_DATA_STAT_AFTER_ERASE(scr)	MMC_RSP_BITS((scr), 55, 1)
268 #define SCR_SD_SECURITY(scr)		MMC_RSP_BITS((scr), 52, 3)
269 #define  SCR_SD_SECURITY_NONE		0 /* no security */
270 #define  SCR_SD_SECURITY_1_0		1 /* security protocol 1.0 */
271 #define  SCR_SD_SECURITY_1_0_2		2 /* security protocol 1.0 */
272 #define SCR_SD_BUS_WIDTHS(scr)		MMC_RSP_BITS((scr), 48, 4)
273 #define  SCR_SD_BUS_WIDTHS_1BIT		(1 << 0) /* 1bit (DAT0) */
274 #define  SCR_SD_BUS_WIDTHS_4BIT		(1 << 2) /* 4bit (DAT0-3) */
275 #define SCR_SD_SPEC3(scr)		MMC_RSP_BITS((scr), 47, 1)
276 #define SCR_EX_SECURITY(scr)		MMC_RSP_BITS((scr), 43, 4)
277 #define SCR_SD_SPEC4(scr)		MMC_RSP_BITS((scr), 42, 1)
278 #define SCR_RESERVED(scr)		MMC_RSP_BITS((scr), 34, 8)
279 #define SCR_CMD_SUPPORT_CMD23(scr)	MMC_RSP_BITS((scr), 33, 1)
280 #define SCR_CMD_SUPPORT_CMD20(scr)	MMC_RSP_BITS((scr), 32, 1)
281 #define SCR_RESERVED2(scr)		MMC_RSP_BITS((scr), 0, 32)
282 
283 /* Status of Switch Function */
284 #define SFUNC_STATUS_GROUP(status, group) \
285 	(__bitfield((uint32_t *)(status), 400 + (group - 1) * 16, 16))
286 
287 #define SD_ACCESS_MODE_SDR12	0
288 #define SD_ACCESS_MODE_SDR25	1
289 #define SD_ACCESS_MODE_SDR50	2
290 #define SD_ACCESS_MODE_SDR104	3
291 #define SD_ACCESS_MODE_DDR50	4
292 
293 /* Might be slow, but it should work on big and little endian systems. */
294 #define MMC_RSP_BITS(resp, start, len)	__bitfield((resp), (start)-8, (len))
295 static __inline int
__bitfield(u_int32_t * src,int start,int len)296 __bitfield(u_int32_t *src, int start, int len)
297 {
298 	u_int8_t *sp;
299 	u_int32_t dst, mask;
300 	int shift, bs, bc;
301 
302 	if (start < 0 || len < 0 || len > 32)
303 		return 0;
304 
305 	dst = 0;
306 	mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
307 	shift = 0;
308 
309 	while (len > 0) {
310 		sp = (u_int8_t *)src + start / 8;
311 		bs = start % 8;
312 		bc = 8 - bs;
313 		if (bc > len)
314 			bc = len;
315 		dst |= (*sp++ >> bs) << shift;
316 		shift += bc;
317 		start += bc;
318 		len -= bc;
319 	}
320 
321 	dst &= mask;
322 	return (int)dst;
323 }
324 
325 #endif
326