1 /******************************************************************************* 2 Copyright (C) 2016 Marvell International Ltd. 3 4 SPDX-License-Identifier: BSD-2-Clause-Patent 5 6 *******************************************************************************/ 7 #ifndef __SPI_MASTER_H__ 8 #define __SPI_MASTER_H__ 9 10 #include <Library/IoLib.h> 11 #include <Library/PcdLib.h> 12 #include <Library/UefiLib.h> 13 #include <Library/DebugLib.h> 14 #include <Library/DxeServicesTableLib.h> 15 #include <Library/MemoryAllocationLib.h> 16 #include <Uefi/UefiBaseType.h> 17 #include <Library/BaseMemoryLib.h> 18 #include <Library/UefiBootServicesTableLib.h> 19 #include <Library/UefiRuntimeLib.h> 20 21 #include <Protocol/Spi.h> 22 23 #define SPI_MASTER_SIGNATURE SIGNATURE_32 ('M', 'S', 'P', 'I') 24 #define SPI_MASTER_FROM_SPI_MASTER_PROTOCOL(a) CR (a, SPI_MASTER, SpiMasterProtocol, SPI_MASTER_SIGNATURE) 25 26 // Marvell Flash Device Controller Registers 27 #define SPI_CTRL_REG (0x00) 28 #define SPI_CONF_REG (0x04) 29 #define SPI_DATA_OUT_REG (0x08) 30 #define SPI_DATA_IN_REG (0x0c) 31 #define SPI_INT_CAUSE_REG (0x10) 32 33 // Serial Memory Interface Control Register Masks 34 #define SPI_CS_NUM_OFFSET 2 35 #define SPI_CS_NUM_MASK (0x7 << SPI_CS_NUM_OFFSET) 36 #define SPI_MEM_READY_MASK (0x1 << 1) 37 #define SPI_CS_EN_MASK (0x1 << 0) 38 39 // Serial Memory Interface Configuration Register Masks 40 #define SPI_BYTE_LENGTH_OFFSET 5 41 #define SPI_BYTE_LENGTH (0x1 << SPI_BYTE_LENGTH_OFFSET) 42 #define SPI_CPOL_OFFSET 11 43 #define SPI_CPOL_MASK (0x1 << SPI_CPOL_OFFSET) 44 #define SPI_CPHA_OFFSET 12 45 #define SPI_CPHA_MASK (0x1 << SPI_CPHA_OFFSET) 46 #define SPI_TXLSBF_OFFSET 13 47 #define SPI_TXLSBF_MASK (0x1 << SPI_TXLSBF_OFFSET) 48 #define SPI_RXLSBF_OFFSET 14 49 #define SPI_RXLSBF_MASK (0x1 << SPI_RXLSBF_OFFSET) 50 51 #define SPI_SPR_OFFSET 0 52 #define SPI_SPR_MASK (0xf << SPI_SPR_OFFSET) 53 #define SPI_SPPR_0_OFFSET 4 54 #define SPI_SPPR_0_MASK (0x1 << SPI_SPPR_0_OFFSET) 55 #define SPI_SPPR_HI_OFFSET 6 56 #define SPI_SPPR_HI_MASK (0x3 << SPI_SPPR_HI_OFFSET) 57 58 #define SPI_TRANSFER_BEGIN 0x01 // Assert CS before transfer 59 #define SPI_TRANSFER_END 0x02 // Deassert CS after transfers 60 61 #define SPI_TIMEOUT 100000 62 63 typedef struct { 64 MARVELL_SPI_MASTER_PROTOCOL SpiMasterProtocol; 65 UINTN Signature; 66 EFI_HANDLE Handle; 67 EFI_LOCK Lock; 68 } SPI_MASTER; 69 70 EFI_STATUS 71 EFIAPI 72 MvSpiTransfer ( 73 IN MARVELL_SPI_MASTER_PROTOCOL *This, 74 IN SPI_DEVICE *Slave, 75 IN UINTN DataByteCount, 76 IN VOID *DataOut, 77 IN VOID *DataIn, 78 IN UINTN Flag 79 ); 80 81 EFI_STATUS 82 EFIAPI 83 MvSpiReadWrite ( 84 IN MARVELL_SPI_MASTER_PROTOCOL *This, 85 IN SPI_DEVICE *Slave, 86 IN UINT8 *Cmd, 87 IN UINTN CmdSize, 88 IN UINT8 *DataOut, 89 OUT UINT8 *DataIn, 90 IN UINTN DataSize 91 ); 92 93 EFI_STATUS 94 EFIAPI 95 MvSpiInit ( 96 IN MARVELL_SPI_MASTER_PROTOCOL * This 97 ); 98 99 SPI_DEVICE * 100 EFIAPI 101 MvSpiSetupSlave ( 102 IN MARVELL_SPI_MASTER_PROTOCOL * This, 103 IN SPI_DEVICE *Slave, 104 IN UINTN Cs, 105 IN SPI_MODE Mode 106 ); 107 108 EFI_STATUS 109 EFIAPI 110 MvSpiFreeSlave ( 111 IN SPI_DEVICE *Slave 112 ); 113 114 EFI_STATUS 115 EFIAPI 116 SpiMasterEntryPoint ( 117 IN EFI_HANDLE ImageHandle, 118 IN EFI_SYSTEM_TABLE *SystemTable 119 ); 120 121 #endif // __SPI_MASTER_H__ 122