1 /* Declarations for functions in ESP8266 ROM code 2 * 3 * Copyright (c) 2016-2019 Espressif Systems (Shanghai) PTE LTD & Cesanta Software Limited 4 * All rights reserved 5 * 6 * This program is free software; you can redistribute it and/or modify it under 7 * the terms of the GNU General Public License as published by the Free Software 8 * Foundation; either version 2 of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS 12 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 51 Franklin 16 * Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 20 /* ROM function prototypes for functions in ROM which are 21 called by the flasher stubs. 22 */ 23 #pragma once 24 25 #include <stdint.h> 26 #include "soc_support.h" 27 28 int uart_rx_one_char(uint8_t *ch); 29 uint8_t uart_rx_one_char_block(); 30 int uart_tx_one_char(char ch); 31 void uart_div_modify(uint32_t uart_no, uint32_t baud_div); 32 33 int SendMsg(uint8_t *msg, uint8_t size); 34 int send_packet(const void *packet, uint32_t size); 35 36 void _putc1(char *ch); 37 38 void ets_delay_us(uint32_t us); 39 40 typedef enum { SPI_FLASH_RESULT_OK = 0, 41 SPI_FLASH_RESULT_ERR = 1, 42 SPI_FLASH_RESULT_TIMEOUT = 2 } SpiFlashOpResult; 43 44 SpiFlashOpResult SPILock(); 45 SpiFlashOpResult SPIUnlock(); 46 SpiFlashOpResult SPIRead(uint32_t addr, void *dst, uint32_t size); 47 SpiFlashOpResult SPIWrite(uint32_t addr, const uint8_t *src, uint32_t size); 48 SpiFlashOpResult SPIEraseChip(); 49 SpiFlashOpResult SPIEraseBlock(uint32_t block_num); 50 SpiFlashOpResult SPIEraseSector(uint32_t sector_num); 51 uint32_t SPI_read_status(); 52 uint32_t Wait_SPI_Idle(); 53 void spi_flash_attach(); 54 55 void SelectSpiFunction(); 56 void SPIFlashModeConfig(uint32_t a, uint32_t b); 57 void SPIReadModeCnfig(uint32_t a); 58 uint32_t SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask); 59 60 void ets_delay_us(uint32_t delay_micros); 61 62 void ets_isr_mask(uint32_t ints); 63 void ets_isr_unmask(uint32_t ints); 64 void ets_set_user_start(void (*user_start_fn)()); 65 66 void software_reset(); 67 void software_reset_cpu(int cpu_no); 68 69 struct MD5Context { 70 uint32_t buf[4]; 71 uint32_t bits[2]; 72 uint8_t in[64]; 73 }; 74 75 void MD5Init(struct MD5Context *ctx); 76 void MD5Update(struct MD5Context *ctx, void *buf, uint32_t len); 77 void MD5Final(uint8_t digest[16], struct MD5Context *ctx); 78 79 typedef struct { 80 uint32_t device_id; 81 uint32_t chip_size; // chip size in bytes 82 uint32_t block_size; 83 uint32_t sector_size; 84 uint32_t page_size; 85 uint32_t status_mask; 86 } esp_rom_spiflash_chip_t; 87 88 89 typedef void (*int_handler_t)(void *arg); 90 int_handler_t ets_isr_attach(uint32_t int_num, int_handler_t handler, 91 void *arg); 92 /* Some ESP32-onwards ROM functions */ 93 #if ESP32_OR_LATER 94 uint32_t ets_get_detected_xtal_freq(void); 95 void uart_tx_flush(int uart); 96 uint32_t ets_efuse_get_spiconfig(void); 97 98 #if ESP32 99 SpiFlashOpResult esp_rom_spiflash_write_encrypted(uint32_t addr, const uint8_t *src, uint32_t size); 100 #else 101 void SPI_Write_Encrypt_Enable(); 102 void SPI_Write_Encrypt_Disable(); 103 SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32_t len); 104 #endif 105 106 #if ESP32S2_OR_LATER 107 uint32_t GetSecurityInfoProc(int* pMsg, int* pnErr, uint8_t *buf); // pMsg and pnErr unused in ROM 108 SpiFlashOpResult SPI_read_status_high(esp_rom_spiflash_chip_t *spi, uint32_t *status); 109 #else 110 /* Note: On ESP32 this was a static function whose first argument was elided by the 111 compiler. */ 112 SpiFlashOpResult SPI_read_status_high(uint32_t *status); 113 #endif 114 115 SpiFlashOpResult SPI_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); 116 117 void intr_matrix_set(int cpu_no, uint32_t module_num, uint32_t intr_num); 118 #endif /* ESP32_OR_LATER */ 119 120 /* RISC-V-only ROM functions */ 121 #if IS_RISCV 122 void esprv_intc_int_set_priority(int intr_num, int priority); 123 #endif // IS_RISCV 124 125 /* USB-OTG and USB-JTAG-Serial imports */ 126 #ifdef WITH_USB_OTG 127 #define ACM_BYTES_PER_TX 64 128 #define ACM_STATUS_LINESTATE_CHANGED -1 129 #define ACM_STATUS_RX -4 130 #define LINE_CTRL_BAUD_RATE (1 << 0) 131 #define LINE_CTRL_RTS (1 << 1) 132 #define LINE_CTRL_DTR (1 << 2) 133 #define LINE_CTRL_DCD (1 << 3) 134 #define LINE_CTRL_DSR (1 << 4) 135 #define USBDC_PERSIST_ENA (1<<31) 136 void usb_dw_isr_handler(void* arg); 137 typedef void cdc_acm_device; 138 extern cdc_acm_device *uart_acm_dev; 139 typedef void(*uart_irq_callback_t)(cdc_acm_device *dev, int status); 140 void cdc_acm_irq_callback_set(cdc_acm_device *dev, uart_irq_callback_t cb); 141 void cdc_acm_irq_rx_enable(cdc_acm_device *dev); 142 void cdc_acm_irq_rx_disable(cdc_acm_device *dev); 143 int cdc_acm_fifo_read(cdc_acm_device *dev, uint8_t *rx_data, const int size); 144 int cdc_acm_fifo_fill(cdc_acm_device *dev, const uint8_t *tx_data, int len); 145 int cdc_acm_line_ctrl_get(cdc_acm_device *dev, uint32_t ctrl, uint32_t *val); 146 int cdc_acm_rx_fifo_cnt(cdc_acm_device *dev); 147 void cdc_acm_irq_state_enable(cdc_acm_device *dev); 148 void usb_dc_check_poll_for_interrupts(void); 149 void chip_usb_set_persist_flags(uint32_t flags); 150 int usb_dc_prepare_persist(void); 151 #endif // WITH_USB_OTG 152 153 #if WITH_USB_JTAG_SERIAL || WITH_USB_OTG 154 typedef struct { 155 uint8_t *pRcvMsgBuff; 156 uint8_t *pWritePos; 157 uint8_t *pReadPos; 158 uint8_t TrigLvl; 159 int BuffState; 160 } RcvMsgBuff; 161 162 typedef struct { 163 int baud_rate; 164 int data_bits; 165 int exist_parity; 166 int parity; 167 int stop_bits; 168 int flow_ctrl; 169 uint8_t buff_uart_no; 170 RcvMsgBuff rcv_buff; 171 int rcv_state; 172 int received; 173 } UartDevice; 174 175 UartDevice * GetUartDevice(); 176 #endif // WITH_USB_JTAG_SERIAL || WITH_USB_OTG 177 178 /* Enabling 32-bit flash memory addressing for ESP32S3 */ 179 #if defined(ESP32S3) 180 #define BIT(nr) (1UL << (nr)) 181 182 // GigaDevice Flash read commands 183 #define ROM_FLASH_CMD_RD4B_GD 0x13 184 #define ROM_FLASH_CMD_FSTRD4B_GD 0x0C 185 #define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C 186 #define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC 187 #define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD 188 189 // GigaDevice Flash page program commands 190 #define ROM_FLASH_CMD_PP4B_GD 0x12 191 #define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 192 #define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E 193 194 #define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) 195 196 typedef enum { 197 SPI_FLASH_QIO_MODE = 0, 198 SPI_FLASH_QOUT_MODE, 199 SPI_FLASH_DIO_MODE, 200 SPI_FLASH_DOUT_MODE, 201 SPI_FLASH_FASTRD_MODE, 202 SPI_FLASH_SLOWRD_MODE, 203 SPI_FLASH_OPI_STR_MODE, 204 SPI_FLASH_OPI_DTR_MODE, 205 SPI_FLASH_OOUT_MODE, 206 SPI_FLASH_OIO_STR_MODE, 207 SPI_FLASH_OIO_DTR_MODE, 208 SPI_FLASH_QPI_MODE, 209 } SpiFlashRdMode; 210 211 typedef enum { 212 ESP_ROM_SPIFLASH_RESULT_OK, 213 ESP_ROM_SPIFLASH_RESULT_ERR, 214 ESP_ROM_SPIFLASH_RESULT_TIMEOUT 215 } esp_rom_spiflash_result_t; 216 217 /* Stub doesn't currently support OPI flash mode, following functions are used for 32-bit addressing only */ 218 void esp_rom_opiflash_exec_cmd(int spi_num, SpiFlashRdMode mode, 219 uint32_t cmd, int cmd_bit_len, 220 uint32_t addr, int addr_bit_len, 221 int dummy_bits, 222 uint8_t* mosi_data, int mosi_bit_len, 223 uint8_t* miso_data, int miso_bit_len, 224 uint32_t cs_mask, 225 bool is_write_erase_operation); 226 227 esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(int spi_num, SpiFlashRdMode mode); 228 229 esp_rom_spiflash_result_t opi_flash_wren(int spi_num, SpiFlashRdMode mode); 230 231 esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(int spi_num, uint32_t sector_num, SpiFlashRdMode mode); 232 233 esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(int spi_num, uint32_t block_num, SpiFlashRdMode mode); 234 #endif // ESP32S3 235