1 /*  Copyright 2003-2005 Guillaume Duhamel
2     Copyright 2004-2005, 2013 Theo Berkau
3     Copyright 2016 James Laird-Wah
4 
5     This file is part of Yabause.
6 
7     Yabause is free software; you can redistribute it and/or modify
8     it under the terms of the GNU General Public License as published by
9     the Free Software Foundation; either version 2 of the License, or
10     (at your option) any later version.
11 
12     Yabause is distributed in the hope that it will be useful,
13     but WITHOUT ANY WARRANTY; without even the implied warranty of
14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15     GNU General Public License for more details.
16 
17     You should have received a copy of the GNU General Public License
18     along with Yabause; if not, write to the Free Software
19     Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301  USA
20 */
21 
22 /*! \file sh7034.c
23     \brief SH7034 cpu implementation (CD block controller)
24 */
25 
26 #include "core.h"
27 #include "sh7034.h"
28 #include "assert.h"
29 #include "memory.h"
30 #include "ygr.h"
31 #include "debug.h"
32 #include <stdarg.h>
33 #include "cd_drive.h"
34 #ifdef ENABLE_TSUNAMI
35 #include "tsunami/yab_tsunami.h"
36 #endif
37 #include "mpeg_card.h"
38 
39 //#define SH1_MEM_DEBUG
40 #ifdef SH1_MEM_DEBUG
41 #define SH1MEMLOG(...) DebugPrintf(MainLog, __FILE__, __LINE__, __VA_ARGS__)
42 #else
43 #define SH1MEMLOG(...)
44 #endif
45 
46 //#define WANT_TIMER_TRACE
47 #ifdef WANT_TIMER_TRACE
48 #define TIMERTRACE(...) cd_trace_log(__VA_ARGS__)
49 #else
50 #define TIMERTRACE(...)
51 #endif
52 
53 //#define WANT_PORT_TRACE
54 #ifdef WANT_PORT_TRACE
55 #define PORTTRACE(...) cd_trace_log(__VA_ARGS__)
56 #else
57 #define PORTTRACE(...)
58 #endif
59 
60 u8 transfer_buffer[13] = { 0 };
61 
update_transfer_buffer()62 void update_transfer_buffer()
63 {
64    int i;
65    for (i = 0; i < 13; i++)
66    {
67       transfer_buffer[i] = T2ReadByte(sh1_cxt.ram, 0x0002D0 + i);//0xF0002D0
68    }
69 }
70 
71 u16 cr_response[4] = { 0 };
72 
update_cr_response_values(u32 addr)73 void update_cr_response_values(u32 addr)
74 {
75    int updated = 0;
76    if (addr >= 0x0F00026C && addr <= 0x0F000273)
77    {
78       updated = 1;
79       //0x0F00026C
80       cr_response[0] = T2ReadWord(sh1_cxt.ram, 0x00026C + 0);
81       cr_response[1] = T2ReadWord(sh1_cxt.ram, 0x00026C + 2);
82       cr_response[2] = T2ReadWord(sh1_cxt.ram, 0x00026C + 4);
83       cr_response[3] = T2ReadWord(sh1_cxt.ram, 0x00026C + 6);
84    }
85 
86    if (updated)
87    {
88       int q = 1;
89    }
90 }
91 
cd_trace_log(const char * format,...)92 void cd_trace_log(const char * format, ...)
93 {
94    static int started = 0;
95    static FILE* fp = NULL;
96    va_list l;
97 
98    if (!started)
99    {
100       fp = fopen("C:/yabause/log.txt", "w");
101 
102       if (!fp)
103       {
104          return;
105       }
106       started = 1;
107    }
108 
109    va_start(l, format);
110    vfprintf(fp, format, l);
111    va_end(l);
112 }
113 
114 
print_tocr()115 void print_tocr()
116 {
117    TIMERTRACE("Timer Output Control Register(TOCR)\n");
118 
119    //tocr
120    if (sh1_cxt.onchip.itu.tocr & (1 << 1))
121       TIMERTRACE("\tTIOCA3, TIOCA4, and TIOCB4 are output directly \n");
122    else
123       TIMERTRACE("\tTIOCA3, TIOCA4, and TIOCB4 are inverted and output\n");
124 
125    if (sh1_cxt.onchip.itu.tocr & (1 << 0))
126       TIMERTRACE("\tTIOCB3, TOCXA4, and TOCXB4 are output directly\n");
127    else
128       TIMERTRACE("\tTIOCB3, TOCXA4, and TOCXB4 are inverted and output\n");
129 }
130 
print_tcr(int which)131 void print_tcr(int which)
132 {
133    TIMERTRACE("Timer Control Register(TCR)\n");
134 
135    switch ((sh1_cxt.onchip.itu.channel[which].tcr >> 5) & 3)
136    {
137    case 0:
138       TIMERTRACE("\tTCNT is not cleared\n");
139       break;
140    case 1:
141       TIMERTRACE("\tTCNT is cleared by general register A (GRA) compare match or input capture\n");
142       break;
143    case 2:
144       TIMERTRACE("\tTCNT is cleared by general register B (GRB) compare match or input capture\n");
145       break;
146    case 3:
147       TIMERTRACE("\tSynchronizing clear: TCNT is cleared in synchronization with clear of other timer counters operating in sync\n");
148       break;
149    }
150 
151    if (sh1_cxt.onchip.itu.channel[which].tcr & (1 << 4))
152       TIMERTRACE("\tCount both rising and falling edges\n");
153    else
154    {
155       if (sh1_cxt.onchip.itu.channel[which].tcr & (1 << 3))
156          TIMERTRACE("\tCount falling edges.\n", which);
157       else
158          TIMERTRACE("\tCount rising edges.\n", which);
159    }
160 
161    switch (sh1_cxt.onchip.itu.channel[which].tcr & 7)
162    {
163    case 0:
164       TIMERTRACE("\tInternal clock phi\n");
165       break;
166    case 1:
167       TIMERTRACE("\tInternal clock phi/2\n");
168       break;
169    case 2:
170       TIMERTRACE("\tInternal clock phi/4\n");
171       break;
172    case 3:
173       TIMERTRACE("\tInternal clock phi/8\n");
174       break;
175    case 4:
176       TIMERTRACE("\tExternal clock A\n");
177       break;
178    case 5:
179       TIMERTRACE("\tExternal clock B\n");
180       break;
181    case 6:
182       TIMERTRACE("\tExternal clock C\n");
183       break;
184    case 7:
185       TIMERTRACE("\tExternal clock D\n");
186       break;
187    }
188 }
189 
print_tior(int which)190 void print_tior(int which)
191 {
192    TIMERTRACE("Timer I/O Control Register (TIOR)\n");
193 
194    //tior3
195    switch ((sh1_cxt.onchip.itu.channel[which].tior >> 4) & 7)
196    {
197       //output compare
198    case 0:
199       TIMERTRACE("\tGRB Compare match with pin output disabled\n");
200       break;
201    case 1:
202       TIMERTRACE("\tGRB 0 output at GRB compare match\n");
203       break;
204    case 2:
205       TIMERTRACE("\tGRB 1 output at GRB compare match\n");
206       break;
207    case 3:
208       TIMERTRACE("\tGRB Output toggles at GRB compare match \n");
209       break;
210       //input capture
211    case 4:
212       TIMERTRACE("\tGRB captures rising edge of input\n");
213       break;
214    case 5:
215       TIMERTRACE("\tGRB captures falling edge of input\n");
216       break;
217    case 6:
218    case 7:
219       TIMERTRACE("\tGRB captures both edges of input\n");
220       break;
221    }
222 
223    switch ((sh1_cxt.onchip.itu.channel[which].tior >> 4) & 7)
224    {
225       //output compare
226    case 0:
227       TIMERTRACE("\tGRA Compare match with pin output disabled\n");
228       break;
229    case 1:
230       TIMERTRACE("\tGRA 0 output at GRA compare match\n");
231       break;
232    case 2:
233       TIMERTRACE("\tGRA 1 output at GRA compare match\n");
234       break;
235    case 3:
236       TIMERTRACE("\tGRA Output toggles at GRA compare match \n");
237       break;
238       //input capture
239    case 4:
240       TIMERTRACE("\tGRA captures rising edge of input\n");
241       break;
242    case 5:
243       TIMERTRACE("\tGRA captures falling edge of input\n");
244       break;
245    case 6:
246    case 7:
247       TIMERTRACE("\tGRA captures both edges of input\n");
248       break;
249    }
250 }
251 
print_tier(int which)252 void print_tier(int which)
253 {
254    TIMERTRACE("Timer Interrupt Enable Register (TIER)\n");
255 
256    //tier3
257    if (sh1_cxt.onchip.itu.channel[which].tier & (1 << 2))
258       TIMERTRACE("\tEnables interrupt requests from OVF\n");
259    else
260       TIMERTRACE("\tDisables interrupt requests by OVF\n");
261 
262    if (sh1_cxt.onchip.itu.channel[which].tier & (1 << 1))
263       TIMERTRACE("\tEnables interrupt requests by IMFB (IMIB)\n");
264    else
265       TIMERTRACE("\tDisables interrupt requests by IMFB (IMIB)\n");
266 
267    if (sh1_cxt.onchip.itu.channel[which].tier & (1 << 0))
268       TIMERTRACE("\tEnables interrupt requests by IMFA (IMIA)\n");
269    else
270       TIMERTRACE("\tDisables interrupt requests by IMFA (IMIA)\n");
271 }
272 
print_tsr(int which)273 void print_tsr(int which)
274 {
275    TIMERTRACE("Timer Status Register(TSR)\n");
276 
277    //tsr3
278    if (sh1_cxt.onchip.itu.channel[which].tsr & (1 << 2))
279       TIMERTRACE("\tSetting condition: TCNT overflow from H'FFFF to H'0000 or underflow from H'0000 to H'FFFF\n");
280    else
281       TIMERTRACE("\tClearing condition: Read OVF when OVF = 1, then write 0 in OVF\n");
282 
283    if (sh1_cxt.onchip.itu.channel[which].tsr & (1 << 1))
284       TIMERTRACE("\tSetting conditions: !!!!!!!!\n");
285    else
286       TIMERTRACE("\tClearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB\n");
287 
288    if (sh1_cxt.onchip.itu.channel[which].tsr & (1 << 0))
289       TIMERTRACE("\tSetting conditions: !!!!!!!!\n");
290    else
291       TIMERTRACE("\tClearing condition: Read IMFA when IMFA = 1, then write 0 in IMFA. DMAC is activated by an IMIA interrupt (only channels 0�E)\n");
292 }
293 
print_tmdr(int which)294 void print_tmdr(int which)
295 {
296    TIMERTRACE("TMDR\n");
297 
298    if (which == 2)
299    {
300       if (sh1_cxt.onchip.itu.tmdr & (1 << 6))
301          TIMERTRACE("\tChannel 2 operates in phase counting mode\n");
302       else
303          TIMERTRACE("\tChannel 2 operates normally .\n");
304 
305       if (sh1_cxt.onchip.itu.tmdr & (1 << 5))
306          TIMERTRACE("\tOVF of TSR2 is set to 1 when TCNT2 overflows\n");
307       else
308          TIMERTRACE("\tOVF of TSR2 is set to 1 when TCNT2 overflows or underflows.\n");
309 
310    }
311 
312    if (sh1_cxt.onchip.itu.tmdr & (1 << which))
313       TIMERTRACE("\toperates in PWM mode\n");
314    else
315       TIMERTRACE("\toperates normally.\n");
316 }
317 
print_tsnc(int which)318 void print_tsnc(int which)
319 {
320    //tsnc
321    TIMERTRACE("Timer Synchro Register (TSNC)\n");
322 
323    if (sh1_cxt.onchip.itu.tstr & (1 << which))
324       TIMERTRACE("\toperates synchronously\n");
325    else
326       TIMERTRACE("\toperates independently\n");
327 
328 }
329 
print_tstr(int which)330 void print_tstr(int which)
331 {
332    //tstr
333    TIMERTRACE("Timer Start Register(TSTR)\n");
334 
335    if (sh1_cxt.onchip.itu.tstr & (1 << which))
336       TIMERTRACE("\tTimer is counting\n");
337    else
338       TIMERTRACE("\tTimer is halted\n");
339 }
340 
print_tfcr(int which)341 void print_tfcr(int which)
342 {
343    TIMERTRACE("Timer Function Control Register (TFCR) \n");
344 
345    if (which == 3 || which == 4)
346    {
347       //tfcr
348       switch ((sh1_cxt.onchip.itu.tfcr >> 4) & 3)
349       {
350       case 0:
351       case 1:
352          TIMERTRACE("\tChannels 3 and 4 operate normally\n");
353          break;
354       case 2:
355          TIMERTRACE("\tChannels 3 and 4 operate together in complementary PWM mode\n");
356          break;
357       case 3:
358          TIMERTRACE("\tChannels 3 and 4 operate together in reset-synchronized PWM mode\n");
359          break;
360       }
361    }
362 
363    if (which == 4)
364    {
365       if (sh1_cxt.onchip.itu.tfcr & (1 << 3))
366          TIMERTRACE("\tBuffer operation of GRB4 and BRB4\n");
367       else
368          TIMERTRACE("\tGRB4 operates normally\n");
369 
370       if (sh1_cxt.onchip.itu.tfcr & (1 << 2))
371          TIMERTRACE("\tBuffer operation of GRA4 and BRA4\n");
372       else
373          TIMERTRACE("\tGRA4 operates normally\n");
374    }
375 
376    if (which == 3)
377    {
378       if (sh1_cxt.onchip.itu.tfcr & (1 << 1))
379          TIMERTRACE("\tBuffer operation of GRB3 and BRB3\n");
380       else
381          TIMERTRACE("\tGRB4 operates normally\n");
382 
383       if (sh1_cxt.onchip.itu.tfcr & (1 << 0))
384          TIMERTRACE("\tBuffer operation of GRA3 and BRA3\n");
385       else
386          TIMERTRACE("\tGRA4 operates normally\n");
387    }
388 }
389 
print_timers()390 void print_timers()
391 {
392 
393    //do timer 3
394 
395 
396    //tcr3
397 
398    int which = 3;
399 
400    TIMERTRACE("***TIMER %d***\n", which);
401 
402    print_tstr(which);
403 
404    print_tsnc(which);
405 
406    print_tmdr(which);
407 
408    print_tfcr(which);
409 
410    print_tcr(which);
411 
412    print_tior(which);
413 
414    print_tier(which);
415 
416    print_tsr(which);
417 
418    //tcnt3
419    TIMERTRACE("\tTCNT: %04X\n", sh1_cxt.onchip.itu.channel[which].tcnt);
420    //gra3
421    TIMERTRACE("\tGRA: %04X\n", sh1_cxt.onchip.itu.channel[which].gra);
422    //grb3
423    TIMERTRACE("\tGRB: %04X\n", sh1_cxt.onchip.itu.channel[which].grb);
424    //bra3
425    TIMERTRACE("\tBRA: %04X\n", sh1_cxt.onchip.itu.channel[which].bra);
426    //brb3
427    TIMERTRACE("\tBRB: %04X\n", sh1_cxt.onchip.itu.channel[which].brb);
428 
429    print_tocr();
430 
431 
432 #if 0
433    TIMERTRACE("TSTR\n");
434 
435    int i;
436    for (i = 4; i >= 0; i--)
437    {
438 
439    }
440 
441    TIMERTRACE("TSTR\n");
442 
443    for (i = 4; i >= 0; i--)
444    {
445       if (sh1_cxt.onchip.itu.tsnc & (1 << i))
446          TIMERTRACE("\tThe timer counter for TCNT%d operates independently\n", i);
447       else
448          TIMERTRACE("\tTCNT%d operates synchronously.\n", i);
449    }
450 
451    for (i = 4; i >= 0; i--)
452    {
453       TIMERTRACE("TIER%d\n", i);
454 
455 
456    }
457 #endif
458 
459 #if 0
460    TIMERTRACE("SCR\n");
461 
462    for (i = 0; i < 2; i++)
463    {
464       if (sh1_cxt.onchip.sci[i].scr & SCI_TIE)
465          TIMERTRACE("\tSCI Channel %d Transmit-data-empty interrupt request (TXI) is enabled\n", i);
466       else
467          TIMERTRACE("\tSCI Channel %d Transmit-data-empty interrupt request (TXI) is disabled\n", i);
468 
469       if (sh1_cxt.onchip.sci[i].scr & SCI_RIE)
470          TIMERTRACE("\tSCI Channel %d Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled\n", i);
471       else
472          TIMERTRACE("\tSCI Channel %d Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled \n", i);
473 
474       if (sh1_cxt.onchip.sci[i].scr & SCI_MPIE)
475          TIMERTRACE("\tSCI Channel %d Multiprocessor interrupts are enabled\n", i);
476       else
477          TIMERTRACE("\tSCI Channel %d Multiprocessor interrupts are disabled\n", i);
478 
479       if (sh1_cxt.onchip.sci[i].scr & SCI_TEIE)
480          TIMERTRACE("\tSCI Channel %d Transmit-end interrupt (TEI) requests are enabled\n", i);
481       else
482          TIMERTRACE("\tSCI Channel %d Transmit-end interrupt (TEI) requests are disabled\n", i);
483    }
484 #endif
485    //TIMERTRACE("TCSR\n");
486 
487    //if (sh1_cxt.onchip.wdt.tcsr & (1 << 6))
488    //   TIMERTRACE("\tSCI Channel %d Transmit-data-empty interrupt request (TXI) is enabled\n", i);
489    //else
490    //   TIMERTRACE("\tSCI Channel %d Transmit-data-empty interrupt request (TXI) is disabled\n", i);
491 #if 0
492    for (i = 4; i >= 0; i--)
493    {
494       TIMERTRACE("TIOR%d\n", i);
495 
496 
497    }
498 #endif
499 }
500 
print_pacr1()501 void print_pacr1()
502 {
503    PORTTRACE("PACR1\n");
504 
505    PORTTRACE(" Pin 15\n");
506 
507    switch ((sh1_cxt.onchip.pfc.pacr1 >> 14) & 3)
508    {
509    case 0:
510       PORTTRACE("\tInput / output(PA15)\n");
511       break;
512    case 1:
513       PORTTRACE("\tInterrupt request input (IRQ3)\n");
514       break;
515    case 2:
516       PORTTRACE("\tReserved\n");
517       break;
518    case 3:
519       PORTTRACE("\tDMA transfer request input (DREQ1)\n");
520       break;
521    }
522 
523    PORTTRACE(" Pin 14\n");
524 
525    switch ((sh1_cxt.onchip.pfc.pacr1 >> 12) & 3)
526    {
527    case 0:
528       PORTTRACE("\tInput / output(PA14)\n");
529       break;
530    case 1:
531       PORTTRACE("\tInterrupt request input (IRQ2)\n");
532       break;
533    case 2:
534       PORTTRACE("\tReserved\n");
535       break;
536    case 3:
537       PORTTRACE("\tDMA transfer acknowledge output (DACK1)\n");
538       break;
539    }
540 
541    PORTTRACE(" Pin 13\n");
542 
543    switch ((sh1_cxt.onchip.pfc.pacr1 >> 10) & 3)
544    {
545    case 0:
546       PORTTRACE("\tInput / output(PA13)\n");
547       break;
548    case 1:
549       PORTTRACE("\tInterrupt request input (IRQ1)\n");
550       break;
551    case 2:
552       PORTTRACE("\tITU timer clock input (TCLKB)\n");
553       break;
554    case 3:
555       PORTTRACE("\tDMA transfer request input (DREQ0)\n");
556       break;
557    }
558 
559    PORTTRACE(" Pin 12\n");
560 
561    switch ((sh1_cxt.onchip.pfc.pacr1 >> 8) & 3)
562    {
563    case 0:
564       PORTTRACE("\tInput / output(PA12)\n");
565       break;
566    case 1:
567       PORTTRACE("\tInterrupt request input (IRQ0)\n");
568       break;
569    case 2:
570       PORTTRACE("\tITU timer clock input (TCLKA)\n");
571       break;
572    case 3:
573       PORTTRACE("\tDMA transfer acknowledge output (DACK0)\n");
574       break;
575    }
576 
577    PORTTRACE(" Pin 11\n");
578 
579    switch ((sh1_cxt.onchip.pfc.pacr1 >> 6) & 3)
580    {
581    case 0:
582       PORTTRACE("\tInput / output(PA11)\n");
583       break;
584    case 1:
585       PORTTRACE("\tUpper data bus parity input/output (DPH)\n");
586       break;
587    case 2:
588       PORTTRACE("\tITU input capture/output compare (TIOCB1)\n");
589       break;
590    case 3:
591       PORTTRACE("\tReserved\n");
592       break;
593    }
594 
595    PORTTRACE(" Pin 10\n");
596 
597    switch ((sh1_cxt.onchip.pfc.pacr1 >> 4) & 3)
598    {
599    case 0:
600       PORTTRACE("\tInput / output(PA10)\n");
601       break;
602    case 1:
603       PORTTRACE("\tLower data bus parity input/output (DPL)\n");
604       break;
605    case 2:
606       PORTTRACE("\tITU input capture/output compare (TIOCA1)\n");
607       break;
608    case 3:
609       PORTTRACE("\tReserved\n");
610       break;
611    }
612 
613    PORTTRACE(" Pin 9\n");
614 
615    switch ((sh1_cxt.onchip.pfc.pacr1 >> 2) & 3)
616    {
617    case 0:
618       PORTTRACE("\tInput / output(PA9)\n");
619       break;
620    case 1:
621       PORTTRACE("\tAddress hold output (AH)\n");
622       break;
623    case 2:
624       PORTTRACE("\tA/D conversion trigger input (ADTRG)\n");
625       break;
626    case 3:
627       PORTTRACE("\tInterrupt request output (IRQOUT)\n");
628       break;
629    }
630 
631    PORTTRACE(" Pin 8\n");
632 
633    switch ((sh1_cxt.onchip.pfc.pacr1) & 1)
634    {
635    case 0:
636       PORTTRACE("\tInput / output(PA8)\n");
637       break;
638    case 1:
639       PORTTRACE("\tBus request input (BREQ)\n");
640       break;
641    }
642 }
643 
print_pacr2()644 void print_pacr2()
645 {
646    PORTTRACE("PACR2\n");
647 
648    PORTTRACE(" Pin 7\n");
649 
650    if(!((sh1_cxt.onchip.pfc.pacr2) & (1 << 14)))
651       PORTTRACE("\tInput / output(PA7)\n");
652    else
653       PORTTRACE("\tBus request acknowledge output (BACK)\n");
654 
655    PORTTRACE(" Pin 6\n");
656 
657    if (!((sh1_cxt.onchip.pfc.pacr2) & (1 << 12)))
658       PORTTRACE("\tInput / output(PA6)\n");
659    else
660       PORTTRACE("\tRead output (RD) \n");
661 
662    PORTTRACE(" Pin 5\n");
663 
664    if (!((sh1_cxt.onchip.pfc.pacr2) & (1 << 10)))
665       PORTTRACE("\tInput / output(PA5)\n");
666    else
667       PORTTRACE("\tUpper write output (WRH) or lower byte strobe output (LBS) \n");
668 
669    PORTTRACE(" Pin 4\n");
670 
671    if (!((sh1_cxt.onchip.pfc.pacr2) & (1 << 8)))
672       PORTTRACE("\tInput / output(PA4)\n");
673    else
674       PORTTRACE("\tLower write output (WRL) or write output (WR) \n");
675 
676    PORTTRACE(" Pin 3\n");
677 
678    switch ((sh1_cxt.onchip.pfc.pacr2 >> 6) & 3)
679    {
680    case 0:
681       PORTTRACE("\tInput / output(PA3)\n");
682       break;
683    case 1:
684       PORTTRACE("\tChip select output (CS7)\n");
685       break;
686    case 2:
687       PORTTRACE("\tWait state input (WAIT) \n");
688       break;
689    case 3:
690       PORTTRACE("\tReserved\n");
691       break;
692    }
693 
694    PORTTRACE(" Pin 2\n");
695 
696    switch ((sh1_cxt.onchip.pfc.pacr2 >> 4) & 3)
697    {
698    case 0:
699       PORTTRACE("\tInput / output(PA2)\n");
700       break;
701    case 1:
702       PORTTRACE("\tChip select output (CS6)\n");
703       break;
704    case 2:
705       PORTTRACE("\tITU input capture/output compare (TIOCB0)\n");
706       break;
707    case 3:
708       PORTTRACE("\tReserved\n");
709       break;
710    }
711 
712    PORTTRACE(" Pin 1\n");
713 
714    switch ((sh1_cxt.onchip.pfc.pacr2 >> 2) & 3)
715    {
716    case 0:
717       PORTTRACE("\tInput / output(PA1)\n");
718       break;
719    case 1:
720       PORTTRACE("\tChip select output (CS5)\n");
721       break;
722    case 2:
723       PORTTRACE("\tRow address strobe output (RAS)\n");
724       break;
725    case 3:
726       PORTTRACE("\tReserved\n");
727       break;
728    }
729 
730    PORTTRACE(" Pin 0\n");
731 
732    switch (sh1_cxt.onchip.pfc.pacr2  & 3)
733    {
734    case 0:
735       PORTTRACE("\tInput / output(PA0)\n");
736       break;
737    case 1:
738       PORTTRACE("\tChip select output (CS4)\n");
739       break;
740    case 2:
741       PORTTRACE("\tITU input capture/output compare (TIOCA0)\n");
742       break;
743    case 3:
744       PORTTRACE("\tReserved\n");
745       break;
746    }
747 }
748 
print_pbcr1()749 void print_pbcr1()
750 {
751    PORTTRACE("PBCR1\n");
752 
753    PORTTRACE(" Pin 15\n");
754 
755    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 14) & 3)
756    {
757    case 0:
758       PORTTRACE("\tInput / output(PB15)\n");
759       break;
760    case 1:
761       PORTTRACE("\tInterrupt request input (IRQ7)\n");
762       break;
763    case 2:
764       PORTTRACE("\tReserved\n");
765       break;
766    case 3:
767       PORTTRACE("\tTiming pattern output (TP15)\n");
768       break;
769    }
770 
771    PORTTRACE(" Pin 14\n");
772 
773    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 12) & 3)
774    {
775    case 0:
776       PORTTRACE("\tInput / output(PB14)\n");
777       break;
778    case 1:
779       PORTTRACE("\tInterrupt request input (IRQ6)\n");
780       break;
781    case 2:
782       PORTTRACE("\tReserved\n");
783       break;
784    case 3:
785       PORTTRACE("\tTiming pattern output (TP14)\n");
786       break;
787    }
788 
789    PORTTRACE(" Pin 13\n");
790 
791    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 10) & 3)
792    {
793    case 0:
794       PORTTRACE("\tInput / output(PB13)\n");
795       break;
796    case 1:
797       PORTTRACE("\tInterrupt request input (IRQ5)\n");
798       break;
799    case 2:
800       PORTTRACE("\tSerial clock input/output (SCK1)\n");
801       break;
802    case 3:
803       PORTTRACE("\tTiming pattern output (TP13)\n");
804       break;
805    }
806 
807    PORTTRACE(" Pin 12\n");
808 
809    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 8) & 3)
810    {
811    case 0:
812       PORTTRACE("\tInput / output(PB12)\n");
813       break;
814    case 1:
815       PORTTRACE("\tInterrupt request input (IRQ4)\n");
816       break;
817    case 2:
818       PORTTRACE("\tSerial clock input/output (SCK0)\n");
819       break;
820    case 3:
821       PORTTRACE("\tTiming pattern output (TP12)\n");
822       break;
823    }
824 
825    PORTTRACE(" Pin 11\n");
826 
827    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 6) & 3)
828    {
829    case 0:
830       PORTTRACE("\tInput / output(PB11)\n");
831       break;
832    case 1:
833       PORTTRACE("\tReserved\n");
834       break;
835    case 2:
836       PORTTRACE("\tTransmit data output (TxD1)\n");
837       break;
838    case 3:
839       PORTTRACE("\tTiming pattern output (TP11)\n");
840       break;
841    }
842 
843    PORTTRACE(" Pin 10\n");
844 
845    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 4) & 3)
846    {
847    case 0:
848       PORTTRACE("\tInput / output(PB10)\n");
849       break;
850    case 1:
851       PORTTRACE("\tReserved\n");
852       break;
853    case 2:
854       PORTTRACE("\tReceive data input (RxD1)\n");
855       break;
856    case 3:
857       PORTTRACE("\tTiming pattern output (TP10)\n");
858       break;
859    }
860 
861    PORTTRACE(" Pin 9\n");
862 
863    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 2) & 3)
864    {
865    case 0:
866       PORTTRACE("\tInput / output(PB9)\n");
867       break;
868    case 1:
869       PORTTRACE("\tReserved\n");
870       break;
871    case 2:
872       PORTTRACE("\tTransmit data output (TxD0)\n");
873       break;
874    case 3:
875       PORTTRACE("\tTiming pattern output (TP9)\n");
876       break;
877    }
878 
879    PORTTRACE(" Pin 8\n");
880 
881    switch ((sh1_cxt.onchip.pfc.pbcr1 >> 0) & 3)
882    {
883    case 0:
884       PORTTRACE("\tInput / output(PB8)\n");
885       break;
886    case 1:
887       PORTTRACE("\tReserved\n");
888       break;
889    case 2:
890       PORTTRACE("\tReceive data input (RxD0)\n");
891       break;
892    case 3:
893       PORTTRACE("\tTiming pattern output (TP8)\n");
894       break;
895    }
896 }
897 
print_pbcr2()898 void print_pbcr2()
899 {
900    PORTTRACE("PBCR2\n");
901 
902    PORTTRACE(" Pin 7\n");
903 
904    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 14) & 3)
905    {
906    case 0:
907       PORTTRACE("\tInput / output(PB7)\n");
908       break;
909    case 1:
910       PORTTRACE("\tITU timer clock input (TCLKD)\n");
911       break;
912    case 2:
913       PORTTRACE("\tITU output compare (TOCXB4)\n");
914       break;
915    case 3:
916       PORTTRACE("\tTiming pattern output (TP7)\n");
917       break;
918    }
919 
920    PORTTRACE(" Pin 6\n");
921 
922    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 12) & 3)
923    {
924    case 0:
925       PORTTRACE("\tInput / output(PB6)\n");
926       break;
927    case 1:
928       PORTTRACE("\tITU timer clock input (TCLKC)\n");
929       break;
930    case 2:
931       PORTTRACE("\tITU output compare (TOCXA4)\n");
932       break;
933    case 3:
934       PORTTRACE("\tTiming pattern output (TP6)\n");
935       break;
936    }
937 
938    PORTTRACE(" Pin 5\n");
939 
940    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 10) & 3)
941    {
942    case 0:
943       PORTTRACE("\tInput / output(PB5)\n");
944       break;
945    case 1:
946       PORTTRACE("\tReserved\n");
947       break;
948    case 2:
949       PORTTRACE("\tITU input capture/output compare (TIOCB4)\n");
950       break;
951    case 3:
952       PORTTRACE("\tTiming pattern output (TP5)\n");
953       break;
954    }
955 
956    PORTTRACE(" Pin 4\n");
957 
958    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 8) & 3)
959    {
960    case 0:
961       PORTTRACE("\tInput / output(PB4)\n");
962       break;
963    case 1:
964       PORTTRACE("\tReserved\n");
965       break;
966    case 2:
967       PORTTRACE("\tITU input capture/output compare (TIOCA4)\n");
968       break;
969    case 3:
970       PORTTRACE("\tTiming pattern output (TP4)\n");
971       break;
972    }
973 
974    PORTTRACE(" Pin 3\n");
975 
976    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 6) & 3)
977    {
978    case 0:
979       PORTTRACE("\tInput / output(PB3)\n");
980       break;
981    case 1:
982       PORTTRACE("\tReserved\n");
983       break;
984    case 2:
985       PORTTRACE("\tITU input capture/output compare (TIOCB3)\n");
986       break;
987    case 3:
988       PORTTRACE("\tTiming pattern output (TP3)\n");
989       break;
990    }
991 
992    PORTTRACE(" Pin 2\n");
993 
994    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 4) & 3)
995    {
996    case 0:
997       PORTTRACE("\tInput / output(PB2)\n");
998       break;
999    case 1:
1000       PORTTRACE("\tReserved\n");
1001       break;
1002    case 2:
1003       PORTTRACE("\tITU input capture/output compare (TIOCA3)\n");
1004       break;
1005    case 3:
1006       PORTTRACE("\tTiming pattern output (TP2)\n");
1007       break;
1008    }
1009 
1010    PORTTRACE(" Pin 1\n");
1011 
1012    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 2) & 3)
1013    {
1014    case 0:
1015       PORTTRACE("\tInput / output(PB1)\n");
1016       break;
1017    case 1:
1018       PORTTRACE("\tReserved\n");
1019       break;
1020    case 2:
1021       PORTTRACE("\tITU input capture/output compare (TIOCB2)\n");
1022       break;
1023    case 3:
1024       PORTTRACE("\tTiming pattern output (TP1)\n");
1025       break;
1026    }
1027 
1028    PORTTRACE(" Pin 0\n");
1029 
1030    switch ((sh1_cxt.onchip.pfc.pbcr2 >> 0) & 3)
1031    {
1032    case 0:
1033       PORTTRACE("\tInput / output(PB0)\n");
1034       break;
1035    case 1:
1036       PORTTRACE("\tReserved\n");
1037       break;
1038    case 2:
1039       PORTTRACE("\tITU input capture/output compare (TIOCA2)\n");
1040       break;
1041    case 3:
1042       PORTTRACE("\tTiming pattern output (TP0)\n");
1043       break;
1044    }
1045 }
1046 
1047 
port_debug()1048 void port_debug()
1049 {
1050    int i;
1051    PORTTRACE("PAIOR\n");
1052 
1053    for (i = 0; i < 16; i++)
1054    {
1055       if (sh1_cxt.onchip.pfc.paior & (1 << i))
1056          PORTTRACE("\tPin %d is an output\n", i);
1057       else
1058          PORTTRACE("\tPin %d is an input\n", i);
1059    }
1060 
1061    PORTTRACE("PBIOR\n");
1062 
1063    for (i = 0; i < 16; i++)
1064    {
1065       if (sh1_cxt.onchip.pfc.pbior & (1 << i))
1066          PORTTRACE("\tPin %d is an output\n", i);
1067       else
1068          PORTTRACE("\tPin %d is an input\n", i);
1069    }
1070 
1071    print_pacr1();
1072 
1073    print_pacr2();
1074 
1075    print_pbcr1();
1076 
1077    print_pbcr2();
1078 }
1079 
print_serial(int which)1080 void print_serial(int which)
1081 {
1082    PORTTRACE("SCI channel %d\n", which);
1083 
1084    if (!(sh1_cxt.onchip.sci[which].smr & (1 << 7)))
1085       PORTTRACE("\tAsynchronous mode\n");
1086    else
1087       PORTTRACE("\tSynchronous mode\n");
1088 
1089    if (!(sh1_cxt.onchip.sci[which].smr & (1 << 6)))
1090       PORTTRACE("\tEight-bit data\n");
1091    else
1092       PORTTRACE("\tSeven-bit data.\n");
1093 
1094    if (!(sh1_cxt.onchip.sci[which].smr & (1 << 5)))
1095       PORTTRACE("\tParity bit not added or checked \n");
1096    else
1097       PORTTRACE("\tParity bit added and checked.\n");
1098 
1099    if (!(sh1_cxt.onchip.sci[which].smr & (1 << 4)))
1100       PORTTRACE("\tEven parity \n");
1101    else
1102       PORTTRACE("\tOdd parity\n");
1103 
1104    if (!(sh1_cxt.onchip.sci[which].smr & (1 << 3)))
1105       PORTTRACE("\tOne stop bit\n");
1106    else
1107       PORTTRACE("\tTwo stop bits\n");
1108 
1109    if (!(sh1_cxt.onchip.sci[which].smr & (1 << 2)))
1110       PORTTRACE("\tMultiprocessor function disabled \n");
1111    else
1112       PORTTRACE("\tMultiprocessor format selected\n");
1113 
1114    switch (sh1_cxt.onchip.sci[which].smr & 3)
1115    {
1116    case 0:
1117       PORTTRACE("\tSystem clock\n");
1118       break;
1119    case 1:
1120       PORTTRACE("\tphi/4\n");
1121       break;
1122    case 2:
1123       PORTTRACE("\tphi/16\n");
1124       break;
1125    case 3:
1126       PORTTRACE("\tphi/64\n");
1127       break;
1128    }
1129 
1130    PORTTRACE("SCR");
1131 
1132    if (!(sh1_cxt.onchip.sci[which].scr & SCI_TIE))
1133       PORTTRACE("\tTransmit-data-empty interrupt request (TXI) is disabled \n");
1134    else
1135       PORTTRACE("\tTransmit-data-empty interrupt request (TXI) is enabled\n");
1136 
1137    if (!(sh1_cxt.onchip.sci[which].scr & SCI_RIE))
1138       PORTTRACE("\tReceive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are disabled  \n");
1139    else
1140       PORTTRACE("\tReceive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are enabled\n");
1141 
1142    if (!(sh1_cxt.onchip.sci[which].scr & SCI_TE))
1143       PORTTRACE("\tTransmitter disabled \n");
1144    else
1145       PORTTRACE("\tTransmitter enabled.\n");
1146 
1147    if (!(sh1_cxt.onchip.sci[which].scr & SCI_RE))
1148       PORTTRACE("\tReceiver disabled  \n");
1149    else
1150       PORTTRACE("\tReceiver enabled.\n");
1151 
1152    if (!(sh1_cxt.onchip.sci[which].scr & SCI_MPIE))
1153       PORTTRACE("\tMultiprocessor interrupts are disabled  \n");
1154    else
1155       PORTTRACE("\tMultiprocessor interrupts are enabled\n");
1156 
1157    if (!(sh1_cxt.onchip.sci[which].scr & SCI_TEIE))
1158       PORTTRACE("\tTransmit-end interrupt (TEI) requests are disabled \n");
1159    else
1160       PORTTRACE("\tTransmit-end interrupt (TEI) requests are enabled.\n");
1161 
1162    if (sh1_cxt.onchip.sci[which].smr & (1 << 7))
1163    {
1164       //synchronous mode
1165       switch (sh1_cxt.onchip.sci[which].scr & 3)
1166       {
1167       case 0:
1168       case 1:
1169          PORTTRACE("\tInternal clock, SCK pin used for serial clock output\n");
1170          break;
1171       case 2:
1172       case 3:
1173          PORTTRACE("\tExternal clock, SCK pin used for serial clock input\n");
1174          break;
1175       }
1176    }
1177    else
1178    {
1179       //async
1180       switch (sh1_cxt.onchip.sci[which].scr & 3)
1181       {
1182       case 0:
1183          PORTTRACE("\tInternal clock, SCK pin used for input pin\n");
1184          break;
1185       case 1:
1186          PORTTRACE("\tInternal clock, SCK pin used for clock output\n");
1187          break;
1188       case 2:
1189       case 3:
1190          PORTTRACE("\tExternal clock, SCK pin used for clock input\n");
1191          break;
1192       }
1193    }
1194 
1195    PORTTRACE("\tBitrate %02X\n", sh1_cxt.onchip.sci[which].brr);
1196 
1197    //serial pin
1198 
1199    PORTTRACE("\tSCK0 %d\n", ((sh1_cxt.onchip.pfc.pbcr1 >> 8) & 3));
1200    PORTTRACE("\tIn/out %d (1 means output)\n", ((sh1_cxt.onchip.pfc.pbior >> 12) & 1));
1201 }
1202 
1203 struct Sh1 sh1_cxt;
1204 
onchip_write_timer_byte(struct Onchip * regs,u32 addr,int which_timer,u8 data)1205 void onchip_write_timer_byte(struct Onchip * regs, u32 addr, int which_timer, u8 data)
1206 {
1207 
1208 
1209    //print_serial(1);
1210 
1211    //port_debug();
1212 
1213    //print_timers();
1214 
1215    switch (addr)
1216    {
1217    case 0:
1218       regs->itu.channel[which_timer].tcr = data;
1219       return;
1220       break;
1221    case 1:
1222       regs->itu.channel[which_timer].tior = data;
1223       return;
1224       break;
1225    case 2:
1226       regs->itu.channel[which_timer].tier = data;
1227       return;
1228       break;
1229    case 3:
1230       //can only clear flags
1231       if (!(data & 1))
1232          regs->itu.channel[which_timer].tsr &= ~1;
1233 
1234       if (!(data & 2))
1235          regs->itu.channel[which_timer].tsr &= ~2;
1236 
1237       if (!(data & 4))
1238          regs->itu.channel[which_timer].tsr &= ~4;
1239       return;
1240       break;
1241    case 4:
1242       regs->itu.channel[which_timer].tcnt = (regs->itu.channel[which_timer].tcnt & 0xff) | (data << 8);
1243       return;
1244       break;
1245    case 5:
1246       regs->itu.channel[which_timer].tcnt = (regs->itu.channel[which_timer].tcnt & 0xff00) | data;
1247       return;
1248       break;
1249    case 6:
1250       regs->itu.channel[which_timer].gra = (regs->itu.channel[which_timer].gra & 0xff) | (data << 8);
1251       return;
1252       break;
1253    case 7:
1254       regs->itu.channel[which_timer].gra = (regs->itu.channel[which_timer].gra & 0xff00) | data;
1255       return;
1256       break;
1257    case 8:
1258       regs->itu.channel[which_timer].grb = (regs->itu.channel[which_timer].grb & 0xff) | (data << 8);
1259       return;
1260       break;
1261    case 9:
1262       regs->itu.channel[which_timer].grb = (regs->itu.channel[which_timer].grb & 0xff00) | data;
1263       return;
1264       break;
1265    case 0xa:
1266       regs->itu.channel[which_timer].bra = (regs->itu.channel[which_timer].bra & 0xff) | (data << 8);
1267       return;
1268       break;
1269    case 0xb:
1270       regs->itu.channel[which_timer].bra = (regs->itu.channel[which_timer].bra & 0xff00) | data;
1271       return;
1272       break;
1273    case 0xc:
1274       regs->itu.channel[which_timer].brb = (regs->itu.channel[which_timer].brb & 0xff) | (data << 8);
1275       return;
1276       break;
1277    case 0xd:
1278       regs->itu.channel[which_timer].brb = (regs->itu.channel[which_timer].brb & 0xff00) | data;
1279       return;
1280       break;
1281    }
1282 
1283    assert(0);
1284 }
1285 
onchip_read_timer_byte(struct Onchip * regs,u32 addr,int which_timer)1286 u8 onchip_read_timer_byte(struct Onchip * regs, u32 addr, int which_timer)
1287 {
1288 
1289    //print_timers();
1290 
1291    switch (addr)
1292    {
1293    case 0:
1294       return regs->itu.channel[which_timer].tcr;
1295       break;
1296    case 1:
1297       return regs->itu.channel[which_timer].tior;
1298       break;
1299    case 2:
1300       return regs->itu.channel[which_timer].tier;
1301       break;
1302    case 3:
1303       return regs->itu.channel[which_timer].tsr;
1304       break;
1305    case 4:
1306       return regs->itu.channel[which_timer].tcnt >> 8;
1307       break;
1308    case 5:
1309       return regs->itu.channel[which_timer].tcnt & 0xff;
1310       break;
1311    case 6:
1312       return regs->itu.channel[which_timer].gra >> 8;
1313       break;
1314    case 7:
1315       return regs->itu.channel[which_timer].gra & 0xff;
1316       break;
1317    case 8:
1318       return regs->itu.channel[which_timer].grb >> 8;
1319       break;
1320    case 9:
1321       return regs->itu.channel[which_timer].grb & 0xff;
1322       break;
1323    case 0xa:
1324       return regs->itu.channel[which_timer].bra >> 8;
1325       break;
1326    case 0xb:
1327       return regs->itu.channel[which_timer].bra & 0xff;
1328       break;
1329    case 0xc:
1330       return regs->itu.channel[which_timer].brb >> 8;
1331       break;
1332    case 0xd:
1333       return regs->itu.channel[which_timer].brb & 0xff;
1334       break;
1335    }
1336 
1337    assert(0);
1338    return 0;
1339 }
1340 
onchip_write_timer_word(struct Onchip * regs,u32 addr,int which_timer,u16 data)1341 void onchip_write_timer_word(struct Onchip * regs, u32 addr, int which_timer, u16 data)
1342 {
1343    switch (addr)
1344    {
1345    case 0:
1346    case 1:
1347    case 2:
1348    case 3:
1349       //byte access only
1350       return;
1351       break;
1352    case 4:
1353       regs->itu.channel[which_timer].tcnt = data;
1354       return;
1355       break;
1356    case 6:
1357       regs->itu.channel[which_timer].gra = data;
1358       return;
1359       break;
1360    case 8:
1361       regs->itu.channel[which_timer].grb = data;
1362       return;
1363       break;
1364    case 0xa:
1365       regs->itu.channel[which_timer].bra = data;
1366       return;
1367       break;
1368    case 0xc:
1369       regs->itu.channel[which_timer].brb = data;
1370       return;
1371       break;
1372    }
1373 
1374    assert(0);
1375 }
1376 
onchip_write_byte(struct Onchip * regs,u32 addr,u8 data)1377 void onchip_write_byte(struct Onchip * regs, u32 addr, u8 data)
1378 {
1379    CDTRACE("wbreg: %08X %02X\n", addr, data);
1380 
1381    print_serial(0);
1382 
1383    if (addr == 0x5FFFF25)
1384    {
1385       int q = 1;
1386    }
1387    if (addr >= 0x5FFFE00 && addr <= 0x5FFFEBF)
1388    {
1389       //unmapped
1390       return;
1391    }
1392    //sci
1393    else if (addr >= 0x5FFFEC0 && addr <= 0x5FFFECD)
1394    {
1395       switch (addr - 0x5FFFEC0)
1396       {
1397       case 0:
1398          regs->sci[0].smr = data;
1399          return;
1400          break;
1401       case 1:
1402          regs->sci[0].brr = data;
1403          return;
1404          break;
1405       case 2:
1406          regs->sci[0].scr = data;
1407 
1408          if((data & SCI_TE ) == 0)
1409             regs->sci[0].ssr |= SCI_TEND;//tend is set
1410          return;
1411          break;
1412       case 3:
1413          regs->sci[0].tdr = data;
1414          if (regs->sci[0].tsr_counter == 0) {  // If TSR empty, load it immediately
1415              regs->sci[0].tsr = data;
1416              regs->sci[0].tsr_counter = 8;
1417              regs->sci[0].ssr |= SCI_TDRE;
1418          } else {
1419              regs->sci[0].tdr_written = 1; // flag TDR as pending for next time TSR empties
1420              regs->sci[0].ssr &= ~SCI_TDRE;
1421          }
1422 
1423          return;
1424          break;
1425       case 4:
1426       {
1427          if (data == 0)
1428          {
1429             int clear_te = 0;
1430             if (regs->sci[0].ssr & SCI_TDRE)
1431                clear_te = 1;
1432             regs->sci[0].ssr &= 0x6;//save tend/mpb bits (read only)
1433 
1434             //tend is cleared when software
1435             //reads tdre after it has been set to 1
1436             //then writes 0 in tdre
1437             if(clear_te)
1438                regs->sci[0].ssr &= ~SCI_TEND;
1439             return;
1440          }
1441          else
1442             assert(0);
1443 
1444       }
1445          return;
1446          break;
1447       case 5:
1448          //read only
1449          return;
1450          break;
1451       case 6:
1452          //nothing
1453          return;
1454          break;
1455       case 7:
1456          //nothing
1457          return;
1458          break;
1459       case 8:
1460          regs->sci[1].smr = data;
1461          return;
1462          break;
1463       case 9:
1464          regs->sci[1].brr = data;
1465          return;
1466          break;
1467       case 0xa:
1468          regs->sci[1].scr = data;
1469          return;
1470          break;
1471       case 0xb:
1472          regs->sci[1].tdr = data;
1473          regs->sci[1].tdr_written = 1;//data is present to transmit
1474          return;
1475          break;
1476       case 0xc:
1477          if (data == 0)//only 0 can be written
1478             regs->sci[1].ssr = data;
1479          return;
1480          break;
1481       case 0xd:
1482          //read only
1483          return;
1484          break;
1485       case 0xe:
1486       case 0xf:
1487          //nothing
1488          return;
1489          break;
1490       }
1491    }
1492    else if (addr >= 0x5FFFECE && addr <= 0x5FFFEDF)
1493    {
1494       //unmapped
1495       return;
1496    }
1497    else if (addr >= 0x5FFFEE0 && addr <= 0x5FFFEEF)
1498    {
1499       //a/d
1500       //read only
1501       return;
1502    }
1503    else if (addr >= 0x5FFFEF0 && addr <= 0x5FFFEFF)
1504    {
1505       //unmapped
1506       return;
1507    }
1508    else if (addr >= 0x5FFFF00 && addr <= 0x5FFFF03)
1509    {
1510       switch (addr - 0x5FFFF00)
1511       {
1512       case 0:
1513          regs->itu.tstr = data;
1514          return;
1515       case 1:
1516          regs->itu.tsnc = data;
1517          return;
1518       case 2:
1519          regs->itu.tmdr = data;
1520          return;
1521       case 3:
1522          regs->itu.tfcr = data;
1523          return;
1524       }
1525    }
1526    //timer writes
1527    else if (addr >= 0x5FFFF04 && addr <= 0x5FFFF3F)
1528    {
1529       if (addr <= 0x5FFFF0D)
1530          onchip_write_timer_byte(regs, addr - 0x5FFFF04, 0, data);
1531       else if (addr <= 0x5FFFF17)
1532          onchip_write_timer_byte(regs, addr - 0x5FFFF0E, 1, data);
1533       else if (addr <= 0x5FFFF21)
1534          onchip_write_timer_byte(regs, addr - 0x5FFFF18, 2, data);
1535       else if (addr <= 0x5FFFF2F)
1536          onchip_write_timer_byte(regs, addr - 0x5FFFF22, 3, data);
1537       else if (addr == 0x5FFFF30)
1538       {
1539          return;//unmapped
1540       }
1541       else if (addr == 0x5FFFF31)
1542       {
1543          regs->itu.tocr = data;
1544          return;
1545       }
1546       else
1547          onchip_write_timer_byte(regs, addr - 0x5FFFF32, 4, data);
1548       return;
1549    }
1550    else if (addr >= 0x5FFFF40 && addr <= 0x5FFFF7F)
1551    {
1552       if (addr == 0x5FFFF4e)
1553       {
1554          regs->dmac.channel[0].chcr = (regs->dmac.channel[0].chcr & 0xff) | data << 8;
1555          return;
1556       }
1557       if (addr == 0x5FFFF4F)
1558       {
1559          regs->dmac.channel[0].chcr = (regs->dmac.channel[0].chcr & 0xff00) | (data & 0xfd);
1560          return;
1561       }
1562       if (addr == 0x5FFFF5e)
1563       {
1564          regs->dmac.channel[1].chcr = (regs->dmac.channel[1].chcr & 0xff) | data << 8;
1565          return;
1566       }
1567       if (addr == 0x5FFFF5F)
1568       {
1569          regs->dmac.channel[1].chcr = (regs->dmac.channel[1].chcr & 0xff00) | (data & 0xfd);
1570          return;
1571       }
1572       if (addr == 0x5FFFF6e)
1573       {
1574          regs->dmac.channel[2].chcr = (regs->dmac.channel[2].chcr & 0xff) | data << 8;
1575          return;
1576       }
1577       if (addr == 0x5FFFF6F)
1578       {
1579          regs->dmac.channel[2].chcr = (regs->dmac.channel[2].chcr & 0xff00) | (data & 0xfd);
1580          return;
1581       }
1582       if (addr == 0x5FFFF7e)
1583       {
1584          regs->dmac.channel[3].chcr = (regs->dmac.channel[3].chcr & 0xff) | data << 8;
1585          return;
1586       }
1587       if (addr == 0x5FFFF7F)
1588       {
1589          regs->dmac.channel[3].chcr = (regs->dmac.channel[3].chcr & 0xff00) | (data & 0xfd);
1590          return;
1591       }
1592       //dmac
1593 
1594       //rest is inaccessible from byte writes
1595       return;
1596    }
1597    else if (addr >= 0x5FFFF80 && addr <= 0x5FFFF8F)
1598    {
1599       //intc
1600 
1601       switch (addr - 0x5FFFF80)
1602       {
1603       case 0:
1604       case 1:
1605       case 2:
1606       case 3:
1607          return;
1608          break;
1609       //ipra
1610       case 4:
1611          regs->intc.ipra = (regs->intc.ipra & 0xff) | data << 8;
1612          return;
1613          break;
1614       case 5:
1615          regs->intc.ipra = (regs->intc.ipra & 0xff00) | data;
1616          return;
1617          break;
1618       //iprb
1619       case 6:
1620          regs->intc.iprb = (regs->intc.iprb & 0xff) | data << 8;
1621          return;
1622          break;
1623       case 7:
1624          regs->intc.iprb = (regs->intc.iprb & 0xff00) | data;
1625          return;
1626          break;
1627       //iprc
1628       case 8:
1629          regs->intc.iprc = (regs->intc.iprc & 0xff) | data << 8;
1630          return;
1631          break;
1632       case 9:
1633          regs->intc.iprc = (regs->intc.iprc & 0xff00) | data;
1634          return;
1635          break;
1636       //iprd
1637       case 0xa:
1638          regs->intc.iprd = (regs->intc.iprd & 0xff) | data << 8;
1639          return;
1640          break;
1641       case 0xb:
1642          regs->intc.iprd = (regs->intc.iprd & 0xff00) | data;
1643          return;
1644          break;
1645       //ipre
1646       case 0xc:
1647          regs->intc.ipre = (regs->intc.ipre & 0xff) | data << 8;
1648          return;
1649          break;
1650       case 0xd:
1651          regs->intc.ipre = (regs->intc.ipre & 0xff00) | data;
1652          return;
1653          break;
1654       //icr
1655       case 0xe:
1656          regs->intc.icr = (regs->intc.icr & 0xff) | data << 8;
1657          return;
1658          break;
1659       case 0xf:
1660          regs->intc.icr = (regs->intc.icr & 0xff00) | data;
1661          return;
1662          break;
1663       }
1664    }
1665    else if (addr >= 0x5FFFF90 && addr <= 0x5FFFF99)
1666    {
1667       //ubc
1668       switch (addr - 0x5FFFF90)
1669       {
1670       //bar
1671       case 0:
1672          regs->ubc.bar = (regs->ubc.bar & 0x00ffffff) | data << 24;
1673          return;
1674          break;
1675       case 1:
1676          regs->ubc.bar = (regs->ubc.bar & 0xff00ffff) | data << 16;
1677          return;
1678          break;
1679       case 2:
1680          regs->ubc.bar = (regs->ubc.bar & 0xffff00ff) | data << 8;
1681          return;
1682          break;
1683       case 3:
1684          regs->ubc.bar = (regs->ubc.bar & 0xffffff00) | data;
1685          return;
1686          break;
1687       //bamr
1688       case 4:
1689          regs->ubc.bamr = (regs->ubc.bamr & 0x00ffffff) | data << 24;
1690          return;
1691          break;
1692       case 5:
1693          regs->ubc.bamr = (regs->ubc.bamr & 0xff00ffff) | data << 16;
1694          return;
1695          break;
1696       case 6:
1697          regs->ubc.bamr = (regs->ubc.bamr & 0xffff00ff) | data << 8;
1698          return;
1699          break;
1700       case 7:
1701          regs->ubc.bamr = (regs->ubc.bamr & 0xffffff00) | data;
1702          return;
1703          break;
1704       //bbr
1705       case 8:
1706          regs->ubc.bbr = (regs->ubc.bar & 0x00ff) | data << 8;
1707          return;
1708          break;
1709       case 9:
1710          regs->ubc.bbr = (regs->ubc.bar & 0xff00) | data;
1711          return;
1712          break;
1713       }
1714    }
1715    else if (addr >= 0x5FFFF9A && addr <= 0x5FFFF9F)
1716    {
1717       //unmapped
1718       return;
1719    }
1720    else if (addr >= 0x5FFFFA0 && addr <= 0x5FFFFB3)
1721    {
1722       //bsc
1723       switch (addr - 0x5FFFFA0)
1724       {
1725       case 0:
1726          regs->bsc.bcr = (regs->bsc.bcr & 0x00ff) | data << 8;
1727          return;
1728          break;
1729       case 1:
1730          regs->bsc.bcr = (regs->bsc.bcr & 0xff00) | data;
1731          return;
1732          break;
1733       case 2:
1734          regs->bsc.wcr1 = (regs->bsc.wcr1 & 0x00ff) | data << 8;
1735          return;
1736          break;
1737       case 3:
1738          regs->bsc.wcr1 = (regs->bsc.wcr1 & 0xff00) | data;
1739          return;
1740          break;
1741       case 4:
1742          regs->bsc.wcr2 = (regs->bsc.wcr2 & 0x00ff) | data << 8;
1743          return;
1744          break;
1745       case 5:
1746          regs->bsc.wcr2 = (regs->bsc.wcr2 & 0xff00) | data;
1747          return;
1748          break;
1749       case 6:
1750          regs->bsc.wcr3 = (regs->bsc.wcr3 & 0x00ff) | data << 8;
1751          return;
1752          break;
1753       case 7:
1754          regs->bsc.wcr3 = (regs->bsc.wcr3 & 0xff00) | data;
1755          return;
1756          break;
1757       case 8:
1758          regs->bsc.dcr = (regs->bsc.dcr & 0x00ff) | data << 8;
1759          return;
1760          break;
1761       case 9:
1762          regs->bsc.dcr = (regs->bsc.dcr & 0xff00) | data;
1763          return;
1764          break;
1765       case 0xa:
1766          regs->bsc.pcr = (regs->bsc.pcr & 0x00ff) | data << 8;
1767          return;
1768          break;
1769       case 0xb:
1770          regs->bsc.pcr = (regs->bsc.pcr & 0xff00) | data;
1771          return;
1772          break;
1773       case 0xc:
1774          regs->bsc.rcr = (regs->bsc.rcr & 0x00ff) | data << 8;
1775          return;
1776          break;
1777       case 0xd:
1778          regs->bsc.rcr = (regs->bsc.rcr & 0xff00) | data;
1779          return;
1780          break;
1781       case 0xe:
1782          regs->bsc.rtcsr = (regs->bsc.rtcsr & 0x00ff) | data << 8;
1783          return;
1784          break;
1785       case 0xf:
1786          regs->bsc.rtcsr = (regs->bsc.rtcsr & 0xff00) | data;
1787          return;
1788          break;
1789       //rtcnt
1790       case 0x10:
1791          regs->bsc.rtcnt = (regs->bsc.rtcnt & 0x00ff) | data << 8;
1792          return;
1793          break;
1794       case 0x11:
1795          regs->bsc.rtcnt = (regs->bsc.rtcnt & 0xff00) | data;
1796          return;
1797          break;
1798       //rtcor
1799       case 0x12:
1800          regs->bsc.rtcor = (regs->bsc.rtcor & 0x00ff) | data << 8;
1801          return;
1802          break;
1803       case 0x13:
1804          regs->bsc.rtcor = (regs->bsc.rtcor & 0xff00) | data;
1805          return;
1806          break;
1807       }
1808    }
1809    else if (addr >= 0x5FFFFb4 && addr <= 0x5FFFFb7)
1810    {
1811       //unmapped
1812       return;
1813    }
1814    else if (addr >= 0x5FFFFB8 && addr <= 0x5FFFFBB)
1815    {
1816       //wdt
1817       //TODO
1818       return;
1819    }
1820    else if (addr == 0x5FFFFbc)
1821    {
1822       regs->sbycr = data;
1823       return;
1824    }
1825    else if (addr >= 0x5FFFFBD && addr <= 0x5FFFFBF)
1826    {
1827       //unmapped
1828       return;
1829    }
1830    else if (addr >= 0x5FFFFC0 && addr <= 0x5FFFFC3)
1831    {
1832       //port a / b
1833 
1834       switch (addr - 0x5FFFFC0)
1835       {
1836       case 0:
1837          regs->padr = (regs->padr & 0x00ff) | data << 8;
1838          return;
1839          break;
1840       case 1:
1841          regs->padr = (regs->padr & 0xff00) | data;
1842          return;
1843          break;
1844       case 2:
1845          regs->pbdr = (regs->pbdr & 0x00ff) | data << 8;
1846          return;
1847          break;
1848       case 3:
1849          regs->pbdr = (regs->pbdr & 0xff00) | data;
1850          return;
1851          break;
1852       }
1853    }
1854    else if (addr >= 0x5FFFFC4 && addr <= 0x5FFFFCF)
1855    {
1856       //pfc
1857 
1858       switch (addr - 0x5FFFFC0)
1859       {
1860       //paior
1861       case 4:
1862          regs->pfc.paior = (regs->pfc.paior & 0x00ff) | data << 8;
1863          return;
1864          break;
1865       case 5:
1866          regs->pfc.paior = (regs->pfc.paior & 0xff00) | data;
1867          return;
1868          break;
1869       //pbior
1870       case 6:
1871          regs->pfc.pbior = (regs->pfc.pbior & 0x00ff) | data << 8;
1872          return;
1873          break;
1874       case 7:
1875          regs->pfc.pbior = (regs->pfc.pbior & 0xff00) | data;
1876          return;
1877          break;
1878       //pacr1
1879       case 8:
1880          regs->pfc.pacr1 = (regs->pfc.pacr1 & 0x00ff) | data << 8;
1881          return;
1882          break;
1883       case 9:
1884          regs->pfc.pacr1 = (regs->pfc.pacr1 & 0xff00) | data;
1885          return;
1886          break;
1887       //pacr2
1888       case 0xa:
1889          regs->pfc.pacr2 = (regs->pfc.pacr2 & 0x00ff) | data << 8;
1890          return;
1891          break;
1892       case 0xb:
1893          regs->pfc.pacr2 = (regs->pfc.pacr2 & 0xff00) | data;
1894          return;
1895          break;
1896       //pbcr1
1897       case 0xc:
1898          regs->pfc.pbcr1 = (regs->pfc.pbcr1 & 0x00ff) | data << 8;
1899          return;
1900          break;
1901       case 0xd:
1902          regs->pfc.pbcr1 = (regs->pfc.pbcr1 & 0xff00) | data;
1903          return;
1904          break;
1905       //pbcr2
1906       case 0xe:
1907          regs->pfc.pbcr2 = (regs->pfc.pbcr2 & 0x00ff) | data << 8;
1908          return;
1909          break;
1910       case 0xf:
1911          regs->pfc.pbcr2 = (regs->pfc.pbcr2 & 0xff00) | data;
1912          return;
1913          break;
1914       }
1915    }
1916    else if (addr >= 0x5FFFFD0 && addr <= 0x5FFFFD1)
1917    {
1918       //port a / b
1919 
1920       switch (addr - 0x5FFFFD0)
1921       {
1922       case 0:
1923          regs->pcdr = (regs->pcdr & 0x00ff) | data << 8;
1924          return;
1925          break;
1926       case 1:
1927          regs->pcdr = (regs->pcdr & 0xff00) | data;
1928          return;
1929          break;
1930       }
1931    }
1932    else if (addr >= 0x5FFFFD2 && addr <= 0x5FFFFED)
1933    {
1934       //unmapped
1935       return;
1936    }
1937    else if (addr == 0x5FFFFEE)
1938    {
1939       //cascr
1940       regs->cascr = data;
1941       return;
1942    }
1943    else if (addr == 0x5FFFFEF)
1944    {
1945       //unmapped
1946       return;
1947    }
1948    else if (addr >= 0x5FFFFF0 && addr <= 0x5FFFFF7)
1949    {
1950       //tpc
1951       switch (addr - 0x5FFFFF0)
1952       {
1953       case 0:
1954          regs->tpc.tpmr = data;
1955          return;
1956       case 1:
1957          regs->tpc.tpcr = data;
1958          return;
1959       case 2:
1960          regs->tpc.nderb = data;
1961          return;
1962       case 3:
1963          regs->tpc.ndera = data;
1964          return;
1965       case 4:
1966          regs->tpc.ndrb = data;
1967          return;
1968       case 5:
1969          regs->tpc.ndra = data;
1970          return;
1971       case 6:
1972          regs->tpc.ndrb = data;
1973          return;
1974       case 7:
1975          regs->tpc.ndra = data;
1976          return;
1977       }
1978    }
1979    else if (addr >= 0x5FFFFF8 && addr <= 0x5FFFFFF)
1980    {
1981       //unmapped
1982       return;
1983    }
1984 
1985    assert(0);
1986 }
1987 
onchip_sci_read_byte(struct Onchip * regs,u32 addr,int which)1988 u8 onchip_sci_read_byte(struct Onchip * regs, u32 addr, int which)
1989 {
1990    switch (addr)
1991    {
1992    case 0:
1993       return regs->sci[which].smr;
1994    case 1:
1995       return regs->sci[which].brr;
1996    case 2:
1997       return regs->sci[which].scr;
1998    case 3:
1999       return regs->sci[which].tdr;
2000    case 4:
2001       return regs->sci[which].ssr;
2002    case 5:
2003       return regs->sci[which].rdr;
2004    }
2005 
2006    assert(0);
2007 
2008    return 0;
2009 }
2010 
onchip_read_byte(struct Onchip * regs,u32 addr)2011 u8 onchip_read_byte(struct Onchip * regs, u32 addr)
2012 {
2013    CDTRACE("rbreg: %08X \n", addr);
2014    if (addr >= 0x5FFFE00 && addr <= 0x5FFFEBF)
2015    {
2016       //unmapped
2017       return 0;
2018    }
2019    //sci
2020    else if (addr >= 0x5FFFEC0 && addr <= 0x5FFFECD)
2021    {
2022       if (addr >= 0x5FFFEC0 && addr <= 0x5FFFEC5)
2023       {
2024          //channel 0
2025          return onchip_sci_read_byte(regs, addr - 0x5FFFEC0, 0);
2026       }
2027       else if (addr >= 0x5FFFEC6 && addr <= 0x5FFFEC7)
2028       {
2029          return 0;//unmapped
2030       }
2031       else if (addr >= 0x5FFFEC8 && addr <= 0x5FFFECD)
2032       {
2033          //channel 1
2034          return onchip_sci_read_byte(regs, addr - 0x5FFFEC8, 1);
2035       }
2036       else if (addr >= 0x5FFFECE && addr <= 0x5FFFECF)
2037       {
2038          return 0;//unmapped
2039       }
2040    }
2041    else if (addr >= 0x5FFFECE && addr <= 0x5FFFEDF)
2042    {
2043       //unmapped
2044       return 0;
2045    }
2046    else if (addr >= 0x5FFFEE0 && addr <= 0x5FFFEE9)
2047    {
2048       //a/d
2049       switch (addr - 0x5FFFEE0)
2050       {
2051       //addra
2052       case 0:
2053          return (regs->addra & 0xff00) >> 8;
2054          break;
2055       case 1:
2056          return regs->addra & 0xff;
2057          break;
2058       //addrb
2059       case 2:
2060          return (regs->addrb & 0xff00) >> 8;
2061          break;
2062       case 3:
2063          return regs->addrb & 0xff;
2064          break;
2065       //addrc
2066       case 4:
2067          return (regs->addrc & 0xff00) >> 8;
2068          break;
2069       case 5:
2070          return regs->addrc & 0xff;
2071          break;
2072       //addrd
2073       case 6:
2074          return (regs->addrd & 0xff00) >> 8;
2075          break;
2076       case 7:
2077          return regs->addrd & 0xff;
2078          break;
2079       case 8:
2080          return regs->adcsr;
2081          break;
2082       case 9:
2083          return regs->adcr;
2084          break;
2085       }
2086    }
2087    else if (addr >= 0x5FFFEEa && addr <= 0x5FFFEEf)
2088    {
2089       return 0;//unmapped
2090    }
2091    else if (addr >= 0x5FFFEF0 && addr <= 0x5FFFEFF)
2092    {
2093       //unmapped
2094       return 0;
2095    }
2096    else if (addr >= 0x5FFFF00 && addr <= 0x5FFFF03)
2097    {
2098       //itu shared
2099       switch (addr - 0x5FFFF00)
2100       {
2101       case 0:
2102          return regs->itu.tstr;
2103       case 1:
2104          return regs->itu.tsnc;
2105       case 2:
2106          return regs->itu.tmdr;
2107       case 3:
2108          return regs->itu.tfcr;
2109       }
2110    }
2111    //timer
2112    else if (addr >= 0x5FFFF04 && addr <= 0x5FFFF3F)
2113    {
2114       if (addr <= 0x5FFFF0D)
2115          return onchip_read_timer_byte(regs, addr - 0x5FFFF04, 0);
2116       else if (addr >= 0x5FFFF0e && addr <= 0x5FFFF17)
2117          return onchip_read_timer_byte(regs, addr - 0x5FFFF0E, 1);
2118       else if (addr >= 0x5FFFF18 && addr <= 0x5FFFF21)
2119          return onchip_read_timer_byte(regs, addr - 0x5FFFF18, 2);
2120       else if (addr >= 0x5FFFF22 && addr <= 0x5FFFF2F)
2121          return onchip_read_timer_byte(regs, addr - 0x5FFFF22, 3);
2122       else if (addr >= 0x5FFFF32 && addr <= 0x5FFFF3F)
2123          return onchip_read_timer_byte(regs, addr - 0x5FFFF32, 4);
2124 
2125       if (addr == 0x05ffff30)
2126          return 0;//unmapped
2127 
2128       if (addr == 0x05ffff31)
2129          return regs->itu.tocr;
2130    }
2131    else if (addr >= 0x5FFFF40 && addr <= 0x5FFFF7F)
2132    {
2133       //dmac
2134       if (addr == 0x5FFFF4E)
2135          return regs->dmac.channel[0].chcr >> 8;
2136       else if (addr == 0x5FFFF4F)
2137          return regs->dmac.channel[0].chcr & 0xff;
2138 
2139       if (addr == 0x5FFFF48)
2140          return regs->dmac.dmaor >> 8;
2141       else if (addr == 0x5FFFF49)
2142          return regs->dmac.dmaor & 0xff;
2143 
2144       if (addr == 0x5FFFF5E)
2145          return regs->dmac.channel[1].chcr >> 8;
2146       else if (addr == 0x5FFFF5F)
2147          return regs->dmac.channel[1].chcr & 0xff;
2148 
2149       if (addr == 0x5FFFF6E)
2150          return regs->dmac.channel[2].chcr >> 8;
2151       else if (addr == 0x5FFFF6F)
2152          return regs->dmac.channel[2].chcr & 0xff;
2153 
2154       if (addr == 0x5FFFF7E)
2155          return regs->dmac.channel[3].chcr >> 8;
2156       else if (addr == 0x5FFFF7F)
2157          return regs->dmac.channel[3].chcr & 0xff;
2158 
2159       //the rest is inacessible
2160       return 0;
2161    }
2162    else if (addr >= 0x5FFFF80 && addr <= 0x5FFFF83)
2163    {
2164       //unmapped?
2165       return 0;
2166    }
2167    else if (addr >= 0x5FFFF84 && addr <= 0x5FFFF8F)
2168    {
2169       //intc
2170       switch (addr - 0x5FFFF80)
2171       {
2172       case 0:
2173       case 1:
2174       case 2:
2175       case 3:
2176          assert(0);
2177          break;
2178          //ipra
2179       case 4:
2180          return regs->intc.ipra >> 8;
2181       case 5:
2182          return regs->intc.ipra & 0xff;
2183          //iprb
2184       case 6:
2185          return regs->intc.iprb >> 8;
2186       case 7:
2187          return regs->intc.iprb & 0xff;
2188          //iprc
2189       case 8:
2190          return regs->intc.iprc >> 8;
2191       case 9:
2192          return regs->intc.iprc & 0xff;
2193          //iprd
2194       case 0xa:
2195          return regs->intc.iprd >> 8;
2196       case 0xb:
2197          return regs->intc.iprd & 0xff;
2198          //ipre
2199       case 0xc:
2200          return regs->intc.ipre >> 8;
2201       case 0xd:
2202          return regs->intc.ipre & 0xff;
2203          //icr
2204       case 0xe:
2205          return regs->intc.icr >> 8;
2206       case 0xf:
2207          return regs->intc.icr & 0xff;
2208       }
2209    }
2210    else if (addr >= 0x5FFFF90 && addr <= 0x5FFFF99)
2211    {
2212       //ubc
2213       switch (addr - 0x5FFFF90)
2214       {
2215          //bar
2216       case 0:
2217          return regs->ubc.bar & 0xff000000 >> 24;
2218       case 1:
2219          return regs->ubc.bar & 0x00ff0000 >> 16;
2220       case 2:
2221          return regs->ubc.bar & 0x0000ff00 >> 8;
2222       case 3:
2223          return regs->ubc.bar & 0x000000ff >> 0;
2224          //bamr
2225       case 4:
2226          return regs->ubc.bamr & 0xff000000 >> 24;
2227       case 5:
2228          return regs->ubc.bamr & 0x00ff0000 >> 16;
2229       case 6:
2230          return regs->ubc.bamr & 0x0000ff00 >> 8;
2231       case 7:
2232          return regs->ubc.bamr & 0x000000ff >> 0;
2233          //bbr
2234       case 8:
2235          return regs->ubc.bbr >> 8;
2236       case 9:
2237          return regs->ubc.bbr & 0xff;
2238       }
2239    }
2240    else if (addr >= 0x5FFFF9A && addr <= 0x5FFFF9F)
2241    {
2242       //unmapped
2243       return 0;
2244    }
2245    else if (addr >= 0x5FFFFA0 && addr <= 0x5FFFFB3)
2246    {
2247       //bsc
2248       switch (addr - 0x5FFFFA0)
2249       {
2250       case 0:
2251          return regs->bsc.bcr >> 8;
2252       case 1:
2253          return regs->bsc.bcr & 0xff;
2254       case 2:
2255          return regs->bsc.wcr1 >> 8;
2256       case 3:
2257          return regs->bsc.wcr1 & 0xff;
2258       case 4:
2259          return regs->bsc.wcr2 >> 8;
2260       case 5:
2261          return regs->bsc.wcr2 & 0xff;
2262       case 6:
2263          return regs->bsc.wcr3 >> 8;
2264       case 7:
2265          return regs->bsc.wcr3 & 0xff;
2266       case 8:
2267          return regs->bsc.dcr >> 8;
2268       case 9:
2269          return regs->bsc.dcr & 0xff;
2270       case 0xa:
2271          return regs->bsc.pcr >> 8;
2272       case 0xb:
2273          return regs->bsc.pcr & 0xff;
2274       case 0xc:
2275          return regs->bsc.rcr >> 8;
2276       case 0xd:
2277          return regs->bsc.rcr & 0xff;
2278       case 0xe:
2279          return regs->bsc.rtcsr >> 8;
2280       case 0xf:
2281          return regs->bsc.rtcsr & 0xff;
2282          //rtcnt
2283       case 0x10:
2284          return regs->bsc.rtcnt >> 8;
2285       case 0x11:
2286          return regs->bsc.rtcnt & 0xff;
2287          //rtcor
2288       case 0x12:
2289          return regs->bsc.rtcor >> 8;
2290       case 0x13:
2291          return regs->bsc.rtcor & 0xff;
2292       }
2293    }
2294    else if (addr >= 0x5FFFFb4 && addr <= 0x5FFFFb7)
2295    {
2296       //unmapped
2297       return 0;
2298    }
2299    else if (addr >= 0x5FFFFB8 && addr <= 0x5FFFFBB)
2300    {
2301       //wdt
2302       //TODO
2303       return 0;
2304    }
2305    else if (addr == 0x5FFFFbc)
2306    {
2307       //sbycr
2308       return regs->sbycr;
2309    }
2310    else if (addr >= 0x5FFFFBD && addr <= 0x5FFFFBF)
2311    {
2312       //unmapped
2313       return 0;
2314    }
2315    else if (addr >= 0x5FFFFC0 && addr <= 0x5FFFFC3)
2316    {
2317       //port a/b data reg
2318       switch (addr - 0x5FFFFC0)
2319       {
2320       case 0:
2321          return regs->padr >> 8;
2322       case 1:
2323          return regs->padr & 0xff;
2324       case 2:
2325          return regs->pbdr >> 8;
2326       case 3:
2327          return regs->pbdr & 0xff;
2328       }
2329    }
2330    else if (addr >= 0x5FFFFC4 && addr <= 0x5FFFFCF)
2331    {
2332       //pfc
2333       switch (addr - 0x5FFFFC0)
2334       {
2335       //paior
2336       case 4:
2337          return regs->pfc.paior >> 8;
2338       case 5:
2339          return regs->pfc.paior & 0xff;
2340          //pbior
2341       case 6:
2342          return regs->pfc.pbior >> 8;
2343       case 7:
2344          return regs->pfc.pbior & 0xff;
2345          //pacr1
2346       case 8:
2347          return regs->pfc.pacr1 >> 8;
2348       case 9:
2349          return regs->pfc.pacr1 & 0xff;
2350          //pacr2
2351       case 0xa:
2352          return regs->pfc.pacr2 >> 8;
2353       case 0xb:
2354          return regs->pfc.pacr2 & 0xff;
2355          //pbcr1
2356       case 0xc:
2357          return regs->pfc.pbcr1 >> 8;
2358       case 0xd:
2359          return regs->pfc.pbcr1 & 0xff;
2360          //pbcr2
2361       case 0xe:
2362          return regs->pfc.pbcr2 >> 8;
2363       case 0xf:
2364          return regs->pfc.pbcr2 & 0xff;
2365       }
2366    }
2367    else if (addr == 0x5FFFFD0)
2368    {
2369       return regs->pcdr >> 8;
2370    }
2371    else if (addr == 0x5FFFFD1)
2372    {
2373       return regs->pcdr & 0xff;
2374    }
2375    else if (addr >= 0x5FFFFD2 && addr <= 0x5FFFFED)
2376    {
2377       //unmapped
2378       return 0;
2379    }
2380    else if (addr == 0x5FFFFEE)
2381    {
2382       //cascr
2383       return regs->cascr >> 8;
2384    }
2385    else if (addr == 0x5FFFFEF)
2386    {
2387       return regs->cascr & 0xff;
2388    }
2389    else if (addr >= 0x5FFFFF0 && addr <= 0x5FFFFF7)
2390    {
2391       //tpc
2392       switch (addr - 0x5FFFFF0)
2393       {
2394       case 0:
2395          return regs->tpc.tpmr;
2396       case 1:
2397          return regs->tpc.tpcr;
2398       case 2:
2399          return regs->tpc.nderb;
2400       case 3:
2401          return regs->tpc.ndera;
2402       case 4:
2403          return regs->tpc.ndrb;
2404       case 5:
2405          return regs->tpc.ndra;
2406       case 6:
2407          return regs->tpc.ndrb;
2408       case 7:
2409          return regs->tpc.ndra;
2410       }
2411    }
2412    else if (addr >= 0x5FFFFF8 && addr <= 0x5FFFFFF)
2413    {
2414       //unmapped
2415       return 0;
2416    }
2417 
2418    assert(0);
2419 
2420    return 0;
2421 }
2422 
onchip_sci_write_word(struct Onchip * regs,u32 addr,int which,u16 data)2423 void onchip_sci_write_word(struct Onchip * regs, u32 addr, int which, u16 data)
2424 {
2425    switch (addr)
2426    {
2427    case 0:
2428       regs->sci[which].smr = data >> 8;
2429       regs->sci[which].brr = data & 0xff;
2430       return;
2431    case 2:
2432       regs->sci[which].scr = data >> 8;
2433       regs->sci[which].tdr = data & 0xff;
2434       return;
2435    case 4:
2436       regs->sci[which].ssr = data >> 8;
2437       //rdr is read only
2438       return;
2439    }
2440 
2441    assert(0);
2442 }
2443 
onchip_dmac_write_word(struct Onchip * regs,u32 addr,int which,u16 data)2444 void onchip_dmac_write_word(struct Onchip * regs, u32 addr, int which, u16 data)
2445 {
2446    switch (addr)
2447    {
2448    case 0:
2449       regs->dmac.channel[which].sar = (regs->dmac.channel[which].sar & 0x0000ffff) | data << 16;
2450       return;
2451    case 2:
2452       regs->dmac.channel[which].sar = (regs->dmac.channel[which].sar & 0xffff0000) | data;
2453       return;
2454    case 4:
2455       regs->dmac.channel[which].dar = (regs->dmac.channel[which].dar & 0x0000ffff) | data << 16;
2456       return;
2457    case 6:
2458       regs->dmac.channel[which].dar = (regs->dmac.channel[which].dar & 0xffff0000) | data;
2459       return;
2460    case 8:
2461       //unmapped
2462       return;
2463    case 0xa:
2464       regs->dmac.channel[which].tcr = data;
2465       return;
2466    case 0xc:
2467       //unmapped
2468       return;
2469    case 0xe:
2470       regs->dmac.channel[which].chcr = data & 0xfffd;
2471       return;
2472    }
2473 
2474    assert(0);
2475 }
2476 
onchip_write_word(struct Onchip * regs,u32 addr,u16 data)2477 void onchip_write_word(struct Onchip * regs, u32 addr, u16 data)
2478 {
2479    print_serial(0);
2480    CDTRACE("wwreg: %08X %04X\n", addr, data);
2481    if (addr >= 0x5FFFE00 && addr <= 0x5FFFEBF)
2482    {
2483       //unmapped
2484       return;
2485    }
2486    //sci
2487    else if (addr >= 0x5FFFEC0 && addr <= 0x5FFFECD)
2488    {
2489       if (addr >= 0x5FFFEC0 && addr <= 0x5FFFEC5)
2490       {
2491          //channel 0
2492          onchip_sci_write_word(regs, addr - 0x5FFFEC0, 0, data);
2493          return;
2494       }
2495       else if (addr >= 0x5FFFEC6 && addr <= 0x5FFFEC7)
2496       {
2497          return;//unmapped
2498       }
2499       else if (addr >= 0x5FFFEC8 && addr <= 0x5FFFECD)
2500       {
2501          //channel 1
2502          onchip_sci_write_word(regs, addr - 0x5FFFEC8, 1, data);
2503          return;
2504       }
2505       else if (addr >= 0x5FFFECE && addr <= 0x5FFFECF)
2506       {
2507          return;//unmapped
2508       }
2509    }
2510    else if (addr >= 0x5FFFECE && addr <= 0x5FFFEDF)
2511    {
2512       //unmapped
2513       return;
2514    }
2515    else if (addr >= 0x5FFFEE0 && addr <= 0x5FFFEE9)
2516    {
2517       //a/d
2518       return;//read only
2519    }
2520    else if (addr >= 0x5FFFEEa && addr <= 0x5FFFEEf)
2521    {
2522       return;//unmapped
2523    }
2524    else if (addr >= 0x5FFFEF0 && addr <= 0x5FFFEFF)
2525    {
2526       //unmapped
2527       return;
2528    }
2529    else if (addr >= 0x5FFFF00 && addr <= 0x5FFFF3F)
2530    {
2531       if (addr >= 0x5FFFF00 && addr <= 0x5FFFF03)
2532       {
2533          //not 16-bit accessible
2534          return;
2535       }
2536       if (addr >= 0x5FFFF04 && addr <= 0x5FFFF07)
2537       {
2538          return;//not 16-bit accessible
2539       }
2540       if (addr >= 0x5FFFF0E && addr <= 0x5FFFF11)
2541       {
2542          return;//not 16-bit accessible
2543       }
2544       if (addr >= 0x5FFFF18 && addr <= 0x5FFFF1B)
2545       {
2546          return;//not 16-bit accessible
2547       }
2548       if (addr >= 0x5FFFF22 && addr <= 0x5FFFF25)
2549       {
2550          return;//not 16-bit accessible
2551       }
2552       if (addr >= 0x5FFFF32 && addr <= 0x5FFFF35)
2553       {
2554          return;//not 16-bit accessible
2555       }
2556 
2557       if (addr == 0x5FFFF30)
2558       {
2559          //unmapped
2560          return;
2561       }
2562       //channel 0
2563       if (addr == 0x5FFFF08)
2564       {
2565          regs->itu.channel[0].tcnt = data;
2566          return;
2567       }
2568       else if (addr == 0x5FFFF0a)
2569       {
2570          regs->itu.channel[0].gra = data;
2571          return;
2572       }
2573       else if (addr == 0x5FFFF0c)
2574       {
2575          regs->itu.channel[0].grb = data;
2576          return;
2577       }
2578       //channel 1
2579       else if (addr == 0x5FFFF12)
2580       {
2581          regs->itu.channel[1].tcnt = data;
2582          return;
2583       }
2584       else if (addr == 0x5FFFF14)
2585       {
2586          regs->itu.channel[1].gra = data;
2587          return;
2588       }
2589       else if (addr == 0x5FFFF16)
2590       {
2591          regs->itu.channel[1].grb = data;
2592          return;
2593       }
2594       //channel 2
2595       else if (addr == 0x5FFFF1c)
2596       {
2597          regs->itu.channel[2].tcnt = data;
2598          return;
2599       }
2600       else if (addr == 0x5FFFF1e)
2601       {
2602          regs->itu.channel[2].gra = data;
2603          return;
2604       }
2605       else if (addr == 0x5FFFF20)
2606       {
2607          regs->itu.channel[2].grb = data;
2608          return;
2609       }
2610       //channel 3
2611       else if (addr == 0x5FFFF26)
2612       {
2613          regs->itu.channel[3].tcnt = data;
2614          return;
2615       }
2616       else if (addr == 0x5FFFF28)
2617       {
2618          regs->itu.channel[3].gra = data;
2619          return;
2620       }
2621       else if (addr == 0x5FFFF2a)
2622       {
2623          regs->itu.channel[3].grb = data;
2624          return;
2625       }
2626       else if (addr == 0x5FFFF2c)
2627       {
2628          regs->itu.channel[3].bra = data;
2629          return;
2630       }
2631       else if (addr == 0x5FFFF2e)
2632       {
2633          regs->itu.channel[3].brb = data;
2634          return;
2635       }
2636       //channel 4
2637       else if (addr == 0x5FFFF36)
2638       {
2639          regs->itu.channel[4].tcnt = data;
2640          return;
2641       }
2642       else if (addr == 0x5FFFF38)
2643       {
2644          regs->itu.channel[4].gra = data;
2645          return;
2646       }
2647       else if (addr == 0x5FFFF3a)
2648       {
2649          regs->itu.channel[4].grb = data;
2650          return;
2651       }
2652       else if (addr == 0x5FFFF3c)
2653       {
2654          regs->itu.channel[4].bra = data;
2655          return;
2656       }
2657       else if (addr == 0x5FFFF3e)
2658       {
2659          regs->itu.channel[4].brb = data;
2660          return;
2661       }
2662 
2663       //everywhere else is inacessible
2664 
2665       assert(0);
2666    }
2667    else if (addr >= 0x5FFFF40 && addr <= 0x5FFFF7F)
2668    {
2669       //dmac
2670       if (addr == 0x5FFFF48)
2671       {
2672          regs->dmac.dmaor = data & 0xfff9;
2673          return;
2674       }
2675       if (addr >= 0x5FFFF40 && addr <= 0x5FFFF4E)
2676       {
2677          onchip_dmac_write_word(regs, addr - 0x5FFFF40, 0, data);
2678          return;
2679       }
2680       else if (addr >= 0x5FFFF50 && addr <= 0x5FFFF5E)
2681       {
2682          onchip_dmac_write_word(regs, addr - 0x5FFFF50, 1, data);
2683          return;
2684       }
2685       else if (addr >= 0x5FFFF60 && addr <= 0x5FFFF6E)
2686       {
2687          onchip_dmac_write_word(regs, addr - 0x5FFFF60, 2, data);
2688          return;
2689       }
2690       else if (addr >= 0x5FFFF70 && addr <= 0x5FFFF7E)
2691       {
2692          onchip_dmac_write_word(regs, addr - 0x5FFFF70, 3, data);
2693          return;
2694       }
2695 
2696       assert(0);
2697    }
2698    else if (addr >= 0x5FFFF80 && addr <= 0x5FFFF83)
2699    {
2700       //unmapped?
2701       return;
2702    }
2703    else if (addr >= 0x5FFFF84 && addr <= 0x5FFFF8F)
2704    {
2705       //intc
2706       switch (addr - 0x5FFFF80)
2707       {
2708       case 0:
2709       case 2:
2710          return;//unmapped
2711       case 4:
2712          regs->intc.ipra = data;
2713          return;
2714       case 6:
2715          regs->intc.iprb = data;
2716          return;
2717       case 8:
2718          regs->intc.iprc = data;
2719          return;
2720       case 0xa:
2721          regs->intc.iprd = data;
2722          return;
2723       case 0xc:
2724          regs->intc.ipre = data;
2725          return;
2726       case 0xe:
2727          regs->intc.icr = data;
2728          return;
2729       }
2730 
2731       assert(0);
2732    }
2733    else if (addr >= 0x5FFFF90 && addr <= 0x5FFFF99)
2734    {
2735       //ubc
2736       switch (addr - 0x5FFFF90)
2737       {
2738       case 0:
2739          regs->ubc.bar = (regs->ubc.bar & 0xffff) | data << 16;
2740          return;
2741       case 2:
2742          regs->ubc.bar = (regs->ubc.bar & 0xffff0000) | data;
2743          return;
2744       case 4:
2745          regs->ubc.bamr = (regs->ubc.bamr & 0xffff) | data << 16;
2746          return;
2747       case 6:
2748          regs->ubc.bamr = (regs->ubc.bamr & 0xffff0000) | data;
2749          return;
2750       case 8:
2751          regs->ubc.bbr = data;
2752          return;
2753       }
2754 
2755       assert(0);
2756    }
2757    else if (addr >= 0x5FFFF9A && addr <= 0x5FFFF9F)
2758    {
2759       //unmapped
2760       return;
2761    }
2762    else if (addr >= 0x5FFFFA0 && addr <= 0x5FFFFB3)
2763    {
2764       //bsc
2765       switch (addr - 0x5FFFFA0)
2766       {
2767       case 0:
2768          regs->bsc.bcr = data;
2769          return;
2770       case 2:
2771          regs->bsc.wcr1 = data;
2772          return;
2773       case 4:
2774          regs->bsc.wcr2 = data;
2775          return;
2776       case 6:
2777          regs->bsc.wcr3 = data;
2778          return;
2779       case 8:
2780          regs->bsc.dcr = data;
2781          return;
2782       case 0xa:
2783          regs->bsc.pcr = data;
2784          return;
2785       case 0xc:
2786          regs->bsc.rcr = data;
2787          return;
2788       case 0xe:
2789          regs->bsc.rtcsr = data;
2790          return;
2791       case 0x10:
2792          regs->bsc.rtcnt = data;
2793          return;
2794       case 0x12:
2795          regs->bsc.rtcor = data;
2796          return;
2797       }
2798 
2799       assert(0);
2800    }
2801    else if (addr >= 0x5FFFFb4 && addr <= 0x5FFFFb7)
2802    {
2803       //unmapped
2804       return;
2805    }
2806    else if (addr >= 0x5FFFFB8 && addr <= 0x5FFFFBB)
2807    {
2808       //wdt
2809       //TODO
2810       return;
2811    }
2812    else if (addr == 0x5FFFFbc)
2813    {
2814       //sbycr
2815       //what happens to the lower 8 bits?
2816       regs->sbycr = data >> 8;
2817       return;
2818    }
2819    else if (addr >= 0x5FFFFBD && addr <= 0x5FFFFBF)
2820    {
2821       //unmapped
2822       return;
2823    }
2824    else if (addr >= 0x5FFFFC0 && addr <= 0x5FFFFC3)
2825    {
2826       //port a/b data reg
2827       switch (addr - 0x5FFFFC0)
2828       {
2829       case 0:
2830          regs->padr = data;
2831          return;
2832       case 2:
2833          regs->pbdr = data;
2834          return;
2835       }
2836 
2837       assert(0);
2838    }
2839    else if (addr >= 0x5FFFFC4 && addr <= 0x5FFFFCF)
2840    {
2841       //pfc
2842       switch (addr - 0x5FFFFC0)
2843       {
2844          //paior
2845       case 4:
2846          regs->pfc.paior = data;
2847          return;
2848       case 6:
2849          regs->pfc.pbior = data;
2850          return;
2851       case 8:
2852          regs->pfc.pacr1 = data;
2853          return;
2854       case 0xa:
2855          regs->pfc.pacr2 = data;
2856          return;
2857       case 0xc:
2858          regs->pfc.pbcr1 = data;
2859          return;
2860       case 0xe:
2861          regs->pfc.pbcr2 = data;
2862          return;
2863       }
2864 
2865       assert(0);
2866    }
2867    else if (addr == 0x5FFFFD0)
2868    {
2869       regs->pcdr = data;
2870       return;
2871    }
2872    else if (addr >= 0x5FFFFD2 && addr <= 0x5FFFFED)
2873    {
2874       //unmapped
2875       return;
2876    }
2877    else if (addr == 0x5FFFFEE)
2878    {
2879       //cascr
2880       regs->cascr = data;
2881       return;
2882    }
2883    else if (addr >= 0x5FFFFF0 && addr <= 0x5FFFFF7)
2884    {
2885       //tpc
2886       switch (addr - 0x5FFFFF0)
2887       {
2888       case 0:
2889          regs->tpc.tpmr = data >> 8;
2890          regs->tpc.tpcr = data & 0xff;
2891          return;
2892       case 2:
2893          regs->tpc.nderb = data >> 8;
2894          regs->tpc.ndera = data & 0xff;
2895          return;
2896       case 4:
2897          regs->tpc.ndrb = data >> 8;
2898          regs->tpc.ndra = data & 0xff;
2899          return;
2900       case 6:
2901          regs->tpc.ndrb = data >> 8;
2902          regs->tpc.ndra = data & 0xff;
2903          return;
2904       }
2905 
2906       assert(0);
2907    }
2908    else if (addr >= 0x5FFFFF8 && addr <= 0x5FFFFFF)
2909    {
2910       //unmapped
2911       return;
2912    }
2913    assert(0);
2914 
2915    return;
2916 }
2917 
onchip_sci_read_word(struct Onchip * regs,u32 addr,int which)2918 u16 onchip_sci_read_word(struct Onchip * regs, u32 addr, int which)
2919 {
2920    switch (addr)
2921    {
2922    case 0:
2923       return regs->sci[which].smr << 8 | regs->sci[which].brr;
2924    case 2:
2925       return regs->sci[which].scr << 8 | regs->sci[which].tdr;
2926    case 4:
2927       return regs->sci[which].ssr << 8 | regs->sci[which].rdr;
2928    }
2929 
2930    assert(0);
2931 
2932    return 0;
2933 }
2934 
onchip_timer_read_word(struct Onchip * regs,u32 addr,int which_timer)2935 u16 onchip_timer_read_word(struct Onchip * regs, u32 addr, int which_timer)
2936 {
2937    switch (addr)
2938    {
2939    case 0:
2940    case 1:
2941    case 2:
2942    case 3:
2943       //byte access only
2944       break;
2945    case 4:
2946       return regs->itu.channel[which_timer].tcnt;
2947       break;
2948    case 6:
2949       return regs->itu.channel[which_timer].gra;
2950       break;
2951    case 8:
2952       return regs->itu.channel[which_timer].grb;
2953       break;
2954    case 0xa:
2955       return regs->itu.channel[which_timer].bra;
2956       break;
2957    case 0xc:
2958       return regs->itu.channel[which_timer].brb;
2959       break;
2960    }
2961 
2962    assert(0);
2963    return 0;
2964 }
2965 
onchip_dmac_read_word(struct Onchip * regs,u32 addr,int which)2966 u16 onchip_dmac_read_word(struct Onchip * regs, u32 addr, int which)
2967 {
2968    switch (addr)
2969    {
2970    case 0:
2971       return regs->dmac.channel[which].sar >> 16;
2972    case 2:
2973       return regs->dmac.channel[which].sar & 0xffff;
2974    case 4:
2975       return regs->dmac.channel[which].dar >> 16;
2976    case 6:
2977       return regs->dmac.channel[which].dar & 0xffff;
2978    case 8:
2979       //unmapped
2980       return 0;
2981    case 0xa:
2982       return regs->dmac.channel[which].tcr;
2983    case 0xc:
2984       return 0;
2985    case 0xe:
2986       return regs->dmac.channel[which].chcr;
2987    }
2988 
2989    assert(0);
2990 
2991    return 0;
2992 }
2993 
2994 
onchip_read_word(struct Onchip * regs,u32 addr)2995 u16 onchip_read_word(struct Onchip * regs, u32 addr)
2996 {
2997    CDTRACE("rwreg: %08X %04X\n", addr);
2998    if (addr >= 0x5FFFE00 && addr <= 0x5FFFEBF)
2999    {
3000       //unmapped
3001       return 0;
3002    }
3003    //sci
3004    else if (addr >= 0x5FFFEC0 && addr <= 0x5FFFECD)
3005    {
3006       if (addr >= 0x5FFFEC0 && addr <= 0x5FFFEC5)
3007       {
3008          //channel 0
3009          return onchip_sci_read_word(regs, addr - 0x5FFFEC0, 0);
3010       }
3011       else if (addr >= 0x5FFFEC6 && addr <= 0x5FFFEC7)
3012       {
3013          return 0;//unmapped
3014       }
3015       else if (addr >= 0x5FFFEC8 && addr <= 0x5FFFECD)
3016       {
3017          //channel 1
3018          return onchip_sci_read_word(regs, addr - 0x5FFFEC8, 1);
3019       }
3020       else if (addr >= 0x5FFFECE && addr <= 0x5FFFECF)
3021       {
3022          return 0;//unmapped
3023       }
3024    }
3025    else if (addr >= 0x5FFFECE && addr <= 0x5FFFEDF)
3026    {
3027       //unmapped
3028       return 0;
3029    }
3030    else if (addr >= 0x5FFFEE0 && addr <= 0x5FFFEE9)
3031    {
3032       //a/d
3033       switch (addr - 0x5FFFEE0)
3034       {
3035       case 0:
3036          return regs->addra;
3037       case 2:
3038          return regs->addrb;
3039       case 4:
3040          return regs->addrc;
3041       case 6:
3042          return regs->addrd;
3043       case 8:
3044          return regs->adcsr << 8 | regs->adcr;
3045       }
3046 
3047       assert(0);
3048    }
3049    else if (addr >= 0x5FFFEEa && addr <= 0x5FFFEEf)
3050    {
3051       return 0;//unmapped
3052    }
3053    else if (addr >= 0x5FFFEF0 && addr <= 0x5FFFEFF)
3054    {
3055       //unmapped
3056       return 0;
3057    }
3058    else if (addr >= 0x5FFFF00 && addr <= 0x5FFFF3F)
3059    {
3060       if (addr >= 0x5FFFF00 && addr <= 0x5FFFF03)
3061       {
3062          //not 16-bit accessible
3063          return 0;
3064       }
3065       if (addr >= 0x5FFFF04 && addr <= 0x5FFFF07)
3066       {
3067          return 0;//not 16-bit accessible
3068       }
3069       if (addr >= 0x5FFFF0E && addr <= 0x5FFFF11)
3070       {
3071          return 0;//not 16-bit accessible
3072       }
3073       if (addr >= 0x5FFFF18 && addr <= 0x5FFFF1B)
3074       {
3075          return 0;//not 16-bit accessible
3076       }
3077       if (addr >= 0x5FFFF22 && addr <= 0x5FFFF25)
3078       {
3079          return 0;//not 16-bit accessible
3080       }
3081       if (addr >= 0x5FFFF32 && addr <= 0x5FFFF35)
3082       {
3083          return 0;//not 16-bit accessible
3084       }
3085       if (addr == 0x5FFFF30)
3086       {
3087          //unmapped
3088          return 0;
3089       }
3090       if (addr >= 0x5FFFF04 && addr <= 0x5FFFF3F)
3091       {
3092          if (addr <= 0x5FFFF0D)
3093             return onchip_timer_read_word(regs, addr - 0x5FFFF04, 0);
3094          else if (addr <= 0x5FFFF17)
3095             return onchip_timer_read_word(regs, addr - 0x5FFFF0E, 1);
3096          else if (addr <= 0x5FFFF21)
3097             return onchip_timer_read_word(regs, addr - 0x5FFFF18, 2);
3098          else if (addr <= 0x5FFFF2F)
3099             return onchip_timer_read_word(regs, addr - 0x5FFFF22, 3);
3100          else
3101             return onchip_timer_read_word(regs, addr - 0x5FFFF32, 4);
3102       }
3103       //everywhere else is inacessible
3104 
3105       assert(0);
3106 
3107    }
3108    else if (addr >= 0x5FFFF40 && addr <= 0x5FFFF7F)
3109    {
3110       //dmac
3111       if (addr == 0x5FFFF48)
3112       {
3113          return regs->dmac.dmaor;
3114       }
3115       if (addr >= 0x5FFFF40 && addr <= 0x5FFFF4E)
3116       {
3117          return onchip_dmac_read_word(regs, addr - 0x5FFFF40, 0);
3118       }
3119       else if (addr >= 0x5FFFF50 && addr <= 0x5FFFF5E)
3120       {
3121          return onchip_dmac_read_word(regs, addr - 0x5FFFF50, 1);
3122       }
3123       else if (addr >= 0x5FFFF60 && addr <= 0x5FFFF6E)
3124       {
3125          return onchip_dmac_read_word(regs, addr - 0x5FFFF60, 2);
3126       }
3127       else if (addr >= 0x5FFFF70 && addr <= 0x5FFFF7E)
3128       {
3129          return onchip_dmac_read_word(regs, addr - 0x5FFFF70, 3);
3130       }
3131 
3132       assert(0);
3133    }
3134    else if (addr >= 0x5FFFF80 && addr <= 0x5FFFF83)
3135    {
3136       //unmapped?
3137       return 0;
3138    }
3139    else if (addr >= 0x5FFFF84 && addr <= 0x5FFFF8F)
3140    {
3141       //intc
3142       switch (addr - 0x5FFFF80)
3143       {
3144       case 0:
3145       case 2:
3146          return 0;//unmapped
3147       case 4:
3148          return regs->intc.ipra;
3149       case 6:
3150          return regs->intc.iprb;
3151       case 8:
3152          return regs->intc.iprc;
3153       case 0xa:
3154          return regs->intc.iprd;
3155       case 0xc:
3156          return regs->intc.ipre;
3157       case 0xe:
3158          return regs->intc.icr;
3159       }
3160 
3161       assert(0);
3162    }
3163    else if (addr >= 0x5FFFF90 && addr <= 0x5FFFF99)
3164    {
3165       //ubc
3166       switch (addr - 0x5FFFF90)
3167       {
3168       case 0:
3169          return regs->ubc.bar >> 16;
3170       case 2:
3171          return regs->ubc.bar & 0xffff;
3172       case 4:
3173          return regs->ubc.bamr >> 16;
3174       case 6:
3175          return regs->ubc.bamr & 0xffff;
3176       case 8:
3177          return regs->ubc.bbr;
3178       }
3179 
3180       assert(0);
3181    }
3182    else if (addr >= 0x5FFFF9A && addr <= 0x5FFFF9F)
3183    {
3184       //unmapped
3185       return 0;
3186    }
3187    else if (addr >= 0x5FFFFA0 && addr <= 0x5FFFFB3)
3188    {
3189       //bsc
3190       switch (addr - 0x5FFFFA0)
3191       {
3192       case 0:
3193          return regs->bsc.bcr;
3194       case 2:
3195          return regs->bsc.wcr1;
3196       case 4:
3197          return regs->bsc.wcr2;
3198       case 6:
3199          return regs->bsc.wcr3;
3200       case 8:
3201          return regs->bsc.dcr;
3202       case 0xa:
3203          return regs->bsc.pcr;
3204       case 0xc:
3205          return regs->bsc.rcr;
3206       case 0xe:
3207          return regs->bsc.rtcsr;
3208       case 0x10:
3209          return regs->bsc.rtcnt;
3210       case 0x12:
3211          return regs->bsc.rtcor;
3212       }
3213 
3214       assert(0);
3215    }
3216    else if (addr >= 0x5FFFFb4 && addr <= 0x5FFFFb7)
3217    {
3218       //unmapped
3219       return 0;
3220    }
3221    else if (addr >= 0x5FFFFB8 && addr <= 0x5FFFFBB)
3222    {
3223       //wdt
3224       //TODO
3225       return 0;
3226    }
3227    else if (addr == 0x5FFFFbc)
3228    {
3229       //sbycr
3230       //what happens to the lower 8 bits?
3231       return  regs->sbycr << 8 | 0;
3232    }
3233    else if (addr >= 0x5FFFFBD && addr <= 0x5FFFFBF)
3234    {
3235       //unmapped
3236       return 0;
3237    }
3238    else if (addr >= 0x5FFFFC0 && addr <= 0x5FFFFC3)
3239    {
3240       //port a/b data reg
3241       switch (addr - 0x5FFFFC0)
3242       {
3243       case 0:
3244          return regs->padr;
3245       case 2:
3246          return regs->pbdr;
3247       }
3248 
3249       assert(0);
3250    }
3251    else if (addr >= 0x5FFFFC4 && addr <= 0x5FFFFCF)
3252    {
3253       //pfc
3254       switch (addr - 0x5FFFFC0)
3255       {
3256          //paior
3257       case 4:
3258          return regs->pfc.paior;
3259       case 6:
3260          return regs->pfc.pbior;
3261       case 8:
3262          return regs->pfc.pacr1;
3263       case 0xa:
3264          return regs->pfc.pacr2;
3265       case 0xc:
3266          return regs->pfc.pbcr1;
3267       case 0xe:
3268          return regs->pfc.pbcr2;
3269       }
3270 
3271       assert(0);
3272    }
3273    else if (addr == 0x5FFFFD0)
3274    {
3275       return regs->pcdr;
3276    }
3277    else if (addr >= 0x5FFFFD2 && addr <= 0x5FFFFED)
3278    {
3279       //unmapped
3280       return 0;
3281    }
3282    else if (addr == 0x5FFFFEE)
3283    {
3284       //cascr
3285       return regs->cascr;
3286    }
3287    else if (addr >= 0x5FFFFF0 && addr <= 0x5FFFFF7)
3288    {
3289       //tpc
3290       switch (addr - 0x5FFFFF0)
3291       {
3292       case 0:
3293          return regs->tpc.tpmr << 8 | regs->tpc.tpcr;
3294       case 2:
3295          return regs->tpc.nderb << 8 | regs->tpc.ndera;
3296       case 4:
3297          return regs->tpc.ndrb << 8 | regs->tpc.ndra;
3298       case 6:
3299          return regs->tpc.ndrb << 8 | regs->tpc.ndra;
3300       }
3301 
3302       assert(0);
3303    }
3304    else if (addr >= 0x5FFFFF8 && addr <= 0x5FFFFFF)
3305    {
3306       //unmapped
3307       return 0;
3308    }
3309    assert(0);
3310 
3311    return 0;
3312 }
3313 
3314 
onchip_dmac_write_long(struct Onchip * regs,u32 addr,int which,u32 data)3315 void onchip_dmac_write_long(struct Onchip * regs, u32 addr, int which, u32 data)
3316 {
3317    switch (addr)
3318    {
3319    case 0:
3320       regs->dmac.channel[which].sar = data;
3321       return;
3322    case 4:
3323       regs->dmac.channel[which].dar = data;
3324       return;
3325    case 8:
3326       //unmapped
3327       return;
3328    case 0xa:
3329       regs->dmac.channel[which].tcr = data;
3330       return;
3331    case 0xc:
3332       //unmapped?
3333       return;
3334    case 0xe:
3335       regs->dmac.channel[which].chcr = (data >> 16) & 0xfffd;
3336       return;
3337    }
3338 
3339    assert(0);
3340 }
onchip_write_long(struct Onchip * regs,u32 addr,u32 data)3341 void onchip_write_long(struct Onchip * regs, u32 addr, u32 data)
3342 {
3343    print_serial(0);
3344 
3345    CDTRACE("wlreg: %08X %08X\n", addr, data);
3346    if (addr >= 0x5FFFE00 && addr <= 0x5FFFEBF)
3347    {
3348       //unmapped
3349       return;
3350    }
3351    //sci
3352    else if (addr >= 0x5FFFEC0 && addr <= 0x5FFFECD)
3353    {
3354       return;//inaccessible from 32
3355    }
3356    else if (addr >= 0x5FFFECE && addr <= 0x5FFFEDF)
3357    {
3358       //unmapped
3359       return;
3360    }
3361    else if (addr >= 0x5FFFEE0 && addr <= 0x5FFFEE9)
3362    {
3363       //a/d
3364       return;//read only
3365    }
3366    else if (addr >= 0x5FFFEEa && addr <= 0x5FFFEEf)
3367    {
3368       return;//unmapped
3369    }
3370    else if (addr >= 0x5FFFEF0 && addr <= 0x5FFFEFF)
3371    {
3372       //unmapped
3373       return;
3374    }
3375    else if (addr >= 0x5FFFF00 && addr <= 0x5FFFF3F)
3376    {
3377       if (addr >= 0x5FFFF00 && addr <= 0x5FFFF03)
3378       {
3379          //not 16-bit accessible
3380          return;
3381       }
3382       if (addr >= 0x5FFFF04 && addr <= 0x5FFFF07)
3383       {
3384          return;//not 16-bit accessible
3385       }
3386       if (addr >= 0x5FFFF0E && addr <= 0x5FFFF11)
3387       {
3388          return;//not 16-bit accessible
3389       }
3390       if (addr >= 0x5FFFF18 && addr <= 0x5FFFF1B)
3391       {
3392          return;//not 16-bit accessible
3393       }
3394       if (addr >= 0x5FFFF22 && addr <= 0x5FFFF25)
3395       {
3396          return;//not 16-bit accessible
3397       }
3398       if (addr >= 0x5FFFF32 && addr <= 0x5FFFF35)
3399       {
3400          return;//not 16-bit accessible
3401       }
3402 
3403       if (addr == 0x5FFFF30)
3404       {
3405          //unmapped
3406          return;
3407       }
3408       //channel 0
3409       if (addr == 0x5FFFF08)
3410       {
3411          regs->itu.channel[0].tcnt = data >> 16;
3412          regs->itu.channel[0].gra = (data >> 16) & 0xffff;
3413          return;
3414       }
3415       else if (addr == 0x5FFFF0a)
3416       {
3417          regs->itu.channel[0].gra = data >> 16;
3418          regs->itu.channel[0].grb = (data >> 16) & 0xffff;
3419          return;
3420       }
3421       else if (addr == 0x5FFFF0c)
3422       {
3423          //not allowed
3424          return;
3425       }
3426       //channel 1
3427       else if (addr == 0x5FFFF12)
3428       {
3429          //not allowed
3430          return;
3431       }
3432       else if (addr == 0x5FFFF14)
3433       {
3434          regs->itu.channel[1].gra = data >> 16;
3435          regs->itu.channel[1].grb = (data >> 16) & 0xffff;
3436          return;
3437       }
3438       else if (addr == 0x5FFFF16)
3439       {
3440          regs->itu.channel[1].grb = data >> 16;
3441          //the rest is ignored?
3442          return;
3443       }
3444       //channel 2
3445       else if (addr == 0x5FFFF1c)
3446       {
3447          regs->itu.channel[2].tcnt = data >> 16;
3448          regs->itu.channel[2].gra = (data >> 16) & 0xffff;
3449          return;
3450       }
3451       else if (addr == 0x5FFFF1e)
3452       {
3453          regs->itu.channel[2].gra = data >> 16;
3454          regs->itu.channel[2].grb = (data >> 16) & 0xffff;
3455          return;
3456       }
3457       else if (addr == 0x5FFFF20)
3458       {
3459          //not allowed
3460          return;
3461       }
3462       //channel 3
3463       else if (addr == 0x5FFFF26)
3464       {
3465          //not allowed
3466          return;
3467       }
3468       else if (addr == 0x5FFFF28)
3469       {
3470          regs->itu.channel[3].gra = data >> 16;
3471          regs->itu.channel[3].grb = (data >> 16) & 0xffff;
3472          return;
3473       }
3474       else if (addr == 0x5FFFF2a)
3475       {
3476          regs->itu.channel[3].grb = data >> 16;
3477          regs->itu.channel[3].bra = (data >> 16) & 0xffff;
3478          return;
3479       }
3480       else if (addr == 0x5FFFF2c)
3481       {
3482          regs->itu.channel[3].bra = data >> 16;
3483          regs->itu.channel[3].brb = (data >> 16) & 0xffff;
3484          return;
3485       }
3486       else if (addr == 0x5FFFF2e)
3487       {
3488          regs->itu.channel[3].brb = data >> 16;
3489          //ignored?
3490          return;
3491       }
3492       //channel 4
3493       else if (addr == 0x5FFFF36)
3494       {
3495          //not allowed
3496          return;
3497       }
3498       else if (addr == 0x5FFFF38)
3499       {
3500          regs->itu.channel[4].gra = data >> 16;
3501          regs->itu.channel[4].grb = (data >> 16) & 0xffff;
3502          return;
3503       }
3504       else if (addr == 0x5FFFF3a)
3505       {
3506          regs->itu.channel[4].grb = data >> 16;
3507          regs->itu.channel[4].bra = (data >> 16) & 0xffff;
3508          return;
3509       }
3510       else if (addr == 0x5FFFF3c)
3511       {
3512          regs->itu.channel[4].bra = data >> 16;
3513          regs->itu.channel[4].brb = (data >> 16) & 0xffff;
3514          return;
3515       }
3516       else if (addr == 0x5FFFF3e)
3517       {
3518          regs->itu.channel[4].brb = data >> 16;
3519          //ignored?
3520          return;
3521       }
3522 
3523       assert(0);
3524    }
3525    else if (addr >= 0x5FFFF40 && addr <= 0x5FFFF7F)
3526    {
3527       //dmac
3528       if (addr == 0x5FFFF48)//dmaor
3529       {
3530          regs->dmac.dmaor = data & 0xfff9;
3531          return;
3532       }
3533       if (addr >= 0x5FFFF40 && addr <= 0x5FFFF4E)
3534       {
3535          onchip_dmac_write_long(regs, addr - 0x5FFFF40, 0, data);
3536          return;
3537       }
3538       else if (addr >= 0x5FFFF50 && addr <= 0x5FFFF5E)
3539       {
3540          onchip_dmac_write_long(regs, addr - 0x5FFFF50, 1, data);
3541          return;
3542       }
3543       else if (addr >= 0x5FFFF60 && addr <= 0x5FFFF6E)
3544       {
3545          onchip_dmac_write_long(regs, addr - 0x5FFFF60, 2, data);
3546          return;
3547       }
3548       else if (addr >= 0x5FFFF70 && addr <= 0x5FFFF7E)
3549       {
3550          onchip_dmac_write_long(regs, addr - 0x5FFFF70, 3, data);
3551          return;
3552       }
3553 
3554       assert(0);
3555    }
3556    else if (addr >= 0x5FFFF80 && addr <= 0x5FFFF83)
3557    {
3558       //unmapped?
3559       return;
3560    }
3561    else if (addr >= 0x5FFFF84 && addr <= 0x5FFFF8F)
3562    {
3563       //intc
3564       switch (addr - 0x5FFFF80)
3565       {
3566       case 0:
3567       case 2:
3568          return;//unmapped
3569       case 4:
3570          regs->intc.ipra = data >> 16;
3571          regs->intc.iprb = data & 0xffff;
3572          return;
3573       case 6:
3574          regs->intc.iprb = data >> 16;
3575          regs->intc.iprc = data & 0xffff;
3576          return;
3577       case 8:
3578          regs->intc.iprc = data >> 16;
3579          regs->intc.iprd = data & 0xffff;
3580          return;
3581       case 0xa:
3582          regs->intc.iprd = data >> 16;
3583          regs->intc.ipre = data & 0xffff;
3584          return;
3585       case 0xc:
3586          regs->intc.ipre = data >> 16;
3587          regs->intc.icr = data & 0xffff;
3588          return;
3589       case 0xe:
3590          regs->intc.icr = data >> 16;
3591          //ignored?
3592          return;
3593       }
3594 
3595       assert(0);
3596    }
3597    else if (addr >= 0x5FFFF90 && addr <= 0x5FFFF99)
3598    {
3599       //ubc
3600       switch (addr - 0x5FFFF90)
3601       {
3602       case 0:
3603          regs->ubc.bar = data;
3604          return;
3605       case 2://apparently possible?
3606          return;
3607       case 4:
3608          regs->ubc.bamr = data;
3609          return;
3610       case 6://apparently possible?
3611          return;
3612       case 8:
3613          regs->ubc.bbr = data >> 16;
3614          return;
3615       }
3616 
3617       assert(0);
3618    }
3619    else if (addr >= 0x5FFFF9A && addr <= 0x5FFFF9F)
3620    {
3621       //unmapped
3622       return;
3623    }
3624    else if (addr >= 0x5FFFFA0 && addr <= 0x5FFFFB3)
3625    {
3626       //bsc
3627       switch (addr - 0x5FFFFA0)
3628       {
3629       case 0:
3630          regs->bsc.bcr = data >> 16;
3631          regs->bsc.wcr1 = data & 0xffff;
3632          return;
3633       case 2:
3634          regs->bsc.wcr1 = data >> 16;
3635          regs->bsc.wcr2 = data & 0xffff;
3636          return;
3637       case 4:
3638          regs->bsc.wcr2 = data >> 16;
3639          regs->bsc.wcr3 = data & 0xffff;
3640          return;
3641       case 6:
3642          regs->bsc.wcr3 = data >> 16;
3643          regs->bsc.dcr = data & 0xffff;
3644          return;
3645       case 8:
3646          regs->bsc.dcr = data >> 16;
3647          regs->bsc.pcr = data & 0xffff;
3648          return;
3649       case 0xa:
3650          regs->bsc.pcr = data >> 16;
3651          regs->bsc.rcr = data & 0xffff;
3652          return;
3653 
3654       //write only with word transfer instructions?
3655       case 0xc:
3656          return;
3657       case 0xe:
3658          return;
3659       case 0x10:
3660          return;
3661       case 0x12:
3662          return;
3663       }
3664 
3665       assert(0);
3666    }
3667    else if (addr >= 0x5FFFFb4 && addr <= 0x5FFFFb7)
3668    {
3669       //unmapped
3670       return;
3671    }
3672    else if (addr >= 0x5FFFFB8 && addr <= 0x5FFFFBB)
3673    {
3674       //wdt
3675       //TODO
3676       return;
3677    }
3678    else if (addr == 0x5FFFFbc)
3679    {
3680       //sbycr
3681       //extra bits?
3682       regs->sbycr = data >> 24;
3683       return;
3684    }
3685    else if (addr >= 0x5FFFFBD && addr <= 0x5FFFFBF)
3686    {
3687       //unmapped
3688       return;
3689    }
3690    else if (addr >= 0x5FFFFC0 && addr <= 0x5FFFFC3)
3691    {
3692       //port a/b data reg
3693       switch (addr - 0x5FFFFC0)
3694       {
3695       case 0:
3696          //init routine requires pbdr to be set
3697       {
3698          u16 val = 0;
3699 
3700          val = ((data >> 16) & 0xffff);
3701          regs->padr &= ~regs->pfc.paior;
3702          regs->padr |= val & regs->pfc.paior;
3703 
3704          val = data & 0xffff;
3705          regs->pbdr &= ~regs->pfc.pbior;
3706          regs->pbdr |= val & regs->pfc.pbior;
3707       }
3708          return;
3709       case 2:
3710          regs->pbdr = data >> 16;
3711          regs->pfc.paior = data & 0xffff;//check this
3712          return;
3713       }
3714 
3715       assert(0);
3716    }
3717    else if (addr >= 0x5FFFFC4 && addr <= 0x5FFFFCF)
3718    {
3719       //pfc
3720       switch (addr - 0x5FFFFC0)
3721       {
3722          //paior
3723       case 4:
3724          regs->pfc.paior = data >> 16;
3725          regs->pfc.pbior = data & 0xffff;
3726          return;
3727       case 6:
3728          regs->pfc.pbior = data >> 16;
3729          regs->pfc.pacr1 = data & 0xffff;
3730          return;
3731       case 8:
3732          regs->pfc.pacr1 = data >> 16;
3733          regs->pfc.pacr2 = data & 0xffff;
3734          return;
3735       case 0xa:
3736          regs->pfc.pacr2 = data >> 16;
3737          regs->pfc.pbcr1 = data & 0xffff;
3738          return;
3739       case 0xc:
3740          //not allowed according to tpc section but the rom writes this...
3741          regs->pfc.pbcr1 = data >> 16;
3742          regs->pfc.pbcr2 = data & 0xffff;
3743          return;
3744       case 0xe:
3745          regs->pfc.pbcr2 = data >> 16;
3746          regs->pcdr = data & 0xffff;//check this
3747          return;
3748       }
3749 
3750       assert(0);
3751    }
3752    else if (addr == 0x5FFFFD0)
3753    {
3754       regs->pcdr = data >> 16;
3755       return;
3756    }
3757    else if (addr >= 0x5FFFFD2 && addr <= 0x5FFFFED)
3758    {
3759       //unmapped
3760       return;
3761    }
3762    else if (addr == 0x5FFFFEE)
3763    {
3764       //cascr
3765       regs->cascr = data >> 16;
3766       return;
3767    }
3768    else if (addr >= 0x5FFFFF0 && addr <= 0x5FFFFF7)
3769    {
3770       //tpc
3771 
3772       //not accessible from 32 bit
3773       return;
3774 
3775       assert(0);
3776    }
3777    else if (addr >= 0x5FFFFF8 && addr <= 0x5FFFFFF)
3778    {
3779       //unmapped
3780       return;
3781    }
3782    assert(0);
3783 
3784    return;
3785 }
3786 
onchip_dmac_read_long(struct Onchip * regs,u32 addr,int which)3787 u32 onchip_dmac_read_long(struct Onchip * regs, u32 addr, int which)
3788 {
3789    switch (addr)
3790    {
3791    case 0:
3792       return regs->dmac.channel[which].sar;
3793    case 4:
3794       return regs->dmac.channel[which].dar;
3795    case 8:
3796       //unmapped
3797       return 0;
3798    case 0xa:
3799       return regs->dmac.channel[which].tcr;
3800    case 0xc:
3801       //unmapped?
3802       return 0;
3803    case 0xe:
3804       return regs->dmac.channel[which].chcr << 16 | 0;
3805    }
3806 
3807 
3808    assert(0);
3809 
3810    return 0;
3811 }
3812 
onchip_read_long(struct Onchip * regs,u32 addr)3813 u32 onchip_read_long(struct Onchip * regs, u32 addr)
3814 {
3815    CDTRACE("rlreg: %08X\n", addr);
3816    if (addr >= 0x5FFFE00 && addr <= 0x5FFFEBF)
3817    {
3818       //unmapped
3819       return 0;
3820    }
3821    //sci
3822    else if (addr >= 0x5FFFEC0 && addr <= 0x5FFFECD)
3823    {
3824       return 0;//inaccessible from 32
3825    }
3826    else if (addr >= 0x5FFFECE && addr <= 0x5FFFEDF)
3827    {
3828       //unmapped
3829       return 0;
3830    }
3831    else if (addr >= 0x5FFFEE0 && addr <= 0x5FFFEE9)
3832    {
3833       //a/d
3834       return 0;//read only
3835    }
3836    else if (addr >= 0x5FFFEEa && addr <= 0x5FFFEEf)
3837    {
3838       return 0;//unmapped
3839    }
3840    else if (addr >= 0x5FFFEF0 && addr <= 0x5FFFEFF)
3841    {
3842       //unmapped
3843       return 0;
3844    }
3845 
3846    //itu
3847    else if (addr >= 0x5FFFF00 && addr <= 0x5FFFF3F)
3848    {
3849       if (addr >= 0x5FFFF00 && addr <= 0x5FFFF03)
3850       {
3851          //not 16-bit accessible
3852          return 0;
3853       }
3854       if (addr >= 0x5FFFF04 && addr <= 0x5FFFF07)
3855       {
3856          return 0;//not 16-bit accessible
3857       }
3858       if (addr >= 0x5FFFF0E && addr <= 0x5FFFF11)
3859       {
3860          return 0;//not 16-bit accessible
3861       }
3862       if (addr >= 0x5FFFF18 && addr <= 0x5FFFF1B)
3863       {
3864          return 0;//not 16-bit accessible
3865       }
3866       if (addr >= 0x5FFFF22 && addr <= 0x5FFFF25)
3867       {
3868          return 0;//not 16-bit accessible
3869       }
3870       if (addr >= 0x5FFFF32 && addr <= 0x5FFFF35)
3871       {
3872          return 0;//not 16-bit accessible
3873       }
3874 
3875       if (addr == 0x5FFFF30)
3876       {
3877          //unmapped
3878          return 0;
3879       }
3880       //channel 0
3881       if (addr == 0x5FFFF08)
3882       {
3883          return regs->itu.channel[0].tcnt << 16 | regs->itu.channel[0].gra;
3884       }
3885       else if (addr == 0x5FFFF0a)
3886       {
3887          return regs->itu.channel[0].gra << 16 | regs->itu.channel[0].grb;
3888       }
3889       else if (addr == 0x5FFFF0c)
3890       {
3891          //not allowed
3892          return 0;
3893       }
3894       //channel 1
3895       else if (addr == 0x5FFFF12)
3896       {
3897          //not allowed
3898          return 0;
3899       }
3900       else if (addr == 0x5FFFF14)
3901       {
3902          return regs->itu.channel[1].gra << 16 | regs->itu.channel[1].grb;
3903       }
3904       else if (addr == 0x5FFFF16)
3905       {
3906          //lower part?
3907          return regs->itu.channel[1].grb << 16 | 0;
3908       }
3909       //channel 2
3910       else if (addr == 0x5FFFF1c)
3911       {
3912          return regs->itu.channel[2].tcnt << 16 | regs->itu.channel[2].gra;
3913       }
3914       else if (addr == 0x5FFFF1e)
3915       {
3916          return regs->itu.channel[2].gra << 16 | regs->itu.channel[2].grb;
3917       }
3918       else if (addr == 0x5FFFF20)
3919       {
3920          //not allowed
3921          return 0;
3922       }
3923       //channel 3
3924       else if (addr == 0x5FFFF26)
3925       {
3926          //not allowed
3927          return 0;
3928       }
3929       else if (addr == 0x5FFFF28)
3930       {
3931          return regs->itu.channel[3].gra << 16 | regs->itu.channel[3].grb;
3932       }
3933       else if (addr == 0x5FFFF2a)
3934       {
3935          return regs->itu.channel[3].grb << 16 | regs->itu.channel[3].bra;
3936       }
3937       else if (addr == 0x5FFFF2c)
3938       {
3939          return regs->itu.channel[3].bra << 16 | regs->itu.channel[3].brb;
3940       }
3941       else if (addr == 0x5FFFF2e)
3942       {
3943          //lower part?
3944          return regs->itu.channel[3].brb << 16 | 0;
3945       }
3946       //channel 4
3947       else if (addr == 0x5FFFF36)
3948       {
3949          //not allowed
3950          return 0 ;
3951       }
3952       else if (addr == 0x5FFFF38)
3953       {
3954          return regs->itu.channel[4].gra << 16 | regs->itu.channel[4].grb;
3955       }
3956       else if (addr == 0x5FFFF3a)
3957       {
3958          return regs->itu.channel[4].grb << 16 | regs->itu.channel[4].bra;
3959       }
3960       else if (addr == 0x5FFFF3c)
3961       {
3962          return regs->itu.channel[4].bra << 16 | regs->itu.channel[4].brb;
3963       }
3964       else if (addr == 0x5FFFF3e)
3965       {
3966          //lower part?
3967          return regs->itu.channel[4].brb << 16 | 0;
3968       }
3969 
3970       assert(0);
3971    }
3972    else if (addr >= 0x5FFFF40 && addr <= 0x5FFFF7F)
3973    {
3974       //dmac
3975       if (addr == 0x5FFFF48)//dmaor
3976       {
3977          return regs->dmac.dmaor << 16;
3978       }
3979       if (addr >= 0x5FFFF40 && addr <= 0x5FFFF4E)
3980       {
3981          return onchip_dmac_read_long(regs, addr - 0x5FFFF40, 0);
3982       }
3983       else if (addr >= 0x5FFFF50 && addr <= 0x5FFFF5E)
3984       {
3985          return onchip_dmac_read_long(regs, addr - 0x5FFFF50, 1);
3986       }
3987       else if (addr >= 0x5FFFF60 && addr <= 0x5FFFF6E)
3988       {
3989          return onchip_dmac_read_long(regs, addr - 0x5FFFF60, 2);
3990       }
3991       else if (addr >= 0x5FFFF70 && addr <= 0x5FFFF7E)
3992       {
3993          return onchip_dmac_read_long(regs, addr - 0x5FFFF70, 3);
3994       }
3995 
3996       assert(0);
3997    }
3998    else if (addr >= 0x5FFFF80 && addr <= 0x5FFFF83)
3999    {
4000       //unmapped?
4001       return 0;
4002    }
4003    else if (addr >= 0x5FFFF84 && addr <= 0x5FFFF8F)
4004    {
4005       //intc
4006       switch (addr - 0x5FFFF80)
4007       {
4008       case 0:
4009       case 2:
4010          return 0;//unmapped
4011       case 4:
4012          return regs->intc.ipra << 16 | regs->intc.iprb;
4013       case 6:
4014          return regs->intc.iprb << 16 | regs->intc.iprc;
4015       case 8:
4016          return regs->intc.iprc << 16 | regs->intc.iprd;
4017       case 0xa:
4018          return regs->intc.iprd << 16 | regs->intc.ipre;
4019       case 0xc:
4020          return regs->intc.ipre << 16 | regs->intc.icr;
4021       case 0xe:
4022          return regs->intc.icr << 16 | 0;
4023       }
4024 
4025       assert(0);
4026    }
4027    else if (addr >= 0x5FFFF90 && addr <= 0x5FFFF99)
4028    {
4029       //ubc
4030       switch (addr - 0x5FFFF90)
4031       {
4032       case 0:
4033          return regs->ubc.bar;
4034       case 2://apparently possible?
4035          return 0;
4036       case 4:
4037          return regs->ubc.bamr;
4038       case 6://apparently possible?
4039          return 0;
4040       case 8:
4041          return regs->ubc.bar << 16 | 0;
4042       }
4043 
4044       assert(0);
4045    }
4046    else if (addr >= 0x5FFFF9A && addr <= 0x5FFFF9F)
4047    {
4048       //unmapped
4049       return 0;
4050    }
4051    else if (addr >= 0x5FFFFA0 && addr <= 0x5FFFFB3)
4052    {
4053       //bsc
4054       switch (addr - 0x5FFFFA0)
4055       {
4056       case 0:
4057          return regs->bsc.bcr << 16 | regs->bsc.wcr1;
4058       case 2:
4059          return regs->bsc.wcr1 << 16 | regs->bsc.wcr2;
4060       case 4:
4061          return regs->bsc.wcr2 << 16 | regs->bsc.wcr3;
4062       case 6:
4063          return regs->bsc.wcr3 << 16 | regs->bsc.dcr;
4064       case 8:
4065          return regs->bsc.dcr << 16 | regs->bsc.pcr;
4066       case 0xa:
4067          return regs->bsc.pcr << 16 | regs->bsc.rcr;
4068       case 0xc:
4069          return regs->bsc.rcr << 16 | regs->bsc.rtcsr;
4070       case 0xe:
4071          return regs->bsc.rtcsr << 16 | regs->bsc.rtcnt;
4072       case 0x10:
4073          return regs->bsc.rtcnt << 16 | regs->bsc.rtcor;
4074       case 0x12:
4075          return regs->bsc.rtcor << 16 | 0;
4076       }
4077 
4078       assert(0);
4079    }
4080    else if (addr >= 0x5FFFFb4 && addr <= 0x5FFFFb7)
4081    {
4082       //unmapped
4083       return 0;
4084    }
4085    else if (addr >= 0x5FFFFB8 && addr <= 0x5FFFFBB)
4086    {
4087       //wdt
4088       //TODO
4089       return 0;
4090    }
4091    else if (addr == 0x5FFFFbc)
4092    {
4093       //sbycr
4094       //extra bits?
4095       return regs->sbycr << 24 | 0;
4096    }
4097    else if (addr >= 0x5FFFFBD && addr <= 0x5FFFFBF)
4098    {
4099       //unmapped
4100       return 0;
4101    }
4102    else if (addr >= 0x5FFFFC0 && addr <= 0x5FFFFC3)
4103    {
4104       //port a/b data reg
4105       switch (addr - 0x5FFFFC0)
4106       {
4107       case 0:
4108          return regs->padr << 16 | regs->pbdr;
4109       case 2:
4110          return regs->pbdr << 16 | regs->pfc.paior;//check this
4111       }
4112 
4113       assert(0);
4114    }
4115    else if (addr >= 0x5FFFFC4 && addr <= 0x5FFFFCF)
4116    {
4117       //pfc
4118       switch (addr - 0x5FFFFC0)
4119       {
4120          //paior
4121       case 4:
4122          return regs->pfc.paior << 16 | regs->pfc.pbior;
4123       case 6:
4124          return regs->pfc.pbior << 16 | regs->pfc.pacr1;
4125       case 8:
4126          return regs->pfc.pacr1 << 16 | regs->pfc.pacr2;
4127       case 0xa:
4128          return regs->pfc.pacr2 << 16 | regs->pfc.pbcr1;
4129          //not allowed according to tpc section
4130       case 0xc:
4131          //regs->pfc.pbcr1 = data >> 16;
4132          //regs->pfc.pbcr2 = data & 0xffff;
4133          return 0;
4134       case 0xe:
4135          //regs->pfc.pbcr2 = data >> 16;
4136          //regs->pcdr = data & 0xffff;//check this
4137          return 0;
4138       }
4139 
4140       assert(0);
4141    }
4142    else if (addr == 0x5FFFFD0)
4143    {
4144       return regs->pcdr << 16 | 0;
4145    }
4146    else if (addr >= 0x5FFFFD2 && addr <= 0x5FFFFED)
4147    {
4148       //unmapped
4149       return 0;
4150    }
4151    else if (addr == 0x5FFFFEE)
4152    {
4153       //cascr
4154       return regs->cascr << 16;
4155    }
4156    else if (addr >= 0x5FFFFF0 && addr <= 0x5FFFFF7)
4157    {
4158       //tpc
4159 
4160       //not accessible from 32 bit
4161       return 0;
4162 
4163       assert(0);
4164    }
4165    else if (addr >= 0x5FFFFF8 && addr <= 0x5FFFFFF)
4166    {
4167       //unmapped
4168       return 0;
4169    }
4170    assert(0);
4171 
4172    return 0;
4173 }
4174 
memory_map_write_byte(struct Sh1 * sh1,u32 addr,u8 data)4175 void memory_map_write_byte(struct Sh1* sh1, u32 addr, u8 data)
4176 {
4177    u8 area = (addr >> 24) & 7;
4178    u8 a27 = (addr >> 27) & 1;
4179    int mode_pins = 0;
4180 
4181    SH1MEMLOG("memory_map_write_byte 0x%08x 0x%04x", addr, data);
4182 
4183    switch (area)
4184    {
4185    case 0:
4186       //ignore a27 in area 0
4187 
4188       if (mode_pins == 2)//010
4189       {
4190          //   return sh1->rom[addr & 0xffff];
4191       }
4192       else
4193       {
4194          //mode 000 or 001
4195 
4196          //external memory space
4197 
4198          addr &= 0x3FFFFF;
4199       }
4200       break;
4201    case 1:
4202       if (!sh1->onchip.bsc.bcr)
4203       {
4204          //extern memory space
4205       }
4206       else
4207       {
4208 
4209       }
4210 
4211       if (a27)
4212       {
4213          CDTRACE("wbdram: %08X %02X\n", addr, data);
4214          T2WriteByte(SH1Dram, addr & 0x7FFFF, data);
4215          return;
4216       }
4217       break;
4218    case 2:
4219    case 3:
4220    case 4:
4221       //external memory space
4222 
4223       if (a27)
4224       {
4225          ygr_sh1_write_byte(addr, data);
4226          return;
4227       }
4228       break;
4229    case 5:
4230       //onchip area
4231       if (!a27)
4232       {
4233          onchip_write_byte(&sh1->onchip, addr, data);
4234          return;
4235       }
4236       else
4237       {
4238          //external memory space
4239       }
4240       break;
4241    case 6:
4242       if (a27)
4243       {
4244          //external memory space
4245          //mpeg rom read only
4246          return;
4247       }
4248       else if (!sh1->onchip.bsc.bcr)
4249       {
4250          //external memory space
4251       }
4252       break;
4253    case 7:
4254       //onchip ram
4255       CDTRACE("wbram: %08X %02X\n", addr, data);
4256       T2WriteByte(sh1->ram, addr & 0x1fff, data);
4257 //      update_cr_response_values(addr);
4258 //      update_transfer_buffer();
4259       return;
4260 
4261       if (a27)
4262       {
4263          sh1->ram[addr & 0xFFF] = data;
4264       }
4265       else
4266       {
4267          //onchip peripherals
4268       }
4269       break;
4270    }
4271 
4272    assert(0);
4273 }
4274 
memory_map_read_byte(struct Sh1 * sh1,u32 addr)4275 u8 memory_map_read_byte(struct Sh1* sh1, u32 addr)
4276 {
4277    u8 area = (addr >> 24) & 7;
4278    u8 a27 = (addr >> 27) & 1;
4279    int mode_pins = 0;
4280 
4281    SH1MEMLOG("memory_map_read_byte 0x%08x", addr);
4282 
4283    if (addr == 0xF0002D0)
4284    {
4285       int i = 1;
4286    }
4287 
4288    switch (area)
4289    {
4290    case 0:
4291       //ignore a27 in area 0
4292       CDTRACE("rbrom: %08X %02X\n", addr);
4293       return T2ReadByte(SH1Rom, addr & 0xffff);
4294 
4295   //    if (mode_pins == 2)//010
4296   //       return sh1->rom[addr & 0xffff];
4297   //    else
4298       {
4299          //mode 000 or 001
4300 
4301          //external memory space
4302 
4303          addr &= 0x3FFFFF;
4304       }
4305       break;
4306    case 1:
4307       if (!sh1->onchip.bsc.bcr)
4308       {
4309          //extern memory space
4310       }
4311       else
4312       {
4313 
4314       }
4315 
4316       if (a27)
4317       {
4318          CDTRACE("rbdram: %08X %02X\n", addr);
4319          return T2ReadByte(SH1Dram, addr & 0x7FFFF);
4320       }
4321 
4322       break;
4323    case 2:
4324    case 3:
4325    case 4:
4326       //external memory space
4327 
4328       if (a27)
4329       {
4330          return ygr_sh1_read_byte(addr);
4331       }
4332       break;
4333    case 5:
4334       //onchip area
4335       if (!a27)
4336          return onchip_read_byte(&sh1->onchip, addr);
4337       else
4338       {
4339          //external memory space
4340       }
4341       break;
4342    case 6:
4343       if (a27)
4344       {
4345          //external memory space
4346          //mpeg rom
4347          return T2ReadByte(SH1MpegRom, addr & 0x7FFFF);
4348       }
4349       else if (!sh1->onchip.bsc.bcr)
4350       {
4351          //external memory space
4352       }
4353       break;
4354    case 7:
4355       CDTRACE("rbram: %08X %02X\n", addr);
4356       return T2ReadByte(sh1->ram, addr & 0x1fff);
4357 
4358       //onchip ram
4359       if (a27)
4360          return sh1->ram[addr & 0xFFF];
4361       else
4362       {
4363          //onchip peripherals
4364       }
4365       break;
4366    }
4367 
4368    assert(0);
4369    return 0;
4370 }
4371 
4372 
memory_map_read_word(struct Sh1 * sh1,u32 addr)4373 u16 memory_map_read_word(struct Sh1* sh1, u32 addr)
4374 {
4375    u8 area = (addr >> 24) & 7;
4376    u8 a27 = (addr >> 27) & 1;
4377    int mode_pins = 0;
4378 
4379    if (addr == 0xF00026C)
4380    {
4381       int q = 1;
4382    }
4383    SH1MEMLOG("memory_map_read_word 0x%08x", addr);
4384 
4385    switch (area)
4386    {
4387    case 0:
4388       //ignore a27 in area 0
4389 
4390       CDTRACE("rwrom: %08X %04X\n", addr);
4391       return T2ReadWord(SH1Rom, addr & 0xffff);
4392 
4393     //  if (mode_pins == 2)//010
4394     //     return sh1->rom[addr & 0xffff];
4395     //  else
4396    //   {
4397          //mode 000 or 001
4398 
4399          //external memory space
4400 
4401          addr &= 0x3FFFFF;
4402  //     }
4403       break;
4404    case 1:
4405       if (!sh1->onchip.bsc.bcr)
4406       {
4407          //extern memory space
4408       }
4409       else
4410       {
4411 
4412       }
4413 
4414       if (a27)
4415       {
4416          CDTRACE("rwdram: %08X %08X\n", addr);
4417          return T2ReadWord(SH1Dram, addr & 0x7FFFF);
4418       }
4419 
4420       break;
4421    case 2:
4422    case 3:
4423    case 4:
4424       //external memory space
4425 
4426       if (a27)
4427       {
4428          return ygr_sh1_read_word(addr);
4429       }
4430       break;
4431    case 5:
4432       //onchip area
4433       if (!a27)
4434          return onchip_read_word(&sh1->onchip, addr);
4435       else
4436       {
4437          //external memory space
4438       }
4439       break;
4440    case 6:
4441       if (a27)
4442       {
4443          //external memory space
4444          //mpeg rom
4445          return T2ReadWord(SH1MpegRom, addr & 0x7FFFF);
4446       }
4447       else if (!sh1->onchip.bsc.bcr)
4448       {
4449          //external memory space
4450       }
4451       break;
4452    case 7:
4453       //onchip ram
4454 
4455       CDTRACE("rwram: %08X %04X\n", addr);
4456       return T2ReadWord(sh1->ram, addr & 0x1fff);
4457 
4458       if(a27)
4459          return sh1->ram[addr & 0xFFF];
4460       else
4461       {
4462          //onchip peripherals
4463       }
4464       break;
4465    }
4466 
4467    assert(0);
4468    return 0;
4469 }
4470 
memory_map_write_word(struct Sh1 * sh1,u32 addr,u16 data)4471 void memory_map_write_word(struct Sh1* sh1, u32 addr, u16 data)
4472 {
4473    u8 area = (addr >> 24) & 7;
4474    u8 a27 = (addr >> 27) & 1;
4475    int mode_pins = 0;
4476 
4477 
4478 
4479    if (addr == 0x0F00026C)
4480    {
4481       int q = 1;
4482    }
4483 
4484    if (data == 0x20ff)
4485    {
4486       int q = 1;
4487 
4488    }
4489 
4490    SH1MEMLOG("memory_map_write_word 0x%08x 0x%04x", addr, data);
4491 
4492    switch (area)
4493    {
4494    case 0:
4495       //ignore a27 in area 0
4496 
4497       if (mode_pins == 2)//010
4498       {
4499          //sh1->rom[addr & 0xffff];
4500       }
4501       else
4502       {
4503          //mode 000 or 001
4504 
4505          //external memory space
4506 
4507          addr &= 0x3FFFFF;
4508       }
4509       break;
4510    case 1:
4511       if (!sh1->onchip.bsc.bcr)
4512       {
4513          //extern memory space
4514       }
4515       else
4516       {
4517 
4518       }
4519 
4520       if (a27)
4521       {
4522          CDTRACE("wwdram: %08X %04X\n", addr, data);
4523          T2WriteWord(SH1Dram, addr & 0x7FFFF, data);
4524          return;
4525       }
4526 
4527       break;
4528    case 2:
4529    case 3:
4530    case 4:
4531       //external memory space
4532 
4533       if (a27)
4534       {
4535          ygr_sh1_write_word(addr, data);
4536          return;
4537       }
4538       break;
4539    case 5:
4540       //onchip area
4541       if (!a27)
4542       {
4543          onchip_write_word(&sh1->onchip, addr, data);
4544          return;
4545       }
4546       else
4547       {
4548          //external memory space
4549       }
4550       break;
4551    case 6:
4552       if (a27)
4553       {
4554          //external memory space
4555 
4556          //mpeg rom read only
4557 
4558          return;
4559       }
4560       else if (!sh1->onchip.bsc.bcr)
4561       {
4562          //external memory space
4563       }
4564       break;
4565    case 7:
4566       //onchip ram
4567 
4568       CDTRACE("wwram: %08X %04X\n", addr, data);
4569       T2WriteWord(sh1->ram, addr & 0x1fff,data);
4570       //update_cr_response_values(addr);
4571 
4572       return;
4573 
4574       if (a27)
4575       {
4576        //  return sh1->ram[addr & 0xFFF];
4577       }
4578       else
4579       {
4580          //onchip peripherals
4581       }
4582       break;
4583    }
4584 
4585    assert(0);
4586 
4587    return;
4588 }
4589 
memory_map_read_long(struct Sh1 * sh1,u32 addr)4590 u32 memory_map_read_long(struct Sh1* sh1, u32 addr)
4591 {
4592    u8 area = (addr >> 24) & 7;
4593    u8 a27 = (addr >> 27) & 1;
4594    int mode_pins = 0;
4595 
4596    SH1MEMLOG("memory_map_read_long 0x%08x", addr);
4597 
4598    switch (area)
4599    {
4600    case 0:
4601       //ignore a27 in area 0
4602 
4603       return T2ReadLong(SH1Rom, addr & 0xffff);
4604 
4605       //if (mode_pins == 2)//010
4606      //    return sh1->rom[addr & 0xffff];
4607      // else
4608      // {
4609          //mode 000 or 001
4610 
4611          //external memory space
4612 
4613          addr &= 0x3FFFFF;
4614     //  }
4615       break;
4616    case 1:
4617       if (!sh1->onchip.bsc.bcr)
4618       {
4619          //extern memory space
4620       }
4621       else
4622       {
4623 
4624       }
4625 
4626       if (a27)
4627       {
4628          CDTRACE("rlram: %08X\n", addr);
4629          return T2ReadLong(SH1Dram, addr & 0x7FFFF);
4630       }
4631 
4632       break;
4633    case 2:
4634    case 3:
4635    case 4:
4636       //external memory space
4637 
4638       if (a27)
4639       {
4640          return ygr_sh1_read_long(addr);
4641       }
4642       break;
4643    case 5:
4644       //onchip area
4645       if (!a27)
4646          return onchip_read_long(&sh1->onchip, addr);
4647       else
4648       {
4649          //external memory space
4650       }
4651       break;
4652    case 6:
4653       if (a27)
4654       {
4655          //external memory space
4656          //mpeg rom area
4657 
4658          return T2ReadLong(SH1MpegRom, addr & 0x7FFFF);
4659       }
4660       else if (!sh1->onchip.bsc.bcr)
4661       {
4662          //external memory space
4663       }
4664       break;
4665    case 7:
4666       //onchip ram
4667     //  if (a27)
4668       //apparently both are ram?
4669       CDTRACE("rlram: %08X\n", addr);
4670       return T2ReadLong(sh1->ram, addr & 0x1fff);//sh1->ram[addr & 0x1FFF];
4671    //   else
4672     //  {
4673          //onchip peripherals
4674     //  }
4675       break;
4676    }
4677 
4678    return 0;
4679 }
4680 
memory_map_write_long(struct Sh1 * sh1,u32 addr,u32 data)4681 void memory_map_write_long(struct Sh1* sh1, u32 addr, u32 data)
4682 {
4683    u8 area = (addr >> 24) & 7;
4684    u8 a27 = (addr >> 27) & 1;
4685    int mode_pins = 0;
4686 
4687    if (addr == 0x0F00026C && data != 0)
4688    {
4689       int q = 1;
4690    }
4691 
4692    SH1MEMLOG("memory_map_write_long 0x%08x 0x%04x", addr, data);
4693 
4694    switch (area)
4695    {
4696    case 0:
4697       //ignore a27 in area 0
4698 
4699       if (mode_pins == 2)//010
4700       {
4701          //sh1->rom[addr & 0xffff];
4702       }
4703       else
4704       {
4705          //mode 000 or 001
4706 
4707          //external memory space
4708 
4709          addr &= 0x3FFFFF;
4710       }
4711       break;
4712    case 1:
4713       if (!sh1->onchip.bsc.bcr)
4714       {
4715          //extern memory space
4716       }
4717       else
4718       {
4719 
4720       }
4721 
4722       if (a27)
4723       {
4724          CDTRACE("wldram: %08X %08X\n", addr, data);
4725          T2WriteLong(SH1Dram, addr & 0x7FFFF, data);
4726          return;
4727       }
4728 
4729       break;
4730    case 2:
4731    case 3:
4732    case 4:
4733       //external memory space
4734 
4735       //ygr area
4736       if (a27)
4737       {
4738          ygr_sh1_write_long(addr, data);
4739          return;
4740       }
4741       break;
4742    case 5:
4743       //onchip area
4744       if (!a27)
4745       {
4746          onchip_write_long(&sh1->onchip, addr, data);
4747          return;
4748       }
4749       else
4750       {
4751          //external memory space
4752       }
4753       break;
4754    case 6:
4755       if (a27)
4756       {
4757          //external memory space
4758          //mpeg rom area read only
4759 
4760          return;
4761       }
4762       else if (!sh1->onchip.bsc.bcr)
4763       {
4764          //external memory space
4765       }
4766       break;
4767    case 7:
4768       //onchip ram
4769       CDTRACE("wlram: %08X %08X\n", addr, data);
4770       T2WriteLong(sh1->ram, addr & 0x1fff, data);
4771       //update_cr_response_values(addr);
4772       return;
4773       if (a27)
4774       {
4775          //  return sh1->ram[addr & 0xFFF];
4776       }
4777       else
4778       {
4779          //onchip peripherals
4780       }
4781       break;
4782    }
4783 //triggered by yabauseut
4784  //  assert(0);
4785 
4786    return;
4787 }
4788 
Sh1MemoryReadByte(UNUSED SH2_struct * sh,USED_IF_DEBUG u32 addr)4789 u8 FASTCALL Sh1MemoryReadByte(UNUSED SH2_struct *sh, USED_IF_DEBUG u32 addr)
4790 {
4791    return memory_map_read_byte(&sh1_cxt, addr);
4792 }
Sh1MemoryReadWord(UNUSED SH2_struct * sh,USED_IF_DEBUG u32 addr)4793 u16 FASTCALL Sh1MemoryReadWord(UNUSED SH2_struct *sh, USED_IF_DEBUG u32 addr)
4794 {
4795    return memory_map_read_word(&sh1_cxt, addr);
4796 }
Sh1MemoryReadLong(UNUSED SH2_struct * sh,USED_IF_DEBUG u32 addr)4797 u32 FASTCALL Sh1MemoryReadLong(UNUSED SH2_struct *sh, USED_IF_DEBUG u32 addr)
4798 {
4799    return memory_map_read_long(&sh1_cxt, addr);
4800 }
Sh1MemoryWriteByte(UNUSED SH2_struct * sh,USED_IF_DEBUG u32 addr,UNUSED u8 val)4801 void FASTCALL Sh1MemoryWriteByte(UNUSED SH2_struct *sh, USED_IF_DEBUG u32 addr, UNUSED u8 val)
4802 {
4803    memory_map_write_byte(&sh1_cxt, addr, val);
4804 }
Sh1MemoryWriteWord(UNUSED SH2_struct * sh,USED_IF_DEBUG u32 addr,UNUSED u16 val)4805 void FASTCALL Sh1MemoryWriteWord(UNUSED SH2_struct *sh, USED_IF_DEBUG u32 addr, UNUSED u16 val)
4806 {
4807    memory_map_write_word(&sh1_cxt, addr, val);
4808 }
Sh1MemoryWriteLong(UNUSED SH2_struct * sh,USED_IF_DEBUG u32 addr,UNUSED u32 val)4809 void FASTCALL Sh1MemoryWriteLong(UNUSED SH2_struct *sh, USED_IF_DEBUG u32 addr, UNUSED u32 val)
4810 {
4811    memory_map_write_long(&sh1_cxt, addr, val);
4812 }
4813 
4814 
onchip_sci_init(struct Onchip * regs)4815 void onchip_sci_init(struct Onchip * regs)
4816 {
4817    int i;
4818    for (i = 0; i < 2; i++)
4819    {
4820       regs->sci[i].smr = 0;
4821       regs->sci[i].brr = 0xff;
4822       regs->sci[i].scr = 0;
4823       regs->sci[i].tdr = 0xff;
4824       regs->sci[i].ssr = 0x84;
4825       regs->sci[i].rdr = 0;
4826    }
4827 }
4828 
onchip_ad_init(struct Onchip * regs)4829 void onchip_ad_init(struct Onchip * regs)
4830 {
4831    regs->addra = 0;
4832    regs->addrb = 0;
4833    regs->addrc = 0;
4834    regs->addrd = 0;
4835    regs->adcsr = 0;
4836    regs->adcr = 0x7f;
4837 }
4838 
onchip_itu_init(struct Onchip * regs)4839 void onchip_itu_init(struct Onchip * regs)//init values depend on config
4840 {
4841    int i;
4842 
4843    regs->itu.tstr = 0xe0;
4844    regs->itu.tsnc = 0xe0;
4845    regs->itu.tmdr = 0x80;
4846    regs->itu.tfcr = 0xc0;
4847    regs->itu.tocr = 0xff;
4848 
4849    for (i = 0; i < 5; i++)
4850    {
4851       regs->itu.channel[i].tcr = 0x80;
4852       regs->itu.channel[i].tior = 0x88;
4853       regs->itu.channel[i].tier = 0xf8;
4854       regs->itu.channel[i].tsr = 0xf8;
4855       regs->itu.channel[i].tcnt = 0;
4856       regs->itu.channel[i].gra = 0xff;
4857       regs->itu.channel[i].grb = 0xff;
4858       //not used for channels 0-2
4859       regs->itu.channel[i].bra = 0xff;
4860       regs->itu.channel[i].brb = 0xff;
4861    }
4862 }
4863 
onchip_dmac_init(struct Onchip * regs)4864 void onchip_dmac_init(struct Onchip * regs)
4865 {
4866    int i;
4867    for (i = 0; i < 4; i++)
4868    {
4869       regs->dmac.channel[i].sar = 0;//undefined
4870       regs->dmac.channel[i].dar = 0;//undefined
4871       regs->dmac.channel[i].tcr = 0;//undefined
4872       regs->dmac.channel[i].chcr = 0;
4873    }
4874 
4875    regs->dmac.dmaor = 0;
4876 }
4877 
onchip_intc_init(struct Onchip * regs)4878 void onchip_intc_init(struct Onchip * regs)
4879 {
4880    regs->intc.ipra = 0;
4881    regs->intc.iprb = 0;
4882    regs->intc.iprc = 0;
4883    regs->intc.iprd = 0;
4884    regs->intc.ipre = 0;
4885 }
4886 
onchip_ubc_init(struct Onchip * regs)4887 void onchip_ubc_init(struct Onchip * regs)
4888 {
4889    regs->ubc.bar = 0;
4890    regs->ubc.bamr = 0;
4891    regs->ubc.bbr = 0;
4892 }
4893 
onchip_bsc_init(struct Onchip * regs)4894 void onchip_bsc_init(struct Onchip * regs)
4895 {
4896    regs->bsc.bcr = 0;
4897    regs->bsc.wcr1 = 0;
4898    regs->bsc.wcr2 = 0;
4899    regs->bsc.wcr3 = 0;
4900    regs->bsc.dcr = 0;
4901    regs->bsc.pcr = 0;
4902    regs->bsc.rcr = 0;
4903    regs->bsc.rtcsr = 0;
4904    regs->bsc.rtcnt = 0;
4905    regs->bsc.rtcor = 0;
4906 }
4907 
onchip_wdt_init(struct Onchip * regs)4908 void onchip_wdt_init(struct Onchip * regs)
4909 {
4910    regs->wdt.tcsr = 0;
4911    regs->wdt.tcnt = 0;
4912    regs->wdt.rstcsr = 0;
4913 }
4914 
onchip_pfc_init(struct Onchip * regs)4915 void onchip_pfc_init(struct Onchip * regs)
4916 {
4917    regs->pfc.paior = 0;
4918    regs->pfc.pacr1 = 0x3302;
4919    regs->pfc.pacr2 = 0xff95;
4920    regs->pfc.pbior = 0;
4921    regs->pfc.pbcr1 = 0;
4922    regs->pfc.pbcr2 = 0;
4923    regs->cascr = 0x5fff;
4924 }
4925 
onchip_tpc_init(struct Onchip * regs)4926 void onchip_tpc_init(struct Onchip * regs)
4927 {
4928    regs->tpc.tpmr = 0xf0;
4929    regs->tpc.tpcr = 0xff;
4930    regs->tpc.nderb = 0;
4931    regs->tpc.ndera = 0;
4932    regs->tpc.ndrb = 0;
4933    regs->tpc.ndra = 0;
4934 }
4935 
onchip_init(struct Sh1 * sh1)4936 void onchip_init(struct Sh1 * sh1)
4937 {
4938    onchip_sci_init(&sh1->onchip);
4939    onchip_ad_init(&sh1->onchip);
4940    onchip_itu_init(&sh1->onchip);
4941    onchip_dmac_init(&sh1->onchip);
4942    onchip_intc_init(&sh1->onchip);
4943    onchip_ubc_init(&sh1->onchip);
4944    onchip_bsc_init(&sh1->onchip);
4945    onchip_wdt_init(&sh1->onchip);
4946 
4947    sh1->onchip.sbycr = 0;
4948 
4949    sh1->onchip.padr = 0;
4950    sh1->onchip.pbdr = 0;
4951 
4952    onchip_pfc_init(&sh1->onchip);
4953 
4954    sh1->onchip.pcdr = 0;
4955 
4956    onchip_tpc_init(&sh1->onchip);
4957 }
4958 
sh1_init(struct Sh1 * sh1)4959 void sh1_init(struct Sh1* sh1)
4960 {
4961    memset(sh1, 0, sizeof(struct Sh1));
4962    onchip_init(sh1);
4963 }
4964 
sh1_init_func()4965 void sh1_init_func()
4966 {
4967    sh1_init(&sh1_cxt);
4968 
4969    memset(SH1Dram, 0, 0x80000);
4970 
4971    cdd_reset();
4972 
4973    mpeg_card_init();
4974 
4975    sh1_cxt.onchip.pbdr = 0x40c;
4976 }
4977 
4978 
4979 static int cycles_since = 0;
4980 
tick_timer(int which)4981 void tick_timer(int which)
4982 {
4983    if (sh1_cxt.onchip.itu.tstr & (1 << which))//timer is counting
4984    {
4985       u16 old_tcnt = sh1_cxt.onchip.itu.channel[which].tcnt;
4986 
4987       switch (sh1_cxt.onchip.itu.channel[which].tcr & 7)
4988       {
4989       case 0:
4990          sh1_cxt.onchip.itu.channel[which].tcnt++; //internal clock speed
4991          break;
4992       case 1:
4993          if (sh1_cxt.onchip.itu.channel[which].tcnt_fraction == 2)
4994          {
4995             sh1_cxt.onchip.itu.channel[which].tcnt++; // phi/2
4996             sh1_cxt.onchip.itu.channel[which].tcnt_fraction = 0;
4997          }
4998 
4999          sh1_cxt.onchip.itu.channel[which].tcnt_fraction++;
5000          break;
5001       case 2:
5002          if (sh1_cxt.onchip.itu.channel[which].tcnt_fraction == 4)
5003          {
5004             sh1_cxt.onchip.itu.channel[which].tcnt++; // phi/4
5005             sh1_cxt.onchip.itu.channel[which].tcnt_fraction = 0;
5006          }
5007 
5008          sh1_cxt.onchip.itu.channel[which].tcnt_fraction++;
5009          break;
5010       case 3:
5011          if (sh1_cxt.onchip.itu.channel[which].tcnt_fraction == 8)
5012          {
5013             sh1_cxt.onchip.itu.channel[which].tcnt++; // phi/8
5014             sh1_cxt.onchip.itu.channel[which].tcnt_fraction = 0;
5015          }
5016 
5017          sh1_cxt.onchip.itu.channel[which].tcnt_fraction++;
5018          break;
5019       default:
5020          assert(0);
5021       }
5022 
5023       if (sh1_cxt.onchip.itu.channel[which].tier & (1 << 2))
5024       {
5025          if (sh1_cxt.onchip.itu.channel[which].tcnt < old_tcnt)
5026          {
5027             //overflow interrupt
5028             TIMERTRACE("*****TCNT4 OVF interrupt*******\n");
5029 
5030             if (which == 4)
5031                SH2SendInterrupt(SH1, 98, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5032 
5033             cycles_since = 0;
5034          }
5035       }
5036    }
5037 
5038    //timer compare a
5039    if (sh1_cxt.onchip.itu.channel[which].gra == sh1_cxt.onchip.itu.channel[which].tcnt)
5040    {
5041       switch (sh1_cxt.onchip.itu.channel[which].tior & 7)
5042       {
5043       case 0:
5044          sh1_cxt.onchip.itu.channel[which].tsr |= 1;
5045 
5046          //cleared by gra compare match
5047          if(((sh1_cxt.onchip.itu.channel[which].tcr >> 5) & 3) == 1)
5048             sh1_cxt.onchip.itu.channel[which].tcnt = 0;
5049 
5050          if (sh1_cxt.onchip.itu.channel[which].tier & 1)
5051             SH2SendInterrupt(SH1, 96, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5052          break;
5053       case 1:
5054          //output 0
5055          sh1_cxt.onchip.itu.channel[which].tsr &= ~(1 << 1);
5056          break;
5057       case 2:
5058          //output 1
5059          sh1_cxt.onchip.itu.channel[which].tsr |= (1 << 1);
5060          break;
5061       case 3:
5062          //toggles
5063          break;
5064       case 4:
5065          break;
5066       case 5:
5067          break;
5068       case 6:
5069          break;
5070       case 7:
5071          break;
5072       }
5073    }
5074 
5075    //timer compare b
5076    if (sh1_cxt.onchip.itu.channel[which].grb == sh1_cxt.onchip.itu.channel[which].tcnt)
5077    {
5078       switch ((sh1_cxt.onchip.itu.channel[which].tior >> 4) & 7)
5079       {
5080       case 0:
5081          sh1_cxt.onchip.itu.channel[which].tsr |= 2;
5082 
5083          if (((sh1_cxt.onchip.itu.channel[which].tcr >> 5) & 3) == 2)
5084             sh1_cxt.onchip.itu.channel[which].tcnt = 0;
5085 
5086          if (sh1_cxt.onchip.itu.channel[which].tier & 2)
5087             SH2SendInterrupt(SH1, 97, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5088          break;
5089       case 1:
5090          //output 0
5091          sh1_cxt.onchip.itu.channel[which].tsr &= ~(1 << 1);
5092          break;
5093       case 2:
5094          //output 1
5095          sh1_cxt.onchip.itu.channel[which].tsr |= (1 << 1);
5096          break;
5097       case 3:
5098          //toggles
5099          break;
5100       case 4:
5101          break;
5102       case 5:
5103          break;
5104       case 6:
5105          break;
5106       case 7:
5107          break;
5108       }
5109    }
5110 }
5111 
update_tcnt_fraction(int which,s32 cycles,u8 division)5112 u16 update_tcnt_fraction(int which, s32 cycles, u8 division)
5113 {
5114    int remainder = 0;
5115 
5116    sh1_cxt.onchip.itu.channel[which].tcnt_fraction += cycles % division;
5117 
5118    if (sh1_cxt.onchip.itu.channel[which].tcnt_fraction >= division)
5119    {
5120       remainder = 1;
5121       sh1_cxt.onchip.itu.channel[which].tcnt_fraction -= division;
5122    }
5123    return sh1_cxt.onchip.itu.channel[which].tcnt + (cycles / division) + remainder;
5124 }
5125 
update_tcnt_fast(int which,s32 cycles)5126 u16 update_tcnt_fast(int which, s32 cycles)
5127 {
5128 
5129    switch (sh1_cxt.onchip.itu.channel[which].tcr & 7)
5130    {
5131    case 0:
5132       return sh1_cxt.onchip.itu.channel[which].tcnt + cycles; //internal clock speed
5133       break;
5134    case 1:
5135       return update_tcnt_fraction(which, cycles, 2);
5136       break;
5137    case 2:
5138       return update_tcnt_fraction(which, cycles, 4);
5139       break;
5140    case 3:
5141       return update_tcnt_fraction(which, cycles, 8);
5142       break;
5143    default:
5144       assert(0);
5145    }
5146 
5147    return 0;
5148 }
5149 
check_gr_range(u16 gr,u16 old_tcnt,u16 new_tcnt)5150 int check_gr_range(u16 gr, u16 old_tcnt, u16 new_tcnt)
5151 {
5152    if (new_tcnt < old_tcnt)
5153    {
5154       //overflow occured
5155 
5156       if (gr >= old_tcnt || gr <= new_tcnt)
5157       {
5158          return 1;
5159       }
5160    }
5161    else
5162    {
5163       //linear range check
5164       if (gr >= old_tcnt && gr <= new_tcnt)
5165       {
5166          return 1;
5167       }
5168    }
5169 
5170    return 0;
5171 }
5172 
tick_timer_fast(int which,s32 cycles)5173 void tick_timer_fast(int which, s32 cycles)
5174 {
5175    u16 old_tcnt = sh1_cxt.onchip.itu.channel[which].tcnt;
5176    u16 new_tcnt = 0;
5177    int timer_is_counting = sh1_cxt.onchip.itu.tstr & (1 << which);
5178    int gra_match = 0, grb_match = 0;
5179 
5180    if (timer_is_counting)
5181    {
5182       new_tcnt = update_tcnt_fast(which, cycles);
5183    }
5184 
5185    gra_match = check_gr_range(sh1_cxt.onchip.itu.channel[which].gra, old_tcnt, new_tcnt);
5186    grb_match = check_gr_range(sh1_cxt.onchip.itu.channel[which].grb, old_tcnt, new_tcnt);
5187 
5188    if (timer_is_counting && (sh1_cxt.onchip.itu.channel[which].tier & (1 << 2)))
5189    {
5190       if (new_tcnt < old_tcnt)
5191       {
5192          //overflow interrupt
5193          TIMERTRACE("*****TCNT4 OVF interrupt*******\n");
5194 
5195          if (which == 4)
5196             SH2SendInterrupt(SH1, 98, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5197 
5198          cycles_since = 0;
5199       }
5200    }
5201 
5202    //timer compare a
5203    if (gra_match)
5204    {
5205       switch (sh1_cxt.onchip.itu.channel[which].tior & 7)
5206       {
5207       case 0:
5208          sh1_cxt.onchip.itu.channel[which].tsr |= 1;
5209 
5210          //cleared by gra compare match
5211          if (((sh1_cxt.onchip.itu.channel[which].tcr >> 5) & 3) == 1)
5212             new_tcnt = 0;
5213 
5214          if (sh1_cxt.onchip.itu.channel[which].tier & 1)
5215             SH2SendInterrupt(SH1, 96, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5216          break;
5217       case 1:
5218          //output 0
5219          sh1_cxt.onchip.itu.channel[which].tsr &= ~(1 << 1);
5220          break;
5221       case 2:
5222          //output 1
5223          sh1_cxt.onchip.itu.channel[which].tsr |= (1 << 1);
5224          break;
5225       case 3:
5226          //toggles
5227          break;
5228       case 4:
5229          break;
5230       case 5:
5231          break;
5232       case 6:
5233          break;
5234       case 7:
5235          break;
5236       }
5237    }
5238 
5239    //timer compare b
5240    if (grb_match)
5241    {
5242       switch ((sh1_cxt.onchip.itu.channel[which].tior >> 4) & 7)
5243       {
5244       case 0:
5245          sh1_cxt.onchip.itu.channel[which].tsr |= 2;
5246 
5247          if (((sh1_cxt.onchip.itu.channel[which].tcr >> 5) & 3) == 2)
5248             new_tcnt = 0;
5249 
5250          if (sh1_cxt.onchip.itu.channel[which].tier & 2)
5251             SH2SendInterrupt(SH1, 97, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5252          break;
5253       case 1:
5254          //output 0
5255          sh1_cxt.onchip.itu.channel[which].tsr &= ~(1 << 1);
5256          break;
5257       case 2:
5258          //output 1
5259          sh1_cxt.onchip.itu.channel[which].tsr |= (1 << 1);
5260          break;
5261       case 3:
5262          //toggles
5263          break;
5264       case 4:
5265          break;
5266       case 5:
5267          break;
5268       case 6:
5269          break;
5270       case 7:
5271          break;
5272       }
5273    }
5274 
5275    sh1_cxt.onchip.itu.channel[which].tcnt = new_tcnt;
5276 }
5277 
5278 
5279 void sh1_serial_recieve_bit(int bit, int channel);
5280 void sh1_serial_transmit_bit(int channel, int* output_bit);
5281 
receive_bit_from_cdd()5282 void receive_bit_from_cdd()
5283 {
5284    u8 receive_from_cdd = cd_drive_get_serial_bit();
5285    sh1_serial_recieve_bit(receive_from_cdd, 0);
5286 }
5287 
transmit_bit_to_cdd()5288 void transmit_bit_to_cdd()
5289 {
5290    int send_to_cdd = 0;
5291    sh1_serial_transmit_bit(0, &send_to_cdd);
5292    cd_drive_set_serial_bit(send_to_cdd);
5293 }
5294 void cd_serial_exec();
tick_serial(int channel)5295 void tick_serial(int channel)
5296 {
5297    u8 bit_rate = sh1_cxt.onchip.sci[channel].brr;
5298    //number of cycles per bit is determined by
5299    //(brr+1)*4 for settings with an error rate of 0
5300    //sh1 uses 0x63 == 50,000 bits per second
5301    int cycles_per_bit = (bit_rate + 1) * 4;
5302    u8 clock_mode;
5303 
5304    static int was_printed = 0;
5305    if (sh1_cxt.onchip.sci[0].ssr & SCI_TEND)
5306    {
5307       if (!was_printed)
5308       {
5309          was_printed = 1;
5310       }
5311       sh1_cxt.onchip.sci[channel].serial_clock_counter = 0;
5312       //tend is set, no transmission
5313       return;
5314    }
5315    was_printed = 0;
5316 
5317    //if (!sh1_cxt.onchip.sci[channel].tdr_written)
5318    //   return;
5319 
5320    clock_mode = sh1_cxt.onchip.sci[channel].smr & 3;
5321    if (clock_mode == 3 || clock_mode == 2)//clock pin set as input
5322       assert(0);
5323 
5324    sh1_cxt.onchip.sci[channel].serial_clock_counter++;
5325 
5326    if (sh1_cxt.onchip.sci[channel].serial_clock_counter > cycles_per_bit)
5327    {
5328       if (sh1_cxt.onchip.sci[channel].scr & SCI_TE &&
5329          sh1_cxt.onchip.sci[channel].scr & SCI_RE)
5330       {
5331          receive_bit_from_cdd();
5332          transmit_bit_to_cdd();
5333       }
5334 
5335       sh1_cxt.onchip.sci[channel].serial_clock_counter = 0;
5336    }
5337 }
5338 
5339 #define FAST_TIMERS
5340 
sh1_onchip_run_cycle()5341 void sh1_onchip_run_cycle()
5342 {
5343 #ifndef FAST_TIMERS
5344    tick_timer(3);
5345    tick_timer(4);
5346 #endif
5347 
5348    tick_serial(0);
5349 
5350    cycles_since++;
5351 }
5352 
sh1_onchip_run_cycles(s32 cycles)5353 void sh1_onchip_run_cycles(s32 cycles)
5354 {
5355    int i;
5356 
5357 #ifdef FAST_TIMERS
5358    tick_timer_fast(3, cycles);
5359    tick_timer_fast(4, cycles);
5360 #endif
5361 
5362    for (i = 0; i < cycles; i++)
5363       sh1_onchip_run_cycle();
5364 }
5365 
5366 //u16 sh1_fetch(struct Sh1* sh1)
5367 //{
5368 //   u32 PC = 0;
5369 //   return sh1->rom[PC & 0xffff];
5370 //}
5371 
5372 //int sh1_execute_instruction(struct Sh1 * sh1)
5373 //{
5374 //   u16 instruction = sh1_fetch(sh1);
5375 //   int cycles_executed = 1;
5376 //   return cycles_executed;
5377 //}
5378 
5379 
test_byte_access(struct Sh1 * sh1,u32 addr)5380 void test_byte_access(struct Sh1* sh1, u32 addr)
5381 {
5382    u8 test_val = 0xff, result;
5383    memory_map_write_byte(sh1, addr, test_val);
5384    result = memory_map_read_byte(sh1, addr);
5385 }
5386 
test_word_access(struct Sh1 * sh1,u32 addr)5387 void test_word_access(struct Sh1* sh1, u32 addr)
5388 {
5389    u16 test_val = 0xffff, result;
5390    memory_map_write_word(sh1, addr, test_val);
5391    result = memory_map_read_word(sh1, addr);
5392 }
5393 
test_long_access(struct Sh1 * sh1,u32 addr)5394 void test_long_access(struct Sh1* sh1, u32 addr)
5395 {
5396    u32 test_val = 0xffffffff, result;
5397    memory_map_write_long(sh1, addr, test_val);
5398    result = memory_map_read_long(sh1, addr);
5399 }
5400 
test_mem_map(struct Sh1 * sh1)5401 void test_mem_map(struct Sh1* sh1)
5402 {
5403 	int i;
5404 
5405    //ygr
5406    memory_map_write_long(sh1, 0xa000000, 0xdeadbeef);
5407 
5408    //sh1 dram
5409    for (i = 0; i < 0x7FFFF; i += 4)
5410    {
5411       memory_map_write_long(sh1, 0x9000000 + i, 0xdeadbeef);
5412       memory_map_read_long(sh1, 0x9000000 + i);
5413    }
5414 
5415    for (i = 0; i < 0x7FFFF; i += 2)
5416    {
5417       memory_map_write_word(sh1, 0x9000000 + i, 0xdead);
5418       memory_map_read_word(sh1, 0x9000000 + i);
5419    }
5420 
5421    for (i = 0; i < 0x7FFFF; i++)
5422    {
5423       memory_map_write_byte(sh1, 0x9000000 + i, 0xde);
5424       memory_map_read_byte(sh1, 0x9000000 + i);
5425    }
5426 
5427    //mpeg rom
5428    for (i = 0; i < 0x7FFFF; i += 4)
5429    {
5430       memory_map_write_long(sh1, 0xe000000 + i, 0xdeadbeef);
5431       memory_map_read_long(sh1, 0xe000000 + i);
5432    }
5433 
5434    for (i = 0; i < 0x7FFFF; i += 2)
5435    {
5436       memory_map_write_word(sh1, 0xe000000 + i, 0xdead);
5437       memory_map_read_word(sh1, 0xe000000 + i);
5438    }
5439 
5440    for (i = 0; i < 0x7FFFF; i++)
5441    {
5442       memory_map_write_byte(sh1, 0xe000000 + i, 0xde);
5443       memory_map_read_byte(sh1, 0xe000000 + i);
5444    }
5445 }
5446 
sh1_exec(struct Sh1 * sh1,s32 cycles)5447 void sh1_exec(struct Sh1 * sh1, s32 cycles)
5448 {
5449 #if 0
5450    u32 i;
5451 
5452    for (i = 0x5FFFEC0; i < 0x5FFFFFF; i++)
5453    {
5454       test_byte_access(sh1, i);
5455    }
5456 
5457    for (i = 0x5FFFEC0; i < 0x5FFFFFF; i+=2)
5458    {
5459       test_word_access(sh1, i);
5460    }
5461 
5462    for (i = 0x5FFFEC0; i < 0x5FFFFFF; i += 4)
5463    {
5464       test_long_access(sh1, i);
5465    }
5466 
5467    test_mem_map(sh1);
5468 
5469    s32 cycles_temp = sh1->cycles_remainder - cycles;
5470    while (cycles_temp < 0)
5471    {
5472       int cycles = sh1_execute_instruction(sh1);
5473       cycles_temp += cycles;
5474    }
5475    sh1->cycles_remainder = cycles_temp;
5476 #endif
5477 }
5478 #if 0
5479 int sh1_load_rom(struct Sh1* sh1, const char* filename)
5480 {
5481    size_t size = 0;
5482    FILE * fp = NULL;
5483 
5484    if (!sh1)
5485       return -1;
5486 
5487    if (!filename)
5488       return -1;
5489 
5490    fp = fopen(filename, "rb");
5491 
5492    if (!fp)
5493       return -1;
5494 
5495    if (!fseek(fp, 0, SEEK_END))
5496       return -1;
5497 
5498    size = ftell(fp);
5499 
5500    if (size != 0x8000)
5501       return -1;
5502 
5503    if (!fseek(fp, 0, SEEK_SET))
5504       return -1;
5505 
5506    size = fread(&sh1->rom, sizeof(u8), 0x8000, fp);
5507 
5508    if (size != 0x8000)
5509       return -1;
5510 
5511    return 1;
5512 }
5513 #endif
5514 int num_output_enables = 0;
5515 
sh1_set_output_enable_rising_edge()5516 void sh1_set_output_enable_rising_edge()
5517 {
5518 #ifdef ENABLE_TSUNAMI
5519    tsunami_log_value("OE", 1, 1);
5520 #endif
5521 }
5522 //signal from the cd drive board microcontroller
5523 //falling edge
sh1_set_output_enable_falling_edge()5524 void sh1_set_output_enable_falling_edge()
5525 {
5526 #ifdef ENABLE_TSUNAMI
5527    //input capture
5528    tsunami_log_value("OE", 0, 1);
5529 #endif
5530 
5531    if (sh1_cxt.onchip.itu.channel[3].tsr & (1 << 1))
5532    {
5533       //imfb is set, don't overflow again?
5534       return;
5535    }
5536 
5537    if (((sh1_cxt.onchip.itu.channel[3].tior >> 4) & 7) != 5)
5538    {
5539       //grb is not an input capture reg
5540       //capturing the falling edge
5541       return;
5542    }
5543 
5544 
5545    if (!(sh1_cxt.onchip.itu.channel[3].tier & (1 << 1)))
5546    {
5547       //imieb intterupt is disbaled
5548       return;
5549    }
5550 
5551    num_output_enables++;
5552 
5553    //store old grb value in brb
5554    sh1_cxt.onchip.itu.channel[3].brb = sh1_cxt.onchip.itu.channel[3].grb;
5555 
5556    //put tcnt value in grb
5557    sh1_cxt.onchip.itu.channel[3].grb = sh1_cxt.onchip.itu.channel[3].tcnt;
5558 
5559    //clear tcnt
5560    if(((sh1_cxt.onchip.itu.channel[3].tcr >> 5) & 3) == 2)
5561       sh1_cxt.onchip.itu.channel[3].tcnt = 0;
5562 
5563    sh1_cxt.onchip.itu.channel[3].tsr |= (1 << 1);
5564 
5565    //trigger an interrupt
5566    SH2SendInterrupt(SH1, 93, (sh1_cxt.onchip.intc.iprd >> 8) & 0xf);
5567 }
5568 //extern int serial_counter;
sh1_serial_recieve_bit(int bit,int channel)5569 void sh1_serial_recieve_bit(int bit, int channel)
5570 {
5571    sh1_cxt.onchip.sci[channel].rsr <<= 1;
5572    sh1_cxt.onchip.sci[channel].rsr |= bit;
5573    sh1_cxt.onchip.sci[channel].rsr_counter++;
5574 
5575 #ifdef ENABLE_TSUNAMI
5576    tsunami_log_value("SCK", sh1_cxt.onchip.sci[channel].rsr_counter, 4);
5577 #endif
5578 
5579    //a full byte has been received, transfer data to rdr
5580    if (sh1_cxt.onchip.sci[channel].rsr_counter == 8)
5581    {
5582       sh1_cxt.onchip.sci[channel].rsr_counter = 0;
5583       sh1_cxt.onchip.sci[channel].rdr = sh1_cxt.onchip.sci[channel].rsr;
5584       sh1_cxt.onchip.sci[channel].rsr = 0;
5585       sh1_cxt.onchip.sci[channel].ssr |= SCI_RDRF;
5586 
5587 #ifdef ENABLE_TSUNAMI
5588       tsunami_log_value("STA", sh1_cxt.onchip.sci[channel].rdr, 8);
5589 #endif
5590 
5591       //trigger interrupt
5592       if (sh1_cxt.onchip.sci[0].scr & SCI_RIE)//receive data full interrupt is enabled
5593       {
5594          SH2SendInterrupt(SH1, 101, sh1_cxt.onchip.intc.iprd & 0xf);
5595 #ifdef ENABLE_TSUNAMI
5596          tsunami_log_pulse("RXIO", 1);
5597 #endif
5598       }
5599    }
5600 }
5601 
5602 
5603 
sh1_serial_transmit_bit(int channel,int * output_bit)5604 void sh1_serial_transmit_bit(int channel, int* output_bit)
5605 {
5606    *output_bit = sh1_cxt.onchip.sci[channel].tsr & 1;
5607    if (sh1_cxt.onchip.sci[channel].tsr_counter) {
5608        sh1_cxt.onchip.sci[channel].tsr >>= 1;
5609        sh1_cxt.onchip.sci[channel].tsr_counter--;
5610    }
5611 
5612    //a full byte has been transferred, fill tsr again
5613    if (sh1_cxt.onchip.sci[channel].tsr_counter == 0)
5614    {
5615       if (sh1_cxt.onchip.sci[channel].tdr_written)
5616       {
5617          sh1_cxt.onchip.sci[channel].tsr = sh1_cxt.onchip.sci[channel].tdr;
5618          sh1_cxt.onchip.sci[channel].tsr_counter = 8;
5619          sh1_cxt.onchip.sci[channel].tdr_written = 0;
5620          sh1_cxt.onchip.sci[channel].ssr |= SCI_TDRE;
5621       }
5622       else
5623       {
5624          //end of transmission
5625          sh1_cxt.onchip.sci[channel].ssr |= SCI_TEND;
5626       }
5627 
5628       if (sh1_cxt.onchip.sci[0].scr & SCI_TIE)
5629       {
5630          assert(0);
5631        //  SH2SendInterrupt(SH1, 101, sh1_cxt.onchip.intc.iprd & 0xf);
5632       }
5633    }
5634 }
5635 
5636 //pb2
sh1_set_start(int state)5637 void sh1_set_start(int state)
5638 {
5639 #ifdef ENABLE_TSUNAMI
5640    tsunami_log_value("START", state,1);
5641 #endif
5642 
5643    if (state)
5644       sh1_cxt.onchip.pbdr &= ~0x04;
5645    else
5646       sh1_cxt.onchip.pbdr |= 0x04;
5647 }
5648 
tick_dma(int which)5649 void tick_dma(int which)
5650 {
5651    u8 destination_mode, source_mode, is_word_size;
5652    s8 source_increment, dest_increment;
5653    u8 mode = (sh1_cxt.onchip.dmac.channel[which].chcr >> 8) & 0xf;
5654 
5655    if ((sh1_cxt.onchip.dmac.dmaor & 7) != 1 || //ae, nmif == 0, dme == 1
5656       (sh1_cxt.onchip.dmac.channel[which].chcr & 3) != 1) //te == 0, de == 1
5657       return;
5658 
5659    //not dreq based dma
5660    if (!(mode == 2 || mode == 3))//put / get sector data uses mode 3
5661       return;
5662 
5663    if (!ygr_dreq_asserted())
5664       return;
5665 
5666    destination_mode = sh1_cxt.onchip.dmac.channel[which].chcr >> 14;
5667    source_mode = (sh1_cxt.onchip.dmac.channel[which].chcr >> 12) & 3;
5668    is_word_size = (sh1_cxt.onchip.dmac.channel[which].chcr >> 3) & 1;//otherwise byte size
5669 
5670    source_increment = 0;
5671    dest_increment = 0;
5672 
5673    //update addresses
5674    //mode 0 means fixed
5675    if (source_mode == 1)
5676       source_increment = 2;
5677    else if (source_mode == 2)
5678       source_increment = -2;
5679 
5680    if (destination_mode == 1)
5681       dest_increment = 2;
5682    else if (destination_mode == 2)
5683       dest_increment = -2;
5684 
5685    if (is_word_size)
5686    {
5687       u16 src_val = memory_map_read_word(&sh1_cxt, sh1_cxt.onchip.dmac.channel[which].sar);
5688       memory_map_write_word(&sh1_cxt, sh1_cxt.onchip.dmac.channel[which].dar, src_val);
5689    }
5690    else
5691    {
5692       u8 src_val = memory_map_read_byte(&sh1_cxt, sh1_cxt.onchip.dmac.channel[which].sar);
5693       memory_map_write_byte(&sh1_cxt, sh1_cxt.onchip.dmac.channel[which].dar, src_val);
5694    }
5695 
5696    sh1_cxt.onchip.dmac.channel[which].sar += source_increment;
5697    sh1_cxt.onchip.dmac.channel[which].dar += dest_increment;
5698    sh1_cxt.onchip.dmac.channel[which].tcr--;
5699 
5700    if (sh1_cxt.onchip.dmac.channel[which].tcr == 0)
5701    {
5702       sh1_cxt.onchip.dmac.channel[which].is_active = 0;
5703       sh1_cxt.onchip.dmac.channel[which].chcr |= 2;//te dma has ended normally
5704 
5705       if (sh1_cxt.onchip.dmac.channel[which].chcr & 4)
5706       {
5707          //just do dma1 for now
5708          SH2SendInterrupt(SH1, 74, (sh1_cxt.onchip.intc.iprc >> 12) & 0xf);
5709       }
5710    }
5711 }
5712 int print_mpeg_jump = 0;
5713 
5714 
sh1_dma_exec(s32 cycles)5715 void sh1_dma_exec(s32 cycles)
5716 {
5717 	int i;
5718 #if 0 //re-enable when mpeg is fixed
5719    if (SH1->regs.PC == 0xf914)
5720       print_mpeg_jump = 1;
5721 
5722    if (SH1->regs.PC == 0xf91c)
5723       print_mpeg_jump = 0;
5724 
5725    if (print_mpeg_jump && (SH1->regs.PC == 0xf926))
5726       CDLOG("MPEG Jump to %08x\n", SH1->regs.R[0]);
5727 
5728    //pass mpeg card presence test
5729    if (SH1->regs.PC == 0x4c6)
5730    {
5731       mpeg_card_set_all_irqs();
5732    }
5733 
5734    //sh1_cxt.onchip.dmac.channel[2].chcr & 2 must not be set at 0xbd1c to pass test
5735 
5736    //must trigger imia1 to pass test?
5737    if (SH1->regs.PC == 0xbd38)
5738       sh1_cxt.onchip.dmac.channel[2].chcr |= 2;
5739 
5740    if (SH1->regs.PC == 0xbece)
5741       sh1_cxt.onchip.dmac.channel[3].chcr |= 2;
5742 #endif
5743    for (i = 0; i < cycles; i++)
5744       tick_dma(1);
5745 }
5746 
sh1_dma_init(int which)5747 void sh1_dma_init(int which)
5748 {
5749    //de, dme, mnif, ae, te must all be zero to start a dma
5750    //but just check de and dme for now
5751    if (sh1_cxt.onchip.dmac.dmaor & 1 && //dma enabled on all channels
5752       sh1_cxt.onchip.dmac.channel[which].chcr & 1)//dma enabled on this channel
5753    {
5754       sh1_cxt.onchip.dmac.channel[which].is_active = 1;
5755       sh1_cxt.onchip.dmac.channel[which].chcr &= 0xfffd;//clear te bit to indicate dma is active
5756    }
5757 }
5758 
5759 
sh1_dreq_asserted(int which)5760 void sh1_dreq_asserted(int which)
5761 {
5762    if (!sh1_cxt.onchip.dmac.channel[which].is_active)
5763       sh1_dma_init(which);
5764 
5765    tick_dma(which);
5766 }
5767 
sh1_assert_tioca(int which)5768 void sh1_assert_tioca(int which)
5769 {
5770    //capture falling edge of input
5771    if ((sh1_cxt.onchip.itu.channel[which].tior & 7) == 5)
5772    {
5773       //store tcnt in gra
5774       sh1_cxt.onchip.itu.channel[which].gra = sh1_cxt.onchip.itu.channel[which].tcnt;
5775       //set imfa
5776       sh1_cxt.onchip.itu.channel[which].tsr |= 1;
5777 
5778       if (sh1_cxt.onchip.itu.channel[which].tier & 1)
5779       {
5780          //imia
5781          if(which == 0)
5782             SH2SendInterrupt(SH1, 80, (sh1_cxt.onchip.intc.iprc >> 4) & 0xf);
5783          else if (which == 1)
5784             SH2SendInterrupt(SH1, 84, (sh1_cxt.onchip.intc.iprc >> 0) & 0xf);
5785          else if (which == 2)
5786             SH2SendInterrupt(SH1, 88, (sh1_cxt.onchip.intc.iprd >> 12) & 0xf);
5787          else if (which == 3)
5788             SH2SendInterrupt(SH1, 92, (sh1_cxt.onchip.intc.iprd >> 8) & 0xf);
5789          else if (which == 4)
5790             SH2SendInterrupt(SH1, 96, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5791       }
5792 
5793    }
5794 }
5795 
sh1_assert_tiocb(int which)5796 void sh1_assert_tiocb(int which)
5797 {
5798    //capture falling edge of input
5799    if (((sh1_cxt.onchip.itu.channel[which].tior >> 4) & 7) == 5)
5800    {
5801       //store tcnt in gra
5802       sh1_cxt.onchip.itu.channel[which].grb = sh1_cxt.onchip.itu.channel[which].tcnt;
5803       //set imfa
5804       sh1_cxt.onchip.itu.channel[which].tsr |= 2;
5805 
5806       if (sh1_cxt.onchip.itu.channel[which].tier & 2)
5807       {
5808          //imib
5809          if (which == 0)
5810             SH2SendInterrupt(SH1, 81, (sh1_cxt.onchip.intc.iprc >> 4) & 0xf);
5811          else if (which == 1)
5812             SH2SendInterrupt(SH1, 85, (sh1_cxt.onchip.intc.iprc >> 0) & 0xf);
5813          else if (which == 2)
5814             SH2SendInterrupt(SH1, 89, (sh1_cxt.onchip.intc.iprd >> 12) & 0xf);
5815          else if (which == 3)
5816             SH2SendInterrupt(SH1, 93, (sh1_cxt.onchip.intc.iprd >> 8) & 0xf);
5817          else if (which == 4)
5818             SH2SendInterrupt(SH1, 97, (sh1_cxt.onchip.intc.iprd >> 4) & 0xf);
5819       }
5820    }
5821 }
5822