| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 364 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
|
| /dports/www/node10/node-v10.24.1/deps/v8/src/wasm/baseline/arm64/ |
| H A D | liftoff-assembler-arm64.h | 330 void LiftoffAssembler::Spill(uint32_t index, LiftoffRegister reg, in Spill() function
337 void LiftoffAssembler::Spill(uint32_t index, WasmValue value) { in Spill() function
|
| /dports/databases/postgresql13-pltcl/postgresql-13.5/src/backend/storage/lmgr/ |
| H A D | lmgr.c | 750 * The token is used to distinguish multiple insertions by the same
914 VirtualTransactionId *lockholders = lfirst(lc);
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.h | 394 unsigned NumSpilledSGPRs = 0;
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 393 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 393 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 388 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 393 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 393 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
|
| /dports/mail/thunderbird/thunderbird-91.8.0/third_party/rust/regalloc/src/ |
| H A D | snapshot.rs | 20 Spill { vreg: Option<VirtualReg> }, enumerator
|
| /dports/www/firefox/firefox-99.0/third_party/rust/regalloc/src/ |
| H A D | snapshot.rs | 20 Spill { vreg: Option<VirtualReg> }, enumerator
|
| H A D | checker.rs | 388 Spill { into: SpillSlot, from: RealReg }, enumerator
|
| /dports/lang/rust/rustc-1.58.1-src/vendor/regalloc/src/ |
| H A D | snapshot.rs | 20 Spill { vreg: Option<VirtualReg> }, enumerator
|
| /dports/www/firefox-esr/firefox-91.8.0/third_party/rust/regalloc/src/ |
| H A D | snapshot.rs | 20 Spill { vreg: Option<VirtualReg> }, enumerator
|
| /dports/lang/mono/mono-5.10.1.57/external/corefx/src/System.Linq.Expressions/tests/ |
| H A D | StackSpillerTests.cs | 2232 private static Expression Spill(Expression expression) in Spill() method in System.Linq.Expressions.Tests.StackSpillerTests
|
| /dports/sysutils/vector/vector-0.10.0/cargo-crates/regalloc-0.0.25/src/ |
| H A D | checker.rs | 280 Spill { into: SpillSlot, from: RealReg }, enumerator
|
| /dports/lang/spidermonkey78/firefox-78.9.0/third_party/rust/regalloc/src/ |
| H A D | checker.rs | 280 Spill { into: SpillSlot, from: RealReg }, enumerator
|
| /dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 745 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
910 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
|
| /dports/www/node10/node-v10.24.1/deps/v8/src/wasm/baseline/mips64/ |
| H A D | liftoff-assembler-mips64.h | 406 void LiftoffAssembler::Spill(uint32_t index, LiftoffRegister reg, in Spill() function
428 void LiftoffAssembler::Spill(uint32_t index, WasmValue value) { in Spill() function
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 791 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
892 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroFrame.cpp | 289 class Spill { class
295 Spill(Value *Def, llvm::User *U) : Def(Def), User(cast<Instruction>(U)) {} in Spill() function in __anon91faaeaf0511::Spill
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 791 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
892 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Transforms/Coroutines/ |
| H A D | CoroFrame.cpp | 289 class Spill { class
295 Spill(Value *Def, llvm::User *U) : Def(Def), User(cast<Instruction>(U)) {} in Spill() function in __anond32fa10c0511::Spill
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 791 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
892 SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroFrame.cpp | 289 class Spill { class
295 Spill(Value *Def, llvm::User *U) : Def(Def), User(cast<Instruction>(U)) {} in Spill() function in __anon595073370511::Spill
|