| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCompound.cpp | 81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
|
| H A D | HexagonMCDuplexInfo.cpp | 190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZPostRewrite.cpp | 111 Register Src1Reg = MBBI->getOperand(1).getReg(); in selectSELRMux() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 275 Register Src1Reg = MI->getOperand(2).getReg(); in ExpandFPMLxInstruction() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerLowering.cpp | 647 Register Src1Reg = MI.getOperand(1).getReg(); in matchDupLane() local
699 Register Src1Reg = MI.getOperand(1).getReg(); in applyDupLane() local
|
| H A D | AArch64InstructionSelector.cpp | 1668 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorSHL() local
1714 Register Src1Reg = I.getOperand(1).getReg(); in selectVectorAshrLshr() local
3672 Register Src1Reg = I.getOperand(1).getReg(); in selectMergeValues() local
4569 Register Src1Reg = I.getOperand(1).getReg(); in selectShuffleVector() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1201 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
1225 Register Src1Reg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
3328 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
3818 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1044 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
1939 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectDivRem() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 2633 unsigned Src1Reg = getRegForValue(Src1Val); in optimizeSelect() local
2756 unsigned Src1Reg = getRegForValue(SI->getTrueValue()); in selectSelect() local
4545 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectRem() local
4617 unsigned Src1Reg = getRegForValue(I->getOperand(1)); in selectMul() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 424 Register Src1Reg = I.getOperand(3).getReg(); in selectG_UADDO_USUBO_UADDE_USUBE() local
704 Register Src1Reg = I.getOperand(2).getReg(); in selectG_INSERT() local
916 Register Src1Reg = I.getOperand(3).getReg(); in selectG_INTRINSIC() local
2796 Register Src1Reg = MI.getOperand(2).getReg(); in selectG_SHUFFLE_VECTOR() local
|
| H A D | AMDGPURegisterBankInfo.cpp | 4011 Register Src1Reg = MI.getOperand(3).getReg(); in getInstrMapping() local
|
| H A D | AMDGPULegalizerInfo.cpp | 1945 Register Src1Reg = MI.getOperand(2).getReg(); in legalizeFrem() local
|
| H A D | SIInstrInfo.cpp | 2813 Register Src1Reg = Src1->getReg(); in FoldImmediate() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 6289 Register Src1Reg = MI.getOperand(2).getReg(); in lowerShuffleVector() local
|