Searched defs:Srl (Results 1 – 6 of 6) sorted by relevance
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 332 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
2165 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
|
| H A D | SIISelLowering.cpp | 10232 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 1854 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 447 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 5812 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local
|
| /netbsd/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 4219 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
5550 SDValue Srl = Not.getOperand(0); in combineShiftAnd1ToBitTest() local
|