1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2004 Free Software Foundation, Inc. 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 5 and Martin Simmons (@harleqn.co.uk). 6 More major hacks by Richard Earnshaw (rearnsha@arm.com) 7 Minor hacks by Nick Clifton (nickc@cygnus.com) 8 9 This file is part of GNU CC. 10 11 GNU CC is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 2, or (at your option) 14 any later version. 15 16 GNU CC is distributed in the hope that it will be useful, 17 but WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 GNU General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with GNU CC; see the file COPYING. If not, write to 23 the Free Software Foundation, 59 Temple Place - Suite 330, 24 Boston, MA 02111-1307, USA. */ 25 26 #ifndef GCC_ARM_H 27 #define GCC_ARM_H 28 29 /* Target CPU builtins. */ 30 #define TARGET_CPU_CPP_BUILTINS() \ 31 do \ 32 { \ 33 if (TARGET_ARM) \ 34 builtin_define ("__arm__"); \ 35 else \ 36 builtin_define ("__thumb__"); \ 37 \ 38 if (TARGET_BIG_END) \ 39 { \ 40 builtin_define ("__ARMEB__"); \ 41 if (TARGET_THUMB) \ 42 builtin_define ("__THUMBEB__"); \ 43 if (TARGET_LITTLE_WORDS) \ 44 builtin_define ("__ARMWEL__"); \ 45 } \ 46 else \ 47 { \ 48 builtin_define ("__ARMEL__"); \ 49 if (TARGET_THUMB) \ 50 builtin_define ("__THUMBEL__"); \ 51 } \ 52 \ 53 if (TARGET_APCS_32) \ 54 builtin_define ("__APCS_32__"); \ 55 else \ 56 builtin_define ("__APCS_26__"); \ 57 \ 58 if (TARGET_SOFT_FLOAT) \ 59 builtin_define ("__SOFTFP__"); \ 60 \ 61 /* FIXME: TARGET_HARD_FLOAT currently implies \ 62 FPA. */ \ 63 if (TARGET_VFP && !TARGET_HARD_FLOAT) \ 64 builtin_define ("__VFP_FP__"); \ 65 \ 66 /* Add a define for interworking. \ 67 Needed when building libgcc.a. */ \ 68 if (TARGET_INTERWORK) \ 69 builtin_define ("__THUMB_INTERWORK__"); \ 70 \ 71 builtin_assert ("cpu=arm"); \ 72 builtin_assert ("machine=arm"); \ 73 } while (0) 74 75 #define TARGET_CPU_arm2 0x0000 76 #define TARGET_CPU_arm250 0x0000 77 #define TARGET_CPU_arm3 0x0000 78 #define TARGET_CPU_arm6 0x0001 79 #define TARGET_CPU_arm600 0x0001 80 #define TARGET_CPU_arm610 0x0002 81 #define TARGET_CPU_arm7 0x0001 82 #define TARGET_CPU_arm7m 0x0004 83 #define TARGET_CPU_arm7dm 0x0004 84 #define TARGET_CPU_arm7dmi 0x0004 85 #define TARGET_CPU_arm700 0x0001 86 #define TARGET_CPU_arm710 0x0002 87 #define TARGET_CPU_arm7100 0x0002 88 #define TARGET_CPU_arm7500 0x0002 89 #define TARGET_CPU_arm7500fe 0x1001 90 #define TARGET_CPU_arm7tdmi 0x0008 91 #define TARGET_CPU_arm8 0x0010 92 #define TARGET_CPU_arm810 0x0020 93 #define TARGET_CPU_strongarm 0x0040 94 #define TARGET_CPU_strongarm110 0x0040 95 #define TARGET_CPU_strongarm1100 0x0040 96 #define TARGET_CPU_arm9 0x0080 97 #define TARGET_CPU_arm9tdmi 0x0080 98 #define TARGET_CPU_xscale 0x0100 99 /* Configure didn't specify. */ 100 #define TARGET_CPU_generic 0x8000 101 102 typedef enum arm_cond_code 103 { 104 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 105 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 106 } 107 arm_cc; 108 109 extern arm_cc arm_current_cc; 110 111 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 112 113 extern int arm_target_label; 114 extern int arm_ccfsm_state; 115 extern GTY(()) rtx arm_target_insn; 116 /* Run-time compilation parameters selecting different hardware subsets. */ 117 extern int target_flags; 118 /* The floating point instruction architecture, can be 2 or 3 */ 119 extern const char * target_fp_name; 120 /* Define the information needed to generate branch insns. This is 121 stored from the compare operation. */ 122 extern GTY(()) rtx arm_compare_op0; 123 extern GTY(()) rtx arm_compare_op1; 124 /* The label of the current constant pool. */ 125 extern rtx pool_vector_label; 126 /* Set to 1 when a return insn is output, this means that the epilogue 127 is not needed. */ 128 extern int return_used_this_function; 129 /* Used to produce AOF syntax assembler. */ 130 extern GTY(()) rtx aof_pic_label; 131 132 /* Just in case configure has failed to define anything. */ 133 #ifndef TARGET_CPU_DEFAULT 134 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 135 #endif 136 137 /* If the configuration file doesn't specify the cpu, the subtarget may 138 override it. If it doesn't, then default to an ARM6. */ 139 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic 140 #undef TARGET_CPU_DEFAULT 141 142 #ifdef SUBTARGET_CPU_DEFAULT 143 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT 144 #else 145 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6 146 #endif 147 #endif 148 149 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2 150 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__" 151 #else 152 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe 153 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__" 154 #else 155 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m 156 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__" 157 #else 158 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi 159 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__" 160 #else 161 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100 162 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__" 163 #else 164 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale 165 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" 166 #else 167 Unrecognized value in TARGET_CPU_DEFAULT. 168 #endif 169 #endif 170 #endif 171 #endif 172 #endif 173 #endif 174 175 #undef CPP_SPEC 176 #define CPP_SPEC "%(cpp_cpu_arch) %(subtarget_cpp_spec) \ 177 %{mapcs-32:%{mapcs-26: \ 178 %e-mapcs-26 and -mapcs-32 may not be used together}} \ 179 %{msoft-float:%{mhard-float: \ 180 %e-msoft-float and -mhard_float may not be used together}} \ 181 %{mbig-endian:%{mlittle-endian: \ 182 %e-mbig-endian and -mlittle-endian may not be used together}}" 183 184 /* Set the architecture define -- if -march= is set, then it overrides 185 the -mcpu= setting. */ 186 #define CPP_CPU_ARCH_SPEC "\ 187 %{march=arm2:-D__ARM_ARCH_2__} \ 188 %{march=arm250:-D__ARM_ARCH_2__} \ 189 %{march=arm3:-D__ARM_ARCH_2__} \ 190 %{march=arm6:-D__ARM_ARCH_3__} \ 191 %{march=arm600:-D__ARM_ARCH_3__} \ 192 %{march=arm610:-D__ARM_ARCH_3__} \ 193 %{march=arm7:-D__ARM_ARCH_3__} \ 194 %{march=arm700:-D__ARM_ARCH_3__} \ 195 %{march=arm710:-D__ARM_ARCH_3__} \ 196 %{march=arm720:-D__ARM_ARCH_3__} \ 197 %{march=arm7100:-D__ARM_ARCH_3__} \ 198 %{march=arm7500:-D__ARM_ARCH_3__} \ 199 %{march=arm7500fe:-D__ARM_ARCH_3__} \ 200 %{march=arm7m:-D__ARM_ARCH_3M__} \ 201 %{march=arm7dm:-D__ARM_ARCH_3M__} \ 202 %{march=arm7dmi:-D__ARM_ARCH_3M__} \ 203 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \ 204 %{march=arm8:-D__ARM_ARCH_4__} \ 205 %{march=arm810:-D__ARM_ARCH_4__} \ 206 %{march=arm9:-D__ARM_ARCH_4T__} \ 207 %{march=arm920:-D__ARM_ARCH_4__} \ 208 %{march=arm920t:-D__ARM_ARCH_4T__} \ 209 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \ 210 %{march=strongarm:-D__ARM_ARCH_4__} \ 211 %{march=strongarm110:-D__ARM_ARCH_4__} \ 212 %{march=strongarm1100:-D__ARM_ARCH_4__} \ 213 %{march=xscale:-D__ARM_ARCH_5TE__} \ 214 %{march=xscale:-D__XSCALE__} \ 215 %{march=armv2:-D__ARM_ARCH_2__} \ 216 %{march=armv2a:-D__ARM_ARCH_2__} \ 217 %{march=armv3:-D__ARM_ARCH_3__} \ 218 %{march=armv3m:-D__ARM_ARCH_3M__} \ 219 %{march=armv4:-D__ARM_ARCH_4__} \ 220 %{march=armv4t:-D__ARM_ARCH_4T__} \ 221 %{march=armv5:-D__ARM_ARCH_5__} \ 222 %{march=armv5t:-D__ARM_ARCH_5T__} \ 223 %{march=armv5e:-D__ARM_ARCH_5E__} \ 224 %{march=armv5te:-D__ARM_ARCH_5TE__} \ 225 %{!march=*: \ 226 %{mcpu=arm2:-D__ARM_ARCH_2__} \ 227 %{mcpu=arm250:-D__ARM_ARCH_2__} \ 228 %{mcpu=arm3:-D__ARM_ARCH_2__} \ 229 %{mcpu=arm6:-D__ARM_ARCH_3__} \ 230 %{mcpu=arm600:-D__ARM_ARCH_3__} \ 231 %{mcpu=arm610:-D__ARM_ARCH_3__} \ 232 %{mcpu=arm7:-D__ARM_ARCH_3__} \ 233 %{mcpu=arm700:-D__ARM_ARCH_3__} \ 234 %{mcpu=arm710:-D__ARM_ARCH_3__} \ 235 %{mcpu=arm720:-D__ARM_ARCH_3__} \ 236 %{mcpu=arm7100:-D__ARM_ARCH_3__} \ 237 %{mcpu=arm7500:-D__ARM_ARCH_3__} \ 238 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \ 239 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \ 240 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \ 241 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \ 242 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \ 243 %{mcpu=arm8:-D__ARM_ARCH_4__} \ 244 %{mcpu=arm810:-D__ARM_ARCH_4__} \ 245 %{mcpu=arm9:-D__ARM_ARCH_4T__} \ 246 %{mcpu=arm920:-D__ARM_ARCH_4__} \ 247 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \ 248 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \ 249 %{mcpu=strongarm:-D__ARM_ARCH_4__} \ 250 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \ 251 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ 252 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ 253 %{mcpu=xscale:-D__XSCALE__} \ 254 %{!mcpu*:%(cpp_cpu_arch_default)}} \ 255 " 256 257 #ifndef CC1_SPEC 258 #define CC1_SPEC "" 259 #endif 260 261 /* This macro defines names of additional specifications to put in the specs 262 that can be used in various specifications like CC1_SPEC. Its definition 263 is an initializer with a subgrouping for each command option. 264 265 Each subgrouping contains a string constant, that defines the 266 specification name, and a string constant that used by the GNU CC driver 267 program. 268 269 Do not define this macro if it does not need to do anything. */ 270 #define EXTRA_SPECS \ 271 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \ 272 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \ 273 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 274 SUBTARGET_EXTRA_SPECS 275 276 #ifndef SUBTARGET_EXTRA_SPECS 277 #define SUBTARGET_EXTRA_SPECS 278 #endif 279 280 #ifndef SUBTARGET_CPP_SPEC 281 #define SUBTARGET_CPP_SPEC "" 282 #endif 283 284 /* Run-time Target Specification. */ 285 #ifndef TARGET_VERSION 286 #define TARGET_VERSION fputs (" (ARM/generic)", stderr); 287 #endif 288 289 /* Nonzero if the function prologue (and epilogue) should obey 290 the ARM Procedure Call Standard. */ 291 #define ARM_FLAG_APCS_FRAME (1 << 0) 292 293 /* Nonzero if the function prologue should output the function name to enable 294 the post mortem debugger to print a backtrace (very useful on RISCOS, 295 unused on RISCiX). Specifying this flag also enables 296 -fno-omit-frame-pointer. 297 XXX Must still be implemented in the prologue. */ 298 #define ARM_FLAG_POKE (1 << 1) 299 300 /* Nonzero if floating point instructions are emulated by the FPE, in which 301 case instruction scheduling becomes very uninteresting. */ 302 #define ARM_FLAG_FPE (1 << 2) 303 304 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit 305 that assume restoration of the condition flags when returning from a 306 branch and link (ie a function). */ 307 #define ARM_FLAG_APCS_32 (1 << 3) 308 309 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */ 310 311 /* Nonzero if stack checking should be performed on entry to each function 312 which allocates temporary variables on the stack. */ 313 #define ARM_FLAG_APCS_STACK (1 << 4) 314 315 /* Nonzero if floating point parameters should be passed to functions in 316 floating point registers. */ 317 #define ARM_FLAG_APCS_FLOAT (1 << 5) 318 319 /* Nonzero if re-entrant, position independent code should be generated. 320 This is equivalent to -fpic. */ 321 #define ARM_FLAG_APCS_REENT (1 << 6) 322 323 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must 324 be loaded using either LDRH or LDRB instructions. */ 325 #define ARM_FLAG_MMU_TRAPS (1 << 7) 326 327 /* Nonzero if all floating point instructions are missing (and there is no 328 emulator either). Generate function calls for all ops in this case. */ 329 #define ARM_FLAG_SOFT_FLOAT (1 << 8) 330 331 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */ 332 #define ARM_FLAG_BIG_END (1 << 9) 333 334 /* Nonzero if we should compile for Thumb interworking. */ 335 #define ARM_FLAG_INTERWORK (1 << 10) 336 337 /* Nonzero if we should have little-endian words even when compiling for 338 big-endian (for backwards compatibility with older versions of GCC). */ 339 #define ARM_FLAG_LITTLE_WORDS (1 << 11) 340 341 /* Nonzero if we need to protect the prolog from scheduling */ 342 #define ARM_FLAG_NO_SCHED_PRO (1 << 12) 343 344 /* Nonzero if a call to abort should be generated if a noreturn 345 function tries to return. */ 346 #define ARM_FLAG_ABORT_NORETURN (1 << 13) 347 348 /* Nonzero if function prologues should not load the PIC register. */ 349 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) 350 351 /* Nonzero if all call instructions should be indirect. */ 352 #define ARM_FLAG_LONG_CALLS (1 << 15) 353 354 /* Nonzero means that the target ISA is the THUMB, not the ARM. */ 355 #define ARM_FLAG_THUMB (1 << 16) 356 357 /* Set if a TPCS style stack frame should be generated, for non-leaf 358 functions, even if they do not need one. */ 359 #define THUMB_FLAG_BACKTRACE (1 << 17) 360 361 /* Set if a TPCS style stack frame should be generated, for leaf 362 functions, even if they do not need one. */ 363 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18) 364 365 /* Set if externally visible functions should assume that they 366 might be called in ARM mode, from a non-thumb aware code. */ 367 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19) 368 369 /* Set if calls via function pointers should assume that their 370 destination is non-Thumb aware. */ 371 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20) 372 373 /* Nonzero means target uses VFP FP. */ 374 #define ARM_FLAG_VFP (1 << 21) 375 376 /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */ 377 #define ARM_FLAG_ATPCS (1 << 22) 378 379 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) 380 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) 381 #define TARGET_FPE (target_flags & ARM_FLAG_FPE) 382 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32) 383 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK) 384 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT) 385 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT) 386 #define TARGET_ATPCS (target_flags & ARM_FLAG_ATPCS) 387 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) 388 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) 389 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) 390 #define TARGET_VFP (target_flags & ARM_FLAG_VFP) 391 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) 392 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) 393 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS) 394 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO) 395 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN) 396 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE) 397 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS) 398 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB) 399 #define TARGET_ARM (! TARGET_THUMB) 400 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 401 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING) 402 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING) 403 #define TARGET_BACKTRACE (leaf_function_p () \ 404 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ 405 : (target_flags & THUMB_FLAG_BACKTRACE)) 406 407 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ 408 #ifndef SUBTARGET_SWITCHES 409 #define SUBTARGET_SWITCHES 410 #endif 411 412 #define TARGET_SWITCHES \ 413 { \ 414 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \ 415 {"apcs-frame", ARM_FLAG_APCS_FRAME, \ 416 N_("Generate APCS conformant stack frames") }, \ 417 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \ 418 {"poke-function-name", ARM_FLAG_POKE, \ 419 N_("Store function names in object code") }, \ 420 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \ 421 {"fpe", ARM_FLAG_FPE, "" }, \ 422 {"apcs-32", ARM_FLAG_APCS_32, \ 423 N_("Use the 32-bit version of the APCS") }, \ 424 {"apcs-26", -ARM_FLAG_APCS_32, \ 425 N_("Use the 26-bit version of the APCS") }, \ 426 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ 427 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ 428 {"apcs-float", ARM_FLAG_APCS_FLOAT, \ 429 N_("Pass FP arguments in FP registers") }, \ 430 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \ 431 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \ 432 N_("Generate re-entrant, PIC code") }, \ 433 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \ 434 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ 435 N_("The MMU will trap on unaligned accesses") }, \ 436 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ 437 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ 438 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ 439 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ 440 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ 441 {"soft-float", ARM_FLAG_SOFT_FLOAT, \ 442 N_("Use library calls to perform FP operations") }, \ 443 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ 444 N_("Use hardware floating point instructions") }, \ 445 {"big-endian", ARM_FLAG_BIG_END, \ 446 N_("Assume target CPU is configured as big endian") }, \ 447 {"little-endian", -ARM_FLAG_BIG_END, \ 448 N_("Assume target CPU is configured as little endian") }, \ 449 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \ 450 N_("Assume big endian bytes, little endian words") }, \ 451 {"thumb-interwork", ARM_FLAG_INTERWORK, \ 452 N_("Support calls between Thumb and ARM instruction sets") }, \ 453 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \ 454 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \ 455 N_("Generate a call to abort if a noreturn function returns")}, \ 456 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \ 457 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \ 458 N_("Do not move instructions into a function's prologue") }, \ 459 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \ 460 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \ 461 N_("Do not load the PIC register in function prologues") }, \ 462 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \ 463 {"long-calls", ARM_FLAG_LONG_CALLS, \ 464 N_("Generate call insns as indirect calls, if necessary") }, \ 465 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \ 466 {"thumb", ARM_FLAG_THUMB, \ 467 N_("Compile for the Thumb not the ARM") }, \ 468 {"no-thumb", -ARM_FLAG_THUMB, "" }, \ 469 {"arm", -ARM_FLAG_THUMB, "" }, \ 470 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \ 471 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \ 472 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \ 473 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \ 474 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \ 475 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \ 476 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ 477 N_("Thumb: Assume non-static functions may be called from ARM code") }, \ 478 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \ 479 "" }, \ 480 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ 481 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ 482 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ 483 "" }, \ 484 SUBTARGET_SWITCHES \ 485 {"", TARGET_DEFAULT, "" } \ 486 } 487 488 #define TARGET_OPTIONS \ 489 { \ 490 {"cpu=", & arm_select[0].string, \ 491 N_("Specify the name of the target CPU") }, \ 492 {"arch=", & arm_select[1].string, \ 493 N_("Specify the name of the target architecture") }, \ 494 {"tune=", & arm_select[2].string, "" }, \ 495 {"fpe=", & target_fp_name, "" }, \ 496 {"fp=", & target_fp_name, \ 497 N_("Specify the version of the floating point emulator") }, \ 498 {"structure-size-boundary=", & structure_size_string, \ 499 N_("Specify the minimum bit alignment of structures") }, \ 500 {"pic-register=", & arm_pic_register_string, \ 501 N_("Specify the register to be used for PIC addressing") } \ 502 } 503 504 struct arm_cpu_select 505 { 506 const char * string; 507 const char * name; 508 const struct processors * processors; 509 }; 510 511 /* This is a magic array. If the user specifies a command line switch 512 which matches one of the entries in TARGET_OPTIONS then the corresponding 513 string pointer will be set to the value specified by the user. */ 514 extern struct arm_cpu_select arm_select[]; 515 516 enum prog_mode_type 517 { 518 prog_mode26, 519 prog_mode32 520 }; 521 522 /* Recast the program mode class to be the prog_mode attribute */ 523 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) 524 525 extern enum prog_mode_type arm_prgmode; 526 527 /* What sort of floating point unit do we have? Hardware or software. 528 If software, is it issue 2 or issue 3? */ 529 enum floating_point_type 530 { 531 FP_HARD, 532 FP_SOFT2, 533 FP_SOFT3 534 }; 535 536 /* Recast the floating point class to be the floating point attribute. */ 537 #define arm_fpu_attr ((enum attr_fpu) arm_fpu) 538 539 /* What type of floating point to tune for */ 540 extern enum floating_point_type arm_fpu; 541 542 /* What type of floating point instructions are available */ 543 extern enum floating_point_type arm_fpu_arch; 544 545 /* Default floating point architecture. Override in sub-target if 546 necessary. */ 547 #ifndef FP_DEFAULT 548 #define FP_DEFAULT FP_SOFT2 549 #endif 550 551 /* Nonzero if the processor has a fast multiply insn, and one that does 552 a 64-bit multiply of two 32-bit values. */ 553 extern int arm_fast_multiply; 554 555 /* Nonzero if this chip supports the ARM Architecture 4 extensions */ 556 extern int arm_arch4; 557 558 /* Nonzero if this chip supports the ARM Architecture 5 extensions */ 559 extern int arm_arch5; 560 561 /* Nonzero if this chip supports the ARM Architecture 5E extensions */ 562 extern int arm_arch5e; 563 564 /* Nonzero if this chip can benefit from load scheduling. */ 565 extern int arm_ld_sched; 566 567 /* Nonzero if generating thumb code. */ 568 extern int thumb_code; 569 570 /* Nonzero if this chip is a StrongARM. */ 571 extern int arm_is_strong; 572 573 /* Nonzero if this chip is an XScale. */ 574 extern int arm_arch_xscale; 575 576 /* Nonzero if tuning for XScale */ 577 extern int arm_tune_xscale; 578 579 /* Nonzero if this chip is an ARM6 or an ARM7. */ 580 extern int arm_is_6_or_7; 581 582 #ifndef TARGET_DEFAULT 583 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) 584 #endif 585 586 /* The frame pointer register used in gcc has nothing to do with debugging; 587 that is controlled by the APCS-FRAME option. */ 588 #define CAN_DEBUG_WITHOUT_FP 589 590 #undef TARGET_MEM_FUNCTIONS 591 #define TARGET_MEM_FUNCTIONS 1 592 593 #define OVERRIDE_OPTIONS arm_override_options () 594 595 /* Nonzero if PIC code requires explicit qualifiers to generate 596 PLT and GOT relocs rather than the assembler doing so implicitly. 597 Subtargets can override these if required. */ 598 #ifndef NEED_GOT_RELOC 599 #define NEED_GOT_RELOC 0 600 #endif 601 #ifndef NEED_PLT_RELOC 602 #define NEED_PLT_RELOC 0 603 #endif 604 605 /* Nonzero if we need to refer to the GOT with a PC-relative 606 offset. In other words, generate 607 608 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 609 610 rather than 611 612 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 613 614 The default is true, which matches NetBSD. Subtargets can 615 override this if required. */ 616 #ifndef GOT_PCREL 617 #define GOT_PCREL 1 618 #endif 619 620 /* Target machine storage Layout. */ 621 622 623 /* Define this macro if it is advisable to hold scalars in registers 624 in a wider mode than that declared by the program. In such cases, 625 the value is constrained to be within the bounds of the declared 626 type, but kept valid in the wider mode. The signedness of the 627 extension may differ from that of the type. */ 628 629 /* It is far faster to zero extend chars than to sign extend them */ 630 631 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 632 if (GET_MODE_CLASS (MODE) == MODE_INT \ 633 && GET_MODE_SIZE (MODE) < 4) \ 634 { \ 635 if (MODE == QImode) \ 636 UNSIGNEDP = 1; \ 637 else if (MODE == HImode) \ 638 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \ 639 (MODE) = SImode; \ 640 } 641 642 /* Define this macro if the promotion described by `PROMOTE_MODE' 643 should also be done for outgoing function arguments. */ 644 /* This is required to ensure that push insns always push a word. */ 645 #define PROMOTE_FUNCTION_ARGS 646 647 /* For the ARM: 648 I think I have added all the code to make this work. Unfortunately, 649 early releases of the floating point emulation code on RISCiX used a 650 different format for extended precision numbers. On my RISCiX box there 651 is a bug somewhere which causes the machine to lock up when running enquire 652 with long doubles. There is the additional aspect that Norcroft C 653 treats long doubles as doubles and we ought to remain compatible. 654 Perhaps someone with an FPA coprocessor and not running RISCiX would like 655 to try this someday. */ 656 /* #define LONG_DOUBLE_TYPE_SIZE 96 */ 657 658 /* Disable XFmode patterns in md file */ 659 #define ENABLE_XF_PATTERNS 0 660 661 /* Define this if most significant bit is lowest numbered 662 in instructions that operate on numbered bit-fields. */ 663 #define BITS_BIG_ENDIAN 0 664 665 /* Define this if most significant byte of a word is the lowest numbered. 666 Most ARM processors are run in little endian mode, so that is the default. 667 If you want to have it run-time selectable, change the definition in a 668 cover file to be TARGET_BIG_ENDIAN. */ 669 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 670 671 /* Define this if most significant word of a multiword number is the lowest 672 numbered. 673 This is always false, even when in big-endian mode. */ 674 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 675 676 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 677 on processor pre-defineds when compiling libgcc2.c. */ 678 #if defined(__ARMEB__) && !defined(__ARMWEL__) 679 #define LIBGCC2_WORDS_BIG_ENDIAN 1 680 #else 681 #define LIBGCC2_WORDS_BIG_ENDIAN 0 682 #endif 683 684 /* Define this if most significant word of doubles is the lowest numbered. 685 The rules are different based on whether or not we use FPA-format or 686 VFP-format doubles. */ 687 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 688 689 #define UNITS_PER_WORD 4 690 691 #define PARM_BOUNDARY 32 692 693 #define STACK_BOUNDARY 32 694 695 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32) 696 697 #define FUNCTION_BOUNDARY 32 698 699 /* The lowest bit is used to indicate Thumb-mode functions, so the 700 vbit must go into the delta field of pointers to member 701 functions. */ 702 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 703 704 #define EMPTY_FIELD_BOUNDARY 32 705 706 #define BIGGEST_ALIGNMENT 32 707 708 /* Make strings word-aligned so strcpy from constants will be faster. */ 709 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_arch_xscale ? 1 : 2) 710 711 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 712 ((TREE_CODE (EXP) == STRING_CST \ 713 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 714 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 715 716 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 717 value set in previous versions of this toolchain was 8, which produces more 718 compact structures. The command line option -mstructure_size_boundary=<n> 719 can be used to change this value. For compatibility with the ARM SDK 720 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 721 0020D) page 2-20 says "Structures are aligned on word boundaries". */ 722 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 723 extern int arm_structure_size_boundary; 724 725 /* This is the value used to initialize arm_structure_size_boundary. If a 726 particular arm target wants to change the default value it should change 727 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h 728 for an example of this. */ 729 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 730 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 731 #endif 732 733 /* Used when parsing command line option -mstructure_size_boundary. */ 734 extern const char * structure_size_string; 735 736 /* Nonzero if move instructions will actually fail to work 737 when given unaligned data. */ 738 #define STRICT_ALIGNMENT 1 739 740 /* Standard register usage. */ 741 742 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 743 (S - saved over call). 744 745 r0 * argument word/integer result 746 r1-r3 argument word 747 748 r4-r8 S register variable 749 r9 S (rfp) register variable (real frame pointer) 750 751 r10 F S (sl) stack limit (used by -mapcs-stack-check) 752 r11 F S (fp) argument pointer 753 r12 (ip) temp workspace 754 r13 F S (sp) lower end of current stack frame 755 r14 (lr) link address/workspace 756 r15 F (pc) program counter 757 758 f0 floating point result 759 f1-f3 floating point scratch 760 761 f4-f7 S floating point variable 762 763 cc This is NOT a real register, but is used internally 764 to represent things that use or set the condition 765 codes. 766 sfp This isn't either. It is used during rtl generation 767 since the offset between the frame pointer and the 768 auto's isn't known until after register allocation. 769 afp Nor this, we only need this because of non-local 770 goto. Without it fp appears to be used and the 771 elimination code won't get rid of sfp. It tracks 772 fp exactly at all times. 773 774 *: See CONDITIONAL_REGISTER_USAGE */ 775 776 /* The stack backtrace structure is as follows: 777 fp points to here: | save code pointer | [fp] 778 | return link value | [fp, #-4] 779 | return sp value | [fp, #-8] 780 | return fp value | [fp, #-12] 781 [| saved r10 value |] 782 [| saved r9 value |] 783 [| saved r8 value |] 784 [| saved r7 value |] 785 [| saved r6 value |] 786 [| saved r5 value |] 787 [| saved r4 value |] 788 [| saved r3 value |] 789 [| saved r2 value |] 790 [| saved r1 value |] 791 [| saved r0 value |] 792 [| saved f7 value |] three words 793 [| saved f6 value |] three words 794 [| saved f5 value |] three words 795 [| saved f4 value |] three words 796 r0-r3 are not normally saved in a C function. */ 797 798 /* 1 for registers that have pervasive standard uses 799 and are not available for the register allocator. */ 800 #define FIXED_REGISTERS \ 801 { \ 802 0,0,0,0,0,0,0,0, \ 803 0,0,0,0,0,1,0,1, \ 804 0,0,0,0,0,0,0,0, \ 805 1,1,1 \ 806 } 807 808 /* 1 for registers not available across function calls. 809 These must include the FIXED_REGISTERS and also any 810 registers that can be used without being saved. 811 The latter must include the registers where values are returned 812 and the register where structure-value addresses are passed. 813 Aside from that, you can include as many other registers as you like. 814 The CC is not preserved over function calls on the ARM 6, so it is 815 easier to assume this for all. SFP is preserved, since FP is. */ 816 #define CALL_USED_REGISTERS \ 817 { \ 818 1,1,1,1,0,0,0,0, \ 819 0,0,0,0,1,1,1,1, \ 820 1,1,1,1,0,0,0,0, \ 821 1,1,1 \ 822 } 823 824 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 825 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 826 #endif 827 828 #define CONDITIONAL_REGISTER_USAGE \ 829 { \ 830 int regno; \ 831 \ 832 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \ 833 { \ 834 for (regno = FIRST_ARM_FP_REGNUM; \ 835 regno <= LAST_ARM_FP_REGNUM; ++regno) \ 836 fixed_regs[regno] = call_used_regs[regno] = 1; \ 837 } \ 838 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 839 { \ 840 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 841 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 842 } \ 843 else if (TARGET_APCS_STACK) \ 844 { \ 845 fixed_regs[10] = 1; \ 846 call_used_regs[10] = 1; \ 847 } \ 848 if (TARGET_APCS_FRAME) \ 849 { \ 850 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 851 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 852 } \ 853 SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 854 } 855 856 /* These are a couple of extensions to the formats accecpted 857 by asm_fprintf: 858 %@ prints out ASM_COMMENT_START 859 %r prints out REGISTER_PREFIX reg_names[arg] */ 860 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 861 case '@': \ 862 fputs (ASM_COMMENT_START, FILE); \ 863 break; \ 864 \ 865 case 'r': \ 866 fputs (REGISTER_PREFIX, FILE); \ 867 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 868 break; 869 870 /* Round X up to the nearest word. */ 871 #define ROUND_UP(X) (((X) + 3) & ~3) 872 873 /* Convert fron bytes to ints. */ 874 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 875 876 /* The number of (integer) registers required to hold a quantity of type MODE. */ 877 #define ARM_NUM_REGS(MODE) \ 878 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 879 880 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 881 #define ARM_NUM_REGS2(MODE, TYPE) \ 882 ARM_NUM_INTS ((MODE) == BLKmode ? \ 883 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 884 885 /* The number of (integer) argument register available. */ 886 #define NUM_ARG_REGS 4 887 888 /* Return the regiser number of the N'th (integer) argument. */ 889 #define ARG_REGISTER(N) (N - 1) 890 891 #if 0 /* FIXME: The ARM backend has special code to handle structure 892 returns, and will reserve its own hidden first argument. So 893 if this macro is enabled a *second* hidden argument will be 894 reserved, which will break binary compatibility with old 895 toolchains and also thunk handling. One day this should be 896 fixed. */ 897 /* RTX for structure returns. NULL means use a hidden first argument. */ 898 #define STRUCT_VALUE 0 899 #else 900 /* Register in which address to store a structure value 901 is passed to a function. */ 902 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1) 903 #endif 904 905 /* Specify the registers used for certain standard purposes. 906 The values of these macros are register numbers. */ 907 908 /* The number of the last argument register. */ 909 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 910 911 /* The number of the last "lo" register (thumb). */ 912 #define LAST_LO_REGNUM 7 913 914 /* The register that holds the return address in exception handlers. */ 915 #define EXCEPTION_LR_REGNUM 2 916 917 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 918 as an invisible last argument (possible since varargs don't exist in 919 Pascal), so the following is not true. */ 920 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9) 921 922 /* Define this to be where the real frame pointer is if it is not possible to 923 work out the offset between the frame pointer and the automatic variables 924 until after register allocation has taken place. FRAME_POINTER_REGNUM 925 should point to a special register that we will make sure is eliminated. 926 927 For the Thumb we have another problem. The TPCS defines the frame pointer 928 as r11, and GCC belives that it is always possible to use the frame pointer 929 as base register for addressing purposes. (See comments in 930 find_reloads_address()). But - the Thumb does not allow high registers, 931 including r11, to be used as base address registers. Hence our problem. 932 933 The solution used here, and in the old thumb port is to use r7 instead of 934 r11 as the hard frame pointer and to have special code to generate 935 backtrace structures on the stack (if required to do so via a command line 936 option) using r11. This is the only 'user visable' use of r11 as a frame 937 pointer. */ 938 #define ARM_HARD_FRAME_POINTER_REGNUM 11 939 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 940 941 #define HARD_FRAME_POINTER_REGNUM \ 942 (TARGET_ARM \ 943 ? ARM_HARD_FRAME_POINTER_REGNUM \ 944 : THUMB_HARD_FRAME_POINTER_REGNUM) 945 946 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 947 948 /* Register to use for pushing function arguments. */ 949 #define STACK_POINTER_REGNUM SP_REGNUM 950 951 /* ARM floating pointer registers. */ 952 #define FIRST_ARM_FP_REGNUM 16 953 #define LAST_ARM_FP_REGNUM 23 954 955 /* Base register for access to local variables of the function. */ 956 #define FRAME_POINTER_REGNUM 25 957 958 /* Base register for access to arguments of the function. */ 959 #define ARG_POINTER_REGNUM 26 960 961 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ 962 #define FIRST_PSEUDO_REGISTER 27 963 964 /* Value should be nonzero if functions must have frame pointers. 965 Zero means the frame pointer need not be set up (and parms may be accessed 966 via the stack pointer) in functions that seem suitable. 967 If we have to have a frame pointer we might as well make use of it. 968 APCS says that the frame pointer does not need to be pushed in leaf 969 functions, or simple tail call functions. */ 970 #define FRAME_POINTER_REQUIRED \ 971 (current_function_has_nonlocal_label \ 972 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ())) 973 974 /* Return number of consecutive hard regs needed starting at reg REGNO 975 to hold something of mode MODE. 976 This is ordinarily the length in words of a value of mode MODE 977 but can be less for certain modes in special long registers. 978 979 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP 980 mode. */ 981 #define HARD_REGNO_NREGS(REGNO, MODE) \ 982 ((TARGET_ARM \ 983 && REGNO >= FIRST_ARM_FP_REGNUM \ 984 && REGNO != FRAME_POINTER_REGNUM \ 985 && REGNO != ARG_POINTER_REGNUM) \ 986 ? 1 : ARM_NUM_REGS (MODE)) 987 988 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 989 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 990 arm_hard_regno_mode_ok ((REGNO), (MODE)) 991 992 /* Value is 1 if it is a good idea to tie two pseudo registers 993 when one has mode MODE1 and one has mode MODE2. 994 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 995 for any hard reg, then this must be 0 for correct output. */ 996 #define MODES_TIEABLE_P(MODE1, MODE2) \ 997 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 998 999 /* The order in which register should be allocated. It is good to use ip 1000 since no saving is required (though calls clobber it) and it never contains 1001 function parameters. It is quite good to use lr since other calls may 1002 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1003 least likely to contain a function parameter; in addition results are 1004 returned in r0. */ 1005 #define REG_ALLOC_ORDER \ 1006 { \ 1007 3, 2, 1, 0, 12, 14, 4, 5, \ 1008 6, 7, 8, 10, 9, 11, 13, 15, \ 1009 16, 17, 18, 19, 20, 21, 22, 23, \ 1010 24, 25, 26 \ 1011 } 1012 1013 /* Interrupt functions can only use registers that have already been 1014 saved by the prologue, even if they would normally be 1015 call-clobbered. */ 1016 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1017 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1018 regs_ever_live[DST]) 1019 1020 /* Register and constant classes. */ 1021 1022 /* Register classes: used to be simple, just all ARM regs or all FPU regs 1023 Now that the Thumb is involved it has become more complicated. */ 1024 enum reg_class 1025 { 1026 NO_REGS, 1027 FPU_REGS, 1028 LO_REGS, 1029 STACK_REG, 1030 BASE_REGS, 1031 HI_REGS, 1032 CC_REG, 1033 GENERAL_REGS, 1034 ALL_REGS, 1035 LIM_REG_CLASSES 1036 }; 1037 1038 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1039 1040 /* Give names of register classes as strings for dump file. */ 1041 #define REG_CLASS_NAMES \ 1042 { \ 1043 "NO_REGS", \ 1044 "FPU_REGS", \ 1045 "LO_REGS", \ 1046 "STACK_REG", \ 1047 "BASE_REGS", \ 1048 "HI_REGS", \ 1049 "CC_REG", \ 1050 "GENERAL_REGS", \ 1051 "ALL_REGS", \ 1052 } 1053 1054 /* Define which registers fit in which classes. 1055 This is an initializer for a vector of HARD_REG_SET 1056 of length N_REG_CLASSES. */ 1057 #define REG_CLASS_CONTENTS \ 1058 { \ 1059 { 0x0000000 }, /* NO_REGS */ \ 1060 { 0x0FF0000 }, /* FPU_REGS */ \ 1061 { 0x00000FF }, /* LO_REGS */ \ 1062 { 0x0002000 }, /* STACK_REG */ \ 1063 { 0x00020FF }, /* BASE_REGS */ \ 1064 { 0x000FF00 }, /* HI_REGS */ \ 1065 { 0x1000000 }, /* CC_REG */ \ 1066 { 0x200FFFF }, /* GENERAL_REGS */ \ 1067 { 0x2FFFFFF } /* ALL_REGS */ \ 1068 } 1069 1070 /* The same information, inverted: 1071 Return the class number of the smallest class containing 1072 reg number REGNO. This could be a conditional expression 1073 or could index an array. */ 1074 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1075 1076 /* The class value for index registers, and the one for base regs. */ 1077 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) 1078 #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) 1079 1080 /* For the Thumb the high registers cannot be used as base registers 1081 when addressing quanitities in QI or HI mode; if we don't know the 1082 mode, then we must be conservative. After reload we must also be 1083 conservative, since we can't support SP+reg addressing, and we 1084 can't fix up any bad substitutions. */ 1085 #define MODE_BASE_REG_CLASS(MODE) \ 1086 (TARGET_ARM ? GENERAL_REGS : \ 1087 (((MODE) == SImode && !reload_completed) ? BASE_REGS : LO_REGS)) 1088 1089 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1090 registers explicitly used in the rtl to be used as spill registers 1091 but prevents the compiler from extending the lifetime of these 1092 registers. */ 1093 #define SMALL_REGISTER_CLASSES TARGET_THUMB 1094 1095 /* Get reg_class from a letter such as appears in the machine description. 1096 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the 1097 ARM, but several more letters for the Thumb. */ 1098 #define REG_CLASS_FROM_LETTER(C) \ 1099 ( (C) == 'f' ? FPU_REGS \ 1100 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ 1101 : TARGET_ARM ? NO_REGS \ 1102 : (C) == 'h' ? HI_REGS \ 1103 : (C) == 'b' ? BASE_REGS \ 1104 : (C) == 'k' ? STACK_REG \ 1105 : (C) == 'c' ? CC_REG \ 1106 : NO_REGS) 1107 1108 /* The letters I, J, K, L and M in a register constraint string 1109 can be used to stand for particular ranges of immediate operands. 1110 This macro defines what the ranges are. 1111 C is the letter, and VALUE is a constant value. 1112 Return 1 if VALUE is in the range specified by C. 1113 I: immediate arithmetic operand (i.e. 8 bits shifted as required). 1114 J: valid indexing constants. 1115 K: ~value ok in rhs argument of data operand. 1116 L: -value ok in rhs argument of data operand. 1117 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */ 1118 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \ 1119 ((C) == 'I' ? const_ok_for_arm (VALUE) : \ 1120 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \ 1121 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \ 1122 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \ 1123 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \ 1124 || (((VALUE) & ((VALUE) - 1)) == 0)) \ 1125 : 0) 1126 1127 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \ 1128 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \ 1129 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \ 1130 (C) == 'K' ? thumb_shiftable_const (VAL) : \ 1131 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \ 1132 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \ 1133 && ((VAL) & 3) == 0) : \ 1134 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \ 1135 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \ 1136 : 0) 1137 1138 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1139 (TARGET_ARM ? \ 1140 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) 1141 1142 /* Constant letter 'G' for the FPU immediate constants. 1143 'H' means the same constant negated. */ 1144 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ 1145 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \ 1146 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) 1147 1148 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ 1149 (TARGET_ARM ? \ 1150 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0) 1151 1152 /* For the ARM, `Q' means that this is a memory operand that is just 1153 an offset from a register. 1154 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL 1155 address. This means that the symbol is in the text segment and can be 1156 accessed without using a load. */ 1157 1158 #define EXTRA_CONSTRAINT_ARM(OP, C) \ 1159 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ 1160 (C) == 'R' ? (GET_CODE (OP) == MEM \ 1161 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ 1162 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ 1163 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ 1164 : 0) 1165 1166 #define EXTRA_CONSTRAINT_THUMB(X, C) \ 1167 ((C) == 'Q' ? (GET_CODE (X) == MEM \ 1168 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0) 1169 1170 #define EXTRA_CONSTRAINT(X, C) \ 1171 (TARGET_ARM ? \ 1172 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C)) 1173 1174 /* Given an rtx X being reloaded into a reg required to be 1175 in class CLASS, return the class of reg to actually use. 1176 In general this is just CLASS, but for the Thumb we prefer 1177 a LO_REGS class or a subset. */ 1178 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1179 (TARGET_ARM ? (CLASS) : \ 1180 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS)) 1181 1182 /* Must leave BASE_REGS reloads alone */ 1183 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1184 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1185 ? ((true_regnum (X) == -1 ? LO_REGS \ 1186 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1187 : NO_REGS)) \ 1188 : NO_REGS) 1189 1190 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1191 ((CLASS) != LO_REGS \ 1192 ? ((true_regnum (X) == -1 ? LO_REGS \ 1193 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1194 : NO_REGS)) \ 1195 : NO_REGS) 1196 1197 /* Return the register class of a scratch register needed to copy IN into 1198 or out of a register in CLASS in MODE. If it can be done directly, 1199 NO_REGS is returned. */ 1200 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1201 (TARGET_ARM ? \ 1202 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1203 ? GENERAL_REGS : NO_REGS) \ 1204 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1205 1206 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1207 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1208 (TARGET_ARM ? \ 1209 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ 1210 && (GET_CODE (X) == MEM \ 1211 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 1212 && true_regnum (X) == -1))) \ 1213 ? GENERAL_REGS : NO_REGS) \ 1214 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)) 1215 1216 /* Try a machine-dependent way of reloading an illegitimate address 1217 operand. If we find one, push the reload and jump to WIN. This 1218 macro is used in only one place: `find_reloads_address' in reload.c. 1219 1220 For the ARM, we wish to handle large displacements off a base 1221 register by splitting the addend across a MOV and the mem insn. 1222 This can cut the number of reloads needed. */ 1223 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1224 do \ 1225 { \ 1226 if (GET_CODE (X) == PLUS \ 1227 && GET_CODE (XEXP (X, 0)) == REG \ 1228 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 1229 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 1230 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1231 { \ 1232 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1233 HOST_WIDE_INT low, high; \ 1234 \ 1235 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ 1236 low = ((val & 0xf) ^ 0x8) - 0x8; \ 1237 else if (MODE == SImode \ 1238 || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 1239 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ 1240 /* Need to be careful, -4096 is not a valid offset. */ \ 1241 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 1242 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ 1243 /* Need to be careful, -256 is not a valid offset. */ \ 1244 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1245 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1246 && TARGET_HARD_FLOAT) \ 1247 /* Need to be careful, -1024 is not a valid offset. */ \ 1248 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 1249 else \ 1250 break; \ 1251 \ 1252 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ 1253 ^ (unsigned HOST_WIDE_INT) 0x80000000) \ 1254 - (unsigned HOST_WIDE_INT) 0x80000000); \ 1255 /* Check for overflow or zero */ \ 1256 if (low == 0 || high == 0 || (high + low != val)) \ 1257 break; \ 1258 \ 1259 /* Reload the high part into a base reg; leave the low part \ 1260 in the mem. */ \ 1261 X = gen_rtx_PLUS (GET_MODE (X), \ 1262 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 1263 GEN_INT (high)), \ 1264 GEN_INT (low)); \ 1265 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1266 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ 1267 VOIDmode, 0, 0, OPNUM, TYPE); \ 1268 goto WIN; \ 1269 } \ 1270 } \ 1271 while (0) 1272 1273 /* ??? If an HImode FP+large_offset address is converted to an HImode 1274 SP+large_offset address, then reload won't know how to fix it. It sees 1275 only that SP isn't valid for HImode, and so reloads the SP into an index 1276 register, but the resulting address is still invalid because the offset 1277 is too big. We fix it here instead by reloading the entire address. */ 1278 /* We could probably achieve better results by defining PROMOTE_MODE to help 1279 cope with the variances between the Thumb's signed and unsigned byte and 1280 halfword load instructions. */ 1281 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1282 { \ 1283 if (GET_CODE (X) == PLUS \ 1284 && GET_MODE_SIZE (MODE) < 4 \ 1285 && GET_CODE (XEXP (X, 0)) == REG \ 1286 && XEXP (X, 0) == stack_pointer_rtx \ 1287 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1288 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ 1289 { \ 1290 rtx orig_X = X; \ 1291 X = copy_rtx (X); \ 1292 push_reload (orig_X, NULL_RTX, &X, NULL, \ 1293 MODE_BASE_REG_CLASS (MODE), \ 1294 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \ 1295 goto WIN; \ 1296 } \ 1297 } 1298 1299 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1300 if (TARGET_ARM) \ 1301 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1302 else \ 1303 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1304 1305 /* Return the maximum number of consecutive registers 1306 needed to represent mode MODE in a register of class CLASS. 1307 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ 1308 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1309 ((CLASS) == FPU_REGS ? 1 : ARM_NUM_REGS (MODE)) 1310 1311 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ 1312 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1313 (TARGET_ARM ? \ 1314 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \ 1315 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \ 1316 : \ 1317 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1318 1319 /* Stack layout; function entry, exit and calling. */ 1320 1321 /* Define this if pushing a word on the stack 1322 makes the stack pointer a smaller address. */ 1323 #define STACK_GROWS_DOWNWARD 1 1324 1325 /* Define this if the nominal address of the stack frame 1326 is at the high-address end of the local variables; 1327 that is, each additional local variable allocated 1328 goes at a more negative offset in the frame. */ 1329 #define FRAME_GROWS_DOWNWARD 1 1330 1331 /* Offset within stack frame to start allocating local variables at. 1332 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1333 first local allocated. Otherwise, it is the offset to the BEGINNING 1334 of the first local allocated. */ 1335 #define STARTING_FRAME_OFFSET 0 1336 1337 /* If we generate an insn to push BYTES bytes, 1338 this says how many the stack pointer really advances by. */ 1339 /* The push insns do not do this rounding implicitly. 1340 So don't define this. */ 1341 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */ 1342 1343 /* Define this if the maximum size of all the outgoing args is to be 1344 accumulated and pushed during the prologue. The amount can be 1345 found in the variable current_function_outgoing_args_size. */ 1346 #define ACCUMULATE_OUTGOING_ARGS 1 1347 1348 /* Offset of first parameter from the argument pointer register value. */ 1349 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1350 1351 /* Value is the number of byte of arguments automatically 1352 popped when returning from a subroutine call. 1353 FUNDECL is the declaration node of the function (as a tree), 1354 FUNTYPE is the data type of the function (as a tree), 1355 or for a library call it is an identifier node for the subroutine name. 1356 SIZE is the number of bytes of arguments passed on the stack. 1357 1358 On the ARM, the caller does not pop any of its arguments that were passed 1359 on the stack. */ 1360 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 1361 1362 /* Define how to find the value returned by a library function 1363 assuming the value has mode MODE. */ 1364 #define LIBCALL_VALUE(MODE) \ 1365 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1366 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ 1367 : gen_rtx_REG (MODE, ARG_REGISTER (1))) 1368 1369 /* Define how to find the value returned by a function. 1370 VALTYPE is the data type of the value (as a tree). 1371 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1372 otherwise, FUNC is 0. */ 1373 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1374 LIBCALL_VALUE (TYPE_MODE (VALTYPE)) 1375 1376 /* 1 if N is a possible register number for a function value. 1377 On the ARM, only r0 and f0 can return results. */ 1378 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1379 ((REGNO) == ARG_REGISTER (1) \ 1380 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) 1381 1382 /* How large values are returned */ 1383 /* A C expression which can inhibit the returning of certain function values 1384 in registers, based on the type of value. */ 1385 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) 1386 1387 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1388 values must be in memory. On the ARM, they need only do so if larger 1389 than a word, or if they contain elements offset from zero in the struct. */ 1390 #define DEFAULT_PCC_STRUCT_RETURN 0 1391 1392 /* Flags for the call/call_value rtl operations set up by function_arg. */ 1393 #define CALL_NORMAL 0x00000000 /* No special processing. */ 1394 #define CALL_LONG 0x00000001 /* Always call indirect. */ 1395 #define CALL_SHORT 0x00000002 /* Never call indirect. */ 1396 1397 /* These bits describe the different types of function supported 1398 by the ARM backend. They are exclusive. ie a function cannot be both a 1399 normal function and an interworked function, for example. Knowing the 1400 type of a function is important for determining its prologue and 1401 epilogue sequences. 1402 Note value 7 is currently unassigned. Also note that the interrupt 1403 function types all have bit 2 set, so that they can be tested for easily. 1404 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1405 machine_function structure is initialized (to zero) func_type will 1406 default to unknown. This will force the first use of arm_current_func_type 1407 to call arm_compute_func_type. */ 1408 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1409 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1410 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1411 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ 1412 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1413 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1414 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1415 1416 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1417 1418 /* In addition functions can have several type modifiers, 1419 outlined by these bit masks: */ 1420 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1421 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1422 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1423 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1424 1425 /* Some macros to test these flags. */ 1426 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1427 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1428 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1429 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1430 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1431 1432 /* A C structure for machine-specific, per-function data. 1433 This is added to the cfun structure. */ 1434 typedef struct machine_function GTY(()) 1435 { 1436 /* Additionsl stack adjustment in __builtin_eh_throw. */ 1437 rtx eh_epilogue_sp_ofs; 1438 /* Records if LR has to be saved for far jumps. */ 1439 int far_jump_used; 1440 /* Records if ARG_POINTER was ever live. */ 1441 int arg_pointer_live; 1442 /* Records if the save of LR has been eliminated. */ 1443 int lr_save_eliminated; 1444 /* The size of the stack frame. Only valid after reload. */ 1445 int frame_size; 1446 /* Records the type of the current function. */ 1447 unsigned long func_type; 1448 /* Record if the function has a variable argument list. */ 1449 int uses_anonymous_args; 1450 } 1451 machine_function; 1452 1453 /* A C type for declaring a variable that is used as the first argument of 1454 `FUNCTION_ARG' and other related values. For some target machines, the 1455 type `int' suffices and can hold the number of bytes of argument so far. */ 1456 typedef struct 1457 { 1458 /* This is the number of registers of arguments scanned so far. */ 1459 int nregs; 1460 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */ 1461 int call_cookie; 1462 } CUMULATIVE_ARGS; 1463 1464 /* Define where to put the arguments to a function. 1465 Value is zero to push the argument on the stack, 1466 or a hard register in which to store the argument. 1467 1468 MODE is the argument's machine mode. 1469 TYPE is the data type of the argument (as a tree). 1470 This is null for libcalls where that information may 1471 not be available. 1472 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1473 the preceding args and about the function being called. 1474 NAMED is nonzero if this argument is a named parameter 1475 (otherwise it is an extra parameter matching an ellipsis). 1476 1477 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 1478 other arguments are passed on the stack. If (NAMED == 0) (which happens 1479 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is 1480 passed in the stack (function_prologue will indeed make it pass in the 1481 stack if necessary). */ 1482 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1483 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1484 1485 /* For an arg passed partly in registers and partly in memory, 1486 this is the number of registers used. 1487 For args passed entirely in registers or entirely in memory, zero. */ 1488 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1489 ( NUM_ARG_REGS > (CUM).nregs \ 1490 && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \ 1491 ? NUM_ARG_REGS - (CUM).nregs : 0) 1492 1493 /* A C expression that indicates when an argument must be passed by 1494 reference. If nonzero for an argument, a copy of that argument is 1495 made in memory and a pointer to the argument is passed instead of 1496 the argument itself. The pointer is passed in whatever way is 1497 appropriate for passing a pointer to that type. */ 1498 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1499 arm_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED) 1500 1501 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1502 for a call to a function whose data type is FNTYPE. 1503 For a library call, FNTYPE is 0. 1504 On the ARM, the offset starts at 0. */ 1505 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1506 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT)) 1507 1508 /* Update the data in CUM to advance over an argument 1509 of mode MODE and data type TYPE. 1510 (TYPE is null for libcalls where that information may not be available.) */ 1511 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1512 (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE) 1513 1514 /* 1 if N is a possible register number for function argument passing. 1515 On the ARM, r0-r3 are used to pass args. */ 1516 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3)) 1517 1518 /* Implement `va_arg'. */ 1519 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1520 arm_va_arg (valist, type) 1521 1522 1523 /* Tail calling. */ 1524 1525 /* A C expression that evaluates to true if it is ok to perform a sibling 1526 call to DECL. */ 1527 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL)) 1528 1529 /* Perform any actions needed for a function that is receiving a variable 1530 number of arguments. CUM is as above. MODE and TYPE are the mode and type 1531 of the current parameter. PRETEND_SIZE is a variable that should be set to 1532 the amount of stack that must be pushed by the prolog to pretend that our 1533 caller pushed it. 1534 1535 Normally, this macro will push all remaining incoming registers on the 1536 stack and set PRETEND_SIZE to the length of the registers pushed. 1537 1538 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last 1539 named arg and all anonymous args onto the stack. 1540 XXX I know the prologue shouldn't be pushing registers, but it is faster 1541 that way. */ 1542 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \ 1543 { \ 1544 cfun->machine->uses_anonymous_args = 1; \ 1545 if ((CUM).nregs < NUM_ARG_REGS) \ 1546 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \ 1547 } 1548 1549 /* If your target environment doesn't prefix user functions with an 1550 underscore, you may wish to re-define this to prevent any conflicts. 1551 e.g. AOF may prefix mcount with an underscore. */ 1552 #ifndef ARM_MCOUNT_NAME 1553 #define ARM_MCOUNT_NAME "*mcount" 1554 #endif 1555 1556 /* Call the function profiler with a given profile label. The Acorn 1557 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1558 On the ARM the full profile code will look like: 1559 .data 1560 LP1 1561 .word 0 1562 .text 1563 mov ip, lr 1564 bl mcount 1565 .word LP1 1566 1567 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1568 will output the .text section. 1569 1570 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1571 ``prof'' doesn't seem to mind about this! 1572 1573 Note - this version of the code is designed to work in both ARM and 1574 Thumb modes. */ 1575 #ifndef ARM_FUNCTION_PROFILER 1576 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1577 { \ 1578 char temp[20]; \ 1579 rtx sym; \ 1580 \ 1581 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1582 IP_REGNUM, LR_REGNUM); \ 1583 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1584 fputc ('\n', STREAM); \ 1585 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1586 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \ 1587 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1588 } 1589 #endif 1590 1591 #ifdef THUMB_FUNCTION_PROFILER 1592 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1593 if (TARGET_ARM) \ 1594 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1595 else \ 1596 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1597 #else 1598 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1599 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1600 #endif 1601 1602 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1603 the stack pointer does not matter. The value is tested only in 1604 functions that have frame pointers. 1605 No definition is equivalent to always zero. 1606 1607 On the ARM, the function epilogue recovers the stack pointer from the 1608 frame. */ 1609 #define EXIT_IGNORE_STACK 1 1610 1611 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM) 1612 1613 /* Determine if the epilogue should be output as RTL. 1614 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1615 #define USE_RETURN_INSN(ISCOND) \ 1616 (TARGET_ARM ? use_return_insn (ISCOND) : 0) 1617 1618 /* Definitions for register eliminations. 1619 1620 This is an array of structures. Each structure initializes one pair 1621 of eliminable registers. The "from" register number is given first, 1622 followed by "to". Eliminations of the same "from" register are listed 1623 in order of preference. 1624 1625 We have two registers that can be eliminated on the ARM. First, the 1626 arg pointer register can often be eliminated in favor of the stack 1627 pointer register. Secondly, the pseudo frame pointer register can always 1628 be eliminated; it is replaced with either the stack or the real frame 1629 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1630 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1631 1632 #define ELIMINABLE_REGS \ 1633 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1634 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1635 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1636 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1637 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1638 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1639 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1640 1641 /* Given FROM and TO register numbers, say whether this elimination is 1642 allowed. Frame pointer elimination is automatically handled. 1643 1644 All eliminations are permissible. Note that ARG_POINTER_REGNUM and 1645 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame 1646 pointer, we must eliminate FRAME_POINTER_REGNUM into 1647 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or 1648 ARG_POINTER_REGNUM. */ 1649 #define CAN_ELIMINATE(FROM, TO) \ 1650 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \ 1651 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \ 1652 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \ 1653 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \ 1654 1) 1655 1656 #define THUMB_REG_PUSHED_P(reg) \ 1657 (regs_ever_live [reg] \ 1658 && (! call_used_regs [reg] \ 1659 || (flag_pic && (reg) == PIC_OFFSET_TABLE_REGNUM)) \ 1660 && !(TARGET_SINGLE_PIC_BASE && ((reg) == arm_pic_register))) 1661 1662 /* Define the offset between two registers, one to be eliminated, and the 1663 other its replacement, at the start of a routine. */ 1664 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1665 do \ 1666 { \ 1667 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1668 } \ 1669 while (0) 1670 1671 /* Note: This macro must match the code in thumb_function_prologue(). */ 1672 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1673 { \ 1674 (OFFSET) = 0; \ 1675 if ((FROM) == ARG_POINTER_REGNUM) \ 1676 { \ 1677 int count_regs = 0; \ 1678 int regno; \ 1679 for (regno = 8; regno < 13; regno ++) \ 1680 if (THUMB_REG_PUSHED_P (regno)) \ 1681 count_regs ++; \ 1682 if (count_regs) \ 1683 (OFFSET) += 4 * count_regs; \ 1684 count_regs = 0; \ 1685 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \ 1686 if (THUMB_REG_PUSHED_P (regno)) \ 1687 count_regs ++; \ 1688 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\ 1689 (OFFSET) += 4 * (count_regs + 1); \ 1690 if (TARGET_BACKTRACE) \ 1691 { \ 1692 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \ 1693 (OFFSET) += 20; \ 1694 else \ 1695 (OFFSET) += 16; \ 1696 } \ 1697 } \ 1698 if ((TO) == STACK_POINTER_REGNUM) \ 1699 { \ 1700 (OFFSET) += current_function_outgoing_args_size; \ 1701 (OFFSET) += thumb_get_frame_size (); \ 1702 } \ 1703 } 1704 1705 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1706 if (TARGET_ARM) \ 1707 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \ 1708 else \ 1709 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET) 1710 1711 /* Special case handling of the location of arguments passed on the stack. */ 1712 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1713 1714 /* Initialize data used by insn expanders. This is called from insn_emit, 1715 once for every function before code is generated. */ 1716 #define INIT_EXPANDERS arm_init_expanders () 1717 1718 /* Output assembler code for a block containing the constant parts 1719 of a trampoline, leaving space for the variable parts. 1720 1721 On the ARM, (if r8 is the static chain regnum, and remembering that 1722 referencing pc adds an offset of 8) the trampoline looks like: 1723 ldr r8, [pc, #0] 1724 ldr pc, [pc] 1725 .word static chain value 1726 .word function's address 1727 ??? FIXME: When the trampoline returns, r8 will be clobbered. */ 1728 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ 1729 { \ 1730 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 1731 STATIC_CHAIN_REGNUM, PC_REGNUM); \ 1732 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ 1733 PC_REGNUM, PC_REGNUM); \ 1734 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1735 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 1736 } 1737 1738 /* On the Thumb we always switch into ARM mode to execute the trampoline. 1739 Why - because it is easier. This code will always be branched to via 1740 a BX instruction and since the compiler magically generates the address 1741 of the function the linker has no opportunity to ensure that the 1742 bottom bit is set. Thus the processor will be in ARM mode when it 1743 reaches this code. So we duplicate the ARM trampoline code and add 1744 a switch into Thumb mode as well. */ 1745 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \ 1746 { \ 1747 fprintf (FILE, "\t.code 32\n"); \ 1748 fprintf (FILE, ".Ltrampoline_start:\n"); \ 1749 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ 1750 STATIC_CHAIN_REGNUM, PC_REGNUM); \ 1751 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \ 1752 IP_REGNUM, PC_REGNUM); \ 1753 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \ 1754 IP_REGNUM, IP_REGNUM); \ 1755 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \ 1756 fprintf (FILE, "\t.word\t0\n"); \ 1757 fprintf (FILE, "\t.word\t0\n"); \ 1758 fprintf (FILE, "\t.code 16\n"); \ 1759 } 1760 1761 #define TRAMPOLINE_TEMPLATE(FILE) \ 1762 if (TARGET_ARM) \ 1763 ARM_TRAMPOLINE_TEMPLATE (FILE) \ 1764 else \ 1765 THUMB_TRAMPOLINE_TEMPLATE (FILE) 1766 1767 /* Length in units of the trampoline for entering a nested function. */ 1768 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24) 1769 1770 /* Alignment required for a trampoline in bits. */ 1771 #define TRAMPOLINE_ALIGNMENT 32 1772 1773 /* Emit RTL insns to initialize the variable parts of a trampoline. 1774 FNADDR is an RTX for the address of the function's pure code. 1775 CXT is an RTX for the static chain value for the function. */ 1776 #ifndef INITIALIZE_TRAMPOLINE 1777 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 1778 { \ 1779 emit_move_insn (gen_rtx_MEM (SImode, \ 1780 plus_constant (TRAMP, \ 1781 TARGET_ARM ? 8 : 16)), \ 1782 CXT); \ 1783 emit_move_insn (gen_rtx_MEM (SImode, \ 1784 plus_constant (TRAMP, \ 1785 TARGET_ARM ? 12 : 20)), \ 1786 FNADDR); \ 1787 } 1788 #endif 1789 1790 1791 /* Addressing modes, and classification of registers for them. */ 1792 #define HAVE_POST_INCREMENT 1 1793 #define HAVE_PRE_INCREMENT TARGET_ARM 1794 #define HAVE_POST_DECREMENT TARGET_ARM 1795 #define HAVE_PRE_DECREMENT TARGET_ARM 1796 1797 /* Macros to check register numbers against specific register classes. */ 1798 1799 /* These assume that REGNO is a hard or pseudo reg number. 1800 They give nonzero only if REGNO is a hard reg of the suitable class 1801 or a pseudo reg currently allocated to a suitable hard reg. 1802 Since they use reg_renumber, they are safe only once reg_renumber 1803 has been allocated, which happens in local-alloc.c. */ 1804 #define TEST_REGNO(R, TEST, VALUE) \ 1805 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1806 1807 /* On the ARM, don't allow the pc to be used. */ 1808 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1809 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1810 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1811 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1812 1813 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1814 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1815 || (GET_MODE_SIZE (MODE) >= 4 \ 1816 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1817 1818 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1819 (TARGET_THUMB \ 1820 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1821 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1822 1823 /* For ARM code, we don't care about the mode, but for Thumb, the index 1824 must be suitable for use in a QImode load. */ 1825 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1826 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) 1827 1828 /* Maximum number of registers that can appear in a valid memory address. 1829 Shifts in addresses can't be by a register. */ 1830 #define MAX_REGS_PER_ADDRESS 2 1831 1832 /* Recognize any constant value that is a valid address. */ 1833 /* XXX We can address any constant, eventually... */ 1834 1835 #ifdef AOF_ASSEMBLER 1836 1837 #define CONSTANT_ADDRESS_P(X) \ 1838 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X)) 1839 1840 #else 1841 1842 #define CONSTANT_ADDRESS_P(X) \ 1843 (GET_CODE (X) == SYMBOL_REF \ 1844 && (CONSTANT_POOL_ADDRESS_P (X) \ 1845 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1846 1847 #endif /* AOF_ASSEMBLER */ 1848 1849 /* Nonzero if the constant value X is a legitimate general operand. 1850 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1851 1852 On the ARM, allow any integer (invalid ones are removed later by insn 1853 patterns), nice doubles and symbol_refs which refer to the function's 1854 constant pool XXX. 1855 1856 When generating pic allow anything. */ 1857 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 1858 1859 #define THUMB_LEGITIMATE_CONSTANT_P(X) \ 1860 ( GET_CODE (X) == CONST_INT \ 1861 || GET_CODE (X) == CONST_DOUBLE \ 1862 || CONSTANT_ADDRESS_P (X) \ 1863 || flag_pic) 1864 1865 #define LEGITIMATE_CONSTANT_P(X) \ 1866 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X)) 1867 1868 /* Special characters prefixed to function names 1869 in order to encode attribute like information. 1870 Note, '@' and '*' have already been taken. */ 1871 #define SHORT_CALL_FLAG_CHAR '^' 1872 #define LONG_CALL_FLAG_CHAR '#' 1873 1874 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \ 1875 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR) 1876 1877 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \ 1878 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR) 1879 1880 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1881 #define SUBTARGET_NAME_ENCODING_LENGTHS 1882 #endif 1883 1884 /* This is a C fragement for the inside of a switch statement. 1885 Each case label should return the number of characters to 1886 be stripped from the start of a function's name, if that 1887 name starts with the indicated character. */ 1888 #define ARM_NAME_ENCODING_LENGTHS \ 1889 case SHORT_CALL_FLAG_CHAR: return 1; \ 1890 case LONG_CALL_FLAG_CHAR: return 1; \ 1891 case '*': return 1; \ 1892 SUBTARGET_NAME_ENCODING_LENGTHS 1893 1894 /* This is how to output a reference to a user-level label named NAME. 1895 `assemble_name' uses this. */ 1896 #undef ASM_OUTPUT_LABELREF 1897 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1898 arm_asm_output_labelref (FILE, NAME) 1899 1900 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \ 1901 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR) 1902 1903 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1904 and check its validity for a certain class. 1905 We have two alternate definitions for each of them. 1906 The usual definition accepts all pseudo regs; the other rejects 1907 them unless they have been allocated suitable hard regs. 1908 The symbol REG_OK_STRICT causes the latter definition to be used. */ 1909 #ifndef REG_OK_STRICT 1910 1911 #define ARM_REG_OK_FOR_BASE_P(X) \ 1912 (REGNO (X) <= LAST_ARM_REGNUM \ 1913 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1914 || REGNO (X) == FRAME_POINTER_REGNUM \ 1915 || REGNO (X) == ARG_POINTER_REGNUM) 1916 1917 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1918 (REGNO (X) <= LAST_LO_REGNUM \ 1919 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1920 || (GET_MODE_SIZE (MODE) >= 4 \ 1921 && (REGNO (X) == STACK_POINTER_REGNUM \ 1922 || (X) == hard_frame_pointer_rtx \ 1923 || (X) == arg_pointer_rtx))) 1924 1925 #else /* REG_OK_STRICT */ 1926 1927 #define ARM_REG_OK_FOR_BASE_P(X) \ 1928 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1929 1930 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1931 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1932 1933 #endif /* REG_OK_STRICT */ 1934 1935 /* Now define some helpers in terms of the above. */ 1936 1937 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1938 (TARGET_THUMB \ 1939 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1940 : ARM_REG_OK_FOR_BASE_P (X)) 1941 1942 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X) 1943 1944 /* For Thumb, a valid index register is anything that can be used in 1945 a byte load instruction. */ 1946 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode) 1947 1948 /* Nonzero if X is a hard reg that can be used as an index 1949 or if it is a pseudo reg. On the Thumb, the stack pointer 1950 is not suitable. */ 1951 #define REG_OK_FOR_INDEX_P(X) \ 1952 (TARGET_THUMB \ 1953 ? THUMB_REG_OK_FOR_INDEX_P (X) \ 1954 : ARM_REG_OK_FOR_INDEX_P (X)) 1955 1956 1957 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1958 that is a valid memory address for an instruction. 1959 The MODE argument is the machine mode for the MEM expression 1960 that wants to use this address. 1961 1962 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 1963 1964 /* --------------------------------arm version----------------------------- */ 1965 #define ARM_BASE_REGISTER_RTX_P(X) \ 1966 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 1967 1968 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1969 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 1970 1971 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs 1972 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can 1973 only be small constants. */ 1974 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ 1975 do \ 1976 { \ 1977 HOST_WIDE_INT range; \ 1978 enum rtx_code code = GET_CODE (INDEX); \ 1979 \ 1980 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1981 { \ 1982 if (code == CONST_INT && INTVAL (INDEX) < 1024 \ 1983 && INTVAL (INDEX) > -1024 \ 1984 && (INTVAL (INDEX) & 3) == 0) \ 1985 goto LABEL; \ 1986 } \ 1987 else \ 1988 { \ 1989 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \ 1990 && GET_MODE_SIZE (MODE) <= 4) \ 1991 goto LABEL; \ 1992 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ 1993 && (! arm_arch4 || (MODE) != HImode)) \ 1994 { \ 1995 rtx xiop0 = XEXP (INDEX, 0); \ 1996 rtx xiop1 = XEXP (INDEX, 1); \ 1997 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \ 1998 && power_of_two_operand (xiop1, SImode)) \ 1999 goto LABEL; \ 2000 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \ 2001 && power_of_two_operand (xiop0, SImode)) \ 2002 goto LABEL; \ 2003 } \ 2004 if (GET_MODE_SIZE (MODE) <= 4 \ 2005 && (code == LSHIFTRT || code == ASHIFTRT \ 2006 || code == ASHIFT || code == ROTATERT) \ 2007 && (! arm_arch4 || (MODE) != HImode)) \ 2008 { \ 2009 rtx op = XEXP (INDEX, 1); \ 2010 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ 2011 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ 2012 && INTVAL (op) <= 31) \ 2013 goto LABEL; \ 2014 } \ 2015 /* XXX For ARM v4 we may be doing a sign-extend operation \ 2016 during the load, but that has a restricted addressing \ 2017 range and we are unable to tell here whether that is the \ 2018 case. To be safe we restrict all loads to that \ 2019 range. */ \ 2020 if (arm_arch4) \ 2021 range = (mode == HImode || mode == QImode) ? 256 : 4096; \ 2022 else if (mode == HImode) \ 2023 range = 4095; \ 2024 else \ 2025 range = 4096; \ 2026 if (code == CONST_INT && INTVAL (INDEX) < range \ 2027 && INTVAL (INDEX) > -range) \ 2028 goto LABEL; \ 2029 } \ 2030 } \ 2031 while (0) 2032 2033 /* Jump to LABEL if X is a valid address RTX. This must take 2034 REG_OK_STRICT into account when deciding about valid registers. 2035 2036 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non 2037 floating SYMBOL_REF to the constant pool. Allow REG-only and 2038 AUTINC-REG if handling TImode or HImode. Other symbol refs must be 2039 forced though a static cell to ensure addressability. */ 2040 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 2041 { \ 2042 if (ARM_BASE_REGISTER_RTX_P (X)) \ 2043 goto LABEL; \ 2044 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ 2045 && GET_CODE (XEXP (X, 0)) == REG \ 2046 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ 2047 goto LABEL; \ 2048 else if (reload_completed \ 2049 && (GET_CODE (X) == LABEL_REF \ 2050 || (GET_CODE (X) == CONST \ 2051 && GET_CODE (XEXP ((X), 0)) == PLUS \ 2052 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ 2053 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ 2054 goto LABEL; \ 2055 else if ((MODE) == TImode) \ 2056 ; \ 2057 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ 2058 { \ 2059 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \ 2060 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2061 { \ 2062 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 2063 if (val == 4 || val == -4 || val == -8) \ 2064 goto LABEL; \ 2065 } \ 2066 } \ 2067 else if (GET_CODE (X) == PLUS) \ 2068 { \ 2069 rtx xop0 = XEXP (X, 0); \ 2070 rtx xop1 = XEXP (X, 1); \ 2071 \ 2072 if (ARM_BASE_REGISTER_RTX_P (xop0)) \ 2073 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ 2074 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \ 2075 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ 2076 } \ 2077 /* Reload currently can't handle MINUS, so disable this for now */ \ 2078 /* else if (GET_CODE (X) == MINUS) \ 2079 { \ 2080 rtx xop0 = XEXP (X,0); \ 2081 rtx xop1 = XEXP (X,1); \ 2082 \ 2083 if (ARM_BASE_REGISTER_RTX_P (xop0)) \ 2084 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ 2085 } */ \ 2086 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ 2087 && GET_CODE (X) == SYMBOL_REF \ 2088 && CONSTANT_POOL_ADDRESS_P (X) \ 2089 && ! (flag_pic \ 2090 && symbol_mentioned_p (get_pool_constant (X)))) \ 2091 goto LABEL; \ 2092 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ 2093 && (GET_MODE_SIZE (MODE) <= 4) \ 2094 && GET_CODE (XEXP (X, 0)) == REG \ 2095 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ 2096 goto LABEL; \ 2097 } 2098 2099 /* ---------------------thumb version----------------------------------*/ 2100 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \ 2101 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ 2102 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \ 2103 && ((VAL) & 1) == 0) \ 2104 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \ 2105 && ((VAL) & 3) == 0)) 2106 2107 /* The AP may be eliminated to either the SP or the FP, so we use the 2108 least common denominator, e.g. SImode, and offsets from 0 to 64. */ 2109 2110 /* ??? Verify whether the above is the right approach. */ 2111 2112 /* ??? Also, the FP may be eliminated to the SP, so perhaps that 2113 needs special handling also. */ 2114 2115 /* ??? Look at how the mips16 port solves this problem. It probably uses 2116 better ways to solve some of these problems. */ 2117 2118 /* Although it is not incorrect, we don't accept QImode and HImode 2119 addresses based on the frame pointer or arg pointer until the 2120 reload pass starts. This is so that eliminating such addresses 2121 into stack based ones won't produce impossible code. */ 2122 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 2123 { \ 2124 /* ??? Not clear if this is right. Experiment. */ \ 2125 if (GET_MODE_SIZE (MODE) < 4 \ 2126 && ! (reload_in_progress || reload_completed) \ 2127 && ( reg_mentioned_p (frame_pointer_rtx, X) \ 2128 || reg_mentioned_p (arg_pointer_rtx, X) \ 2129 || reg_mentioned_p (virtual_incoming_args_rtx, X) \ 2130 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \ 2131 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \ 2132 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \ 2133 ; \ 2134 /* Accept any base register. SP only in SImode or larger. */ \ 2135 else if (GET_CODE (X) == REG \ 2136 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \ 2137 goto WIN; \ 2138 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \ 2139 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \ 2140 && GET_CODE (X) == SYMBOL_REF \ 2141 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \ 2142 goto WIN; \ 2143 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \ 2144 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ 2145 && (GET_CODE (X) == LABEL_REF \ 2146 || (GET_CODE (X) == CONST \ 2147 && GET_CODE (XEXP (X, 0)) == PLUS \ 2148 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \ 2149 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \ 2150 goto WIN; \ 2151 /* Post-inc indexing only supported for SImode and larger. */ \ 2152 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \ 2153 && GET_CODE (XEXP (X, 0)) == REG \ 2154 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ 2155 goto WIN; \ 2156 else if (GET_CODE (X) == PLUS) \ 2157 { \ 2158 /* REG+REG address can be any two index registers. */ \ 2159 /* We disallow FRAME+REG addressing since we know that FRAME \ 2160 will be replaced with STACK, and SP relative addressing only \ 2161 permits SP+OFFSET. */ \ 2162 if (GET_MODE_SIZE (MODE) <= 4 \ 2163 && GET_CODE (XEXP (X, 0)) == REG \ 2164 && GET_CODE (XEXP (X, 1)) == REG \ 2165 && XEXP (X, 0) != frame_pointer_rtx \ 2166 && XEXP (X, 1) != frame_pointer_rtx \ 2167 && XEXP (X, 0) != virtual_stack_vars_rtx \ 2168 && XEXP (X, 1) != virtual_stack_vars_rtx \ 2169 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ 2170 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \ 2171 goto WIN; \ 2172 /* REG+const has 5-7 bit offset for non-SP registers. */ \ 2173 else if (GET_CODE (XEXP (X, 0)) == REG \ 2174 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ 2175 || XEXP (X, 0) == arg_pointer_rtx) \ 2176 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2177 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ 2178 goto WIN; \ 2179 /* REG+const has 10 bit offset for SP, but only SImode and \ 2180 larger is supported. */ \ 2181 /* ??? Should probably check for DI/DFmode overflow here \ 2182 just like GO_IF_LEGITIMATE_OFFSET does. */ \ 2183 else if (GET_CODE (XEXP (X, 0)) == REG \ 2184 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \ 2185 && GET_MODE_SIZE (MODE) >= 4 \ 2186 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2187 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \ 2188 + GET_MODE_SIZE (MODE)) <= 1024 \ 2189 && (INTVAL (XEXP (X, 1)) & 3) == 0) \ 2190 goto WIN; \ 2191 else if (GET_CODE (XEXP (X, 0)) == REG \ 2192 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \ 2193 && GET_MODE_SIZE (MODE) >= 4 \ 2194 && GET_CODE (XEXP (X, 1)) == CONST_INT \ 2195 && (INTVAL (XEXP (X, 1)) & 3) == 0) \ 2196 goto WIN; \ 2197 } \ 2198 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ 2199 && GET_MODE_SIZE (mode) == 4 \ 2200 && GET_CODE (X) == SYMBOL_REF \ 2201 && CONSTANT_POOL_ADDRESS_P (X) \ 2202 && ! (flag_pic \ 2203 && symbol_mentioned_p (get_pool_constant (X)))) \ 2204 goto WIN; \ 2205 } 2206 2207 /* ------------------------------------------------------------------- */ 2208 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ 2209 if (TARGET_ARM) \ 2210 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ 2211 else /* if (TARGET_THUMB) */ \ 2212 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) 2213 /* ------------------------------------------------------------------- */ 2214 2215 /* Try machine-dependent ways of modifying an illegitimate address 2216 to be legitimate. If we find one, return the new, valid address. 2217 This macro is used in only one place: `memory_address' in explow.c. 2218 2219 OLDX is the address as it was before break_out_memory_refs was called. 2220 In some cases it is useful to look at this to decide what needs to be done. 2221 2222 MODE and WIN are passed so that this macro can use 2223 GO_IF_LEGITIMATE_ADDRESS. 2224 2225 It is always safe for this macro to do nothing. It exists to recognize 2226 opportunities to optimize the output. 2227 2228 On the ARM, try to convert [REG, #BIGCONST] 2229 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], 2230 where VALIDCONST == 0 in case of TImode. */ 2231 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2232 { \ 2233 if (GET_CODE (X) == PLUS) \ 2234 { \ 2235 rtx xop0 = XEXP (X, 0); \ 2236 rtx xop1 = XEXP (X, 1); \ 2237 \ 2238 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ 2239 xop0 = force_reg (SImode, xop0); \ 2240 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ 2241 xop1 = force_reg (SImode, xop1); \ 2242 if (ARM_BASE_REGISTER_RTX_P (xop0) \ 2243 && GET_CODE (xop1) == CONST_INT) \ 2244 { \ 2245 HOST_WIDE_INT n, low_n; \ 2246 rtx base_reg, val; \ 2247 n = INTVAL (xop1); \ 2248 \ 2249 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ 2250 { \ 2251 low_n = n & 0x0f; \ 2252 n &= ~0x0f; \ 2253 if (low_n > 4) \ 2254 { \ 2255 n += 16; \ 2256 low_n -= 16; \ 2257 } \ 2258 } \ 2259 else \ 2260 { \ 2261 low_n = ((MODE) == TImode ? 0 \ 2262 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ 2263 n -= low_n; \ 2264 } \ 2265 base_reg = gen_reg_rtx (SImode); \ 2266 val = force_operand (gen_rtx_PLUS (SImode, xop0, \ 2267 GEN_INT (n)), NULL_RTX); \ 2268 emit_move_insn (base_reg, val); \ 2269 (X) = (low_n == 0 ? base_reg \ 2270 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ 2271 } \ 2272 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ 2273 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ 2274 } \ 2275 else if (GET_CODE (X) == MINUS) \ 2276 { \ 2277 rtx xop0 = XEXP (X, 0); \ 2278 rtx xop1 = XEXP (X, 1); \ 2279 \ 2280 if (CONSTANT_P (xop0)) \ 2281 xop0 = force_reg (SImode, xop0); \ 2282 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ 2283 xop1 = force_reg (SImode, xop1); \ 2284 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ 2285 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ 2286 } \ 2287 if (flag_pic) \ 2288 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ 2289 if (memory_address_p (MODE, X)) \ 2290 goto WIN; \ 2291 } 2292 2293 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2294 if (flag_pic) \ 2295 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); 2296 2297 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ 2298 if (TARGET_ARM) \ 2299 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \ 2300 else \ 2301 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) 2302 2303 /* Go to LABEL if ADDR (a legitimate address expression) 2304 has an effect that depends on the machine mode it is used for. */ 2305 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2306 { \ 2307 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \ 2308 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \ 2309 goto LABEL; \ 2310 } 2311 2312 /* Nothing helpful to do for the Thumb */ 2313 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 2314 if (TARGET_ARM) \ 2315 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL) 2316 2317 2318 /* Specify the machine mode that this machine uses 2319 for the index in the tablejump instruction. */ 2320 #define CASE_VECTOR_MODE Pmode 2321 2322 /* Define as C expression which evaluates to nonzero if the tablejump 2323 instruction expects the table to contain offsets from the address of the 2324 table. 2325 Do not define this if the table should contain absolute addresses. */ 2326 /* #define CASE_VECTOR_PC_RELATIVE 1 */ 2327 2328 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2329 unsigned is probably best, but may break some code. */ 2330 #ifndef DEFAULT_SIGNED_CHAR 2331 #define DEFAULT_SIGNED_CHAR 0 2332 #endif 2333 2334 /* Don't cse the address of the function being compiled. */ 2335 #define NO_RECURSIVE_FUNCTION_CSE 1 2336 2337 /* Max number of bytes we can move from memory to memory 2338 in one reasonably fast instruction. */ 2339 #define MOVE_MAX 4 2340 2341 #undef MOVE_RATIO 2342 #define MOVE_RATIO (arm_arch_xscale ? 4 : 2) 2343 2344 /* Define if operations between registers always perform the operation 2345 on the full register even if a narrower mode is specified. */ 2346 #define WORD_REGISTER_OPERATIONS 2347 2348 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2349 will either zero-extend or sign-extend. The value of this macro should 2350 be the code that says which one of the two operations is implicitly 2351 done, NIL if none. */ 2352 #define LOAD_EXTEND_OP(MODE) \ 2353 (TARGET_THUMB ? ZERO_EXTEND : \ 2354 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2355 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL))) 2356 2357 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2358 #define SLOW_BYTE_ACCESS 0 2359 2360 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2361 2362 /* Immediate shift counts are truncated by the output routines (or was it 2363 the assembler?). Shift counts in a register are truncated by ARM. Note 2364 that the native compiler puts too large (> 32) immediate shift counts 2365 into a register and shifts by the register, letting the ARM decide what 2366 to do instead of doing that itself. */ 2367 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2368 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2369 On the arm, Y in a register is used modulo 256 for the shift. Only for 2370 rotates is modulo 32 used. */ 2371 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2372 2373 /* All integers have the same format so truncation is easy. */ 2374 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2375 2376 /* Calling from registers is a massive pain. */ 2377 #define NO_FUNCTION_CSE 1 2378 2379 /* Chars and shorts should be passed as ints. */ 2380 #define PROMOTE_PROTOTYPES 1 2381 2382 /* The machine modes of pointers and functions */ 2383 #define Pmode SImode 2384 #define FUNCTION_MODE Pmode 2385 2386 #define ARM_FRAME_RTX(X) \ 2387 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2388 || (X) == arg_pointer_rtx) 2389 2390 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \ 2391 return arm_rtx_costs (X, CODE, OUTER_CODE); 2392 2393 /* Moves to and from memory are quite expensive */ 2394 #define MEMORY_MOVE_COST(M, CLASS, IN) \ 2395 (TARGET_ARM ? 10 : \ 2396 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 2397 * (CLASS == LO_REGS ? 1 : 2))) 2398 2399 /* All address computations that can be done are free, but rtx cost returns 2400 the same for practically all of them. So we weight the different types 2401 of address here in the order (most pref first): 2402 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ 2403 #define ARM_ADDRESS_COST(X) \ 2404 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ 2405 || GET_CODE (X) == SYMBOL_REF) \ 2406 ? 0 \ 2407 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ 2408 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ 2409 ? 10 \ 2410 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ 2411 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ 2412 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ 2413 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ 2414 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ 2415 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ 2416 ? 1 : 0)) \ 2417 : 4))))) 2418 2419 #define THUMB_ADDRESS_COST(X) \ 2420 ((GET_CODE (X) == REG \ 2421 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ 2422 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ 2423 ? 1 : 2) 2424 2425 #define ADDRESS_COST(X) \ 2426 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X)) 2427 2428 /* Try to generate sequences that don't involve branches, we can then use 2429 conditional instructions */ 2430 #define BRANCH_COST \ 2431 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0)) 2432 2433 /* Position Independent Code. */ 2434 /* We decide which register to use based on the compilation options and 2435 the assembler in use; this is more general than the APCS restriction of 2436 using sb (r9) all the time. */ 2437 extern int arm_pic_register; 2438 2439 /* Used when parsing command line option -mpic-register=. */ 2440 extern const char * arm_pic_register_string; 2441 2442 /* The register number of the register used to address a table of static 2443 data addresses in memory. */ 2444 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2445 2446 #define FINALIZE_PIC arm_finalize_pic (1) 2447 2448 /* We can't directly access anything that contains a symbol, 2449 nor can we indirect via the constant pool. */ 2450 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2451 (!(symbol_mentioned_p (X) \ 2452 || label_mentioned_p (X) \ 2453 || (GET_CODE (X) == SYMBOL_REF \ 2454 && CONSTANT_POOL_ADDRESS_P (X) \ 2455 && (symbol_mentioned_p (get_pool_constant (X)) \ 2456 || label_mentioned_p (get_pool_constant (X)))))) 2457 2458 /* We need to know when we are making a constant pool; this determines 2459 whether data needs to be in the GOT or can be referenced via a GOT 2460 offset. */ 2461 extern int making_const_table; 2462 2463 /* Handle pragmas for compatibility with Intel's compilers. */ 2464 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ 2465 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \ 2466 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \ 2467 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \ 2468 } while (0) 2469 2470 /* Condition code information. */ 2471 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2472 return the mode to be used for the comparison. */ 2473 2474 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2475 2476 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) 2477 2478 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 2479 do \ 2480 { \ 2481 if (GET_CODE (OP1) == CONST_INT \ 2482 && ! (const_ok_for_arm (INTVAL (OP1)) \ 2483 || (const_ok_for_arm (- INTVAL (OP1))))) \ 2484 { \ 2485 rtx const_op = OP1; \ 2486 CODE = arm_canonicalize_comparison ((CODE), &const_op); \ 2487 OP1 = const_op; \ 2488 } \ 2489 } \ 2490 while (0) 2491 2492 #define STORE_FLAG_VALUE 1 2493 2494 2495 2496 /* Gcc puts the pool in the wrong place for ARM, since we can only 2497 load addresses a limited distance around the pc. We do some 2498 special munging to move the constant pool values to the correct 2499 point in the code. */ 2500 #define MACHINE_DEPENDENT_REORG(INSN) \ 2501 arm_reorg (INSN); \ 2502 2503 #undef ASM_APP_OFF 2504 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") 2505 2506 /* Output an internal label definition. */ 2507 #ifndef ASM_OUTPUT_INTERNAL_LABEL 2508 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ 2509 do \ 2510 { \ 2511 char * s = (char *) alloca (40 + strlen (PREFIX)); \ 2512 \ 2513 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ 2514 && !strcmp (PREFIX, "L")) \ 2515 { \ 2516 arm_ccfsm_state = 0; \ 2517 arm_target_insn = NULL; \ 2518 } \ 2519 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ 2520 ASM_OUTPUT_LABEL (STREAM, s); \ 2521 } \ 2522 while (0) 2523 #endif 2524 2525 /* Output a push or a pop instruction (only used when profiling). */ 2526 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2527 if (TARGET_ARM) \ 2528 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2529 STACK_POINTER_REGNUM, REGNO); \ 2530 else \ 2531 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO) 2532 2533 2534 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2535 if (TARGET_ARM) \ 2536 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2537 STACK_POINTER_REGNUM, REGNO); \ 2538 else \ 2539 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO) 2540 2541 /* This is how to output a label which precedes a jumptable. Since 2542 Thumb instructions are 2 bytes, we may need explicit alignment here. */ 2543 #undef ASM_OUTPUT_CASE_LABEL 2544 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 2545 do \ 2546 { \ 2547 if (TARGET_THUMB) \ 2548 ASM_OUTPUT_ALIGN (FILE, 2); \ 2549 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ 2550 } \ 2551 while (0) 2552 2553 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2554 do \ 2555 { \ 2556 if (TARGET_THUMB) \ 2557 { \ 2558 if (is_called_in_ARM_mode (DECL)) \ 2559 fprintf (STREAM, "\t.code 32\n") ; \ 2560 else \ 2561 fprintf (STREAM, "\t.thumb_func\n") ; \ 2562 } \ 2563 if (TARGET_POKE_FUNCTION_NAME) \ 2564 arm_poke_function_name (STREAM, (char *) NAME); \ 2565 } \ 2566 while (0) 2567 2568 /* For aliases of functions we use .thumb_set instead. */ 2569 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2570 do \ 2571 { \ 2572 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2573 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2574 \ 2575 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2576 { \ 2577 fprintf (FILE, "\t.thumb_set "); \ 2578 assemble_name (FILE, LABEL1); \ 2579 fprintf (FILE, ","); \ 2580 assemble_name (FILE, LABEL2); \ 2581 fprintf (FILE, "\n"); \ 2582 } \ 2583 else \ 2584 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2585 } \ 2586 while (0) 2587 2588 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2589 /* To support -falign-* switches we need to use .p2align so 2590 that alignment directives in code sections will be padded 2591 with no-op instructions, rather than zeroes. */ 2592 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ 2593 if ((LOG) != 0) \ 2594 { \ 2595 if ((MAX_SKIP) == 0) \ 2596 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2597 else \ 2598 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2599 (LOG), (MAX_SKIP)); \ 2600 } 2601 #endif 2602 2603 /* Only perform branch elimination (by making instructions conditional) if 2604 we're optimising. Otherwise it's of no use anyway. */ 2605 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2606 if (TARGET_ARM && optimize) \ 2607 arm_final_prescan_insn (INSN); \ 2608 else if (TARGET_THUMB) \ 2609 thumb_final_prescan_insn (INSN) 2610 2611 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2612 (CODE == '@' || CODE == '|' \ 2613 || (TARGET_ARM && (CODE == '?')) \ 2614 || (TARGET_THUMB && (CODE == '_'))) 2615 2616 /* Output an operand of an instruction. */ 2617 #define PRINT_OPERAND(STREAM, X, CODE) \ 2618 arm_print_operand (STREAM, X, CODE) 2619 2620 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2621 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2622 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2623 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2624 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2625 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2626 : 0)))) 2627 2628 /* Output the address of an operand. */ 2629 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2630 { \ 2631 int is_minus = GET_CODE (X) == MINUS; \ 2632 \ 2633 if (GET_CODE (X) == REG) \ 2634 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ 2635 else if (GET_CODE (X) == PLUS || is_minus) \ 2636 { \ 2637 rtx base = XEXP (X, 0); \ 2638 rtx index = XEXP (X, 1); \ 2639 HOST_WIDE_INT offset = 0; \ 2640 if (GET_CODE (base) != REG) \ 2641 { \ 2642 /* Ensure that BASE is a register */ \ 2643 /* (one of them must be). */ \ 2644 rtx temp = base; \ 2645 base = index; \ 2646 index = temp; \ 2647 } \ 2648 switch (GET_CODE (index)) \ 2649 { \ 2650 case CONST_INT: \ 2651 offset = INTVAL (index); \ 2652 if (is_minus) \ 2653 offset = -offset; \ 2654 asm_fprintf (STREAM, "[%r, #%d]", \ 2655 REGNO (base), offset); \ 2656 break; \ 2657 \ 2658 case REG: \ 2659 asm_fprintf (STREAM, "[%r, %s%r]", \ 2660 REGNO (base), is_minus ? "-" : "", \ 2661 REGNO (index)); \ 2662 break; \ 2663 \ 2664 case MULT: \ 2665 case ASHIFTRT: \ 2666 case LSHIFTRT: \ 2667 case ASHIFT: \ 2668 case ROTATERT: \ 2669 { \ 2670 asm_fprintf (STREAM, "[%r, %s%r", \ 2671 REGNO (base), is_minus ? "-" : "", \ 2672 REGNO (XEXP (index, 0))); \ 2673 arm_print_operand (STREAM, index, 'S'); \ 2674 fputs ("]", STREAM); \ 2675 break; \ 2676 } \ 2677 \ 2678 default: \ 2679 abort(); \ 2680 } \ 2681 } \ 2682 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\ 2683 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\ 2684 { \ 2685 extern int output_memory_reference_mode; \ 2686 \ 2687 if (GET_CODE (XEXP (X, 0)) != REG) \ 2688 abort (); \ 2689 \ 2690 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2691 asm_fprintf (STREAM, "[%r, #%s%d]!", \ 2692 REGNO (XEXP (X, 0)), \ 2693 GET_CODE (X) == PRE_DEC ? "-" : "", \ 2694 GET_MODE_SIZE (output_memory_reference_mode));\ 2695 else \ 2696 asm_fprintf (STREAM, "[%r], #%s%d", \ 2697 REGNO (XEXP (X, 0)), \ 2698 GET_CODE (X) == POST_DEC ? "-" : "", \ 2699 GET_MODE_SIZE (output_memory_reference_mode));\ 2700 } \ 2701 else output_addr_const (STREAM, X); \ 2702 } 2703 2704 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2705 { \ 2706 if (GET_CODE (X) == REG) \ 2707 asm_fprintf (STREAM, "[%r]", REGNO (X)); \ 2708 else if (GET_CODE (X) == POST_INC) \ 2709 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ 2710 else if (GET_CODE (X) == PLUS) \ 2711 { \ 2712 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2713 asm_fprintf (STREAM, "[%r, #%d]", \ 2714 REGNO (XEXP (X, 0)), \ 2715 (int) INTVAL (XEXP (X, 1))); \ 2716 else \ 2717 asm_fprintf (STREAM, "[%r, %r]", \ 2718 REGNO (XEXP (X, 0)), \ 2719 REGNO (XEXP (X, 1))); \ 2720 } \ 2721 else \ 2722 output_addr_const (STREAM, X); \ 2723 } 2724 2725 #define PRINT_OPERAND_ADDRESS(STREAM, X) \ 2726 if (TARGET_ARM) \ 2727 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ 2728 else \ 2729 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) 2730 2731 /* A C expression whose value is RTL representing the value of the return 2732 address for the frame COUNT steps up from the current frame. */ 2733 2734 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2735 arm_return_addr (COUNT, FRAME) 2736 2737 /* Mask of the bits in the PC that contain the real return address 2738 when running in 26-bit mode. */ 2739 #define RETURN_ADDR_MASK26 (0x03fffffc) 2740 2741 /* Pick up the return address upon entry to a procedure. Used for 2742 dwarf2 unwind information. This also enables the table driven 2743 mechanism. */ 2744 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2745 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2746 2747 /* Used to mask out junk bits from the return address, such as 2748 processor state, interrupt status, condition codes and the like. */ 2749 #define MASK_RETURN_ADDR \ 2750 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2751 in 26 bit mode, the condition codes must be masked out of the \ 2752 return address. This does not apply to ARM6 and later processors \ 2753 when running in 32 bit mode. */ \ 2754 ((!TARGET_APCS_32) ? (gen_int_mode (RETURN_ADDR_MASK26, Pmode)) \ 2755 : (arm_arch4 || TARGET_THUMB) ? \ 2756 (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2757 : arm_gen_return_addr_mask ()) 2758 2759 2760 /* Define the codes that are matched by predicates in arm.c */ 2761 #define PREDICATE_CODES \ 2762 {"s_register_operand", {SUBREG, REG}}, \ 2763 {"arm_hard_register_operand", {REG}}, \ 2764 {"f_register_operand", {SUBREG, REG}}, \ 2765 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ 2766 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 2767 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 2768 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ 2769 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ 2770 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ 2771 {"index_operand", {SUBREG, REG, CONST_INT}}, \ 2772 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ 2773 {"offsettable_memory_operand", {MEM}}, \ 2774 {"bad_signed_byte_operand", {MEM}}, \ 2775 {"alignable_memory_operand", {MEM}}, \ 2776 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \ 2777 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \ 2778 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \ 2779 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \ 2780 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \ 2781 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ 2782 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \ 2783 {"load_multiple_operation", {PARALLEL}}, \ 2784 {"store_multiple_operation", {PARALLEL}}, \ 2785 {"equality_operator", {EQ, NE}}, \ 2786 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \ 2787 LTU, UNORDERED, ORDERED, UNLT, UNLE, \ 2788 UNGE, UNGT}}, \ 2789 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \ 2790 {"const_shift_operand", {CONST_INT}}, \ 2791 {"multi_register_push", {PARALLEL}}, \ 2792 {"cc_register", {REG}}, \ 2793 {"logical_binary_operator", {AND, IOR, XOR}}, \ 2794 {"dominant_cc_register", {REG}}, 2795 2796 /* Define this if you have special predicates that know special things 2797 about modes. Genrecog will warn about certain forms of 2798 match_operand without a mode; if the operand predicate is listed in 2799 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ 2800 #define SPECIAL_MODE_PREDICATES \ 2801 "cc_register", "dominant_cc_register", 2802 2803 enum arm_builtins 2804 { 2805 ARM_BUILTIN_CLZ, 2806 ARM_BUILTIN_MAX 2807 }; 2808 #endif /* ! GCC_ARM_H */ 2809