1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 5 6 This file is part of GNU CC. 7 8 GNU CC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GNU CC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GNU CC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23 24 /* Note that some other tm.h files include this one and then override 25 many of the definitions. */ 26 27 /* Definitions for the object file format. These are set at 28 compile-time. */ 29 30 #define OBJECT_XCOFF 1 31 #define OBJECT_ELF 2 32 #define OBJECT_PEF 3 33 #define OBJECT_MACHO 4 34 35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 39 40 #ifndef TARGET_AIX 41 #define TARGET_AIX 0 42 #endif 43 44 /* Default string to use for cpu if not specified. */ 45 #ifndef TARGET_CPU_DEFAULT 46 #define TARGET_CPU_DEFAULT ((char *)0) 47 #endif 48 49 /* Common ASM definitions used by ASM_SPEC among the various targets 50 for handling -mcpu=xxx switches. */ 51 #define ASM_CPU_SPEC \ 52 "%{!mcpu*: \ 53 %{mpower: %{!mpower2: -mpwr}} \ 54 %{mpower2: -mpwrx} \ 55 %{mpowerpc*: -mppc} \ 56 %{mno-power: %{!mpowerpc*: -mcom}} \ 57 %{!mno-power: %{!mpower2: %(asm_default)}}} \ 58 %{mcpu=common: -mcom} \ 59 %{mcpu=power: -mpwr} \ 60 %{mcpu=power2: -mpwrx} \ 61 %{mcpu=power3: -m604} \ 62 %{mcpu=power4: -mpower4} \ 63 %{mcpu=powerpc: -mppc} \ 64 %{mcpu=rios: -mpwr} \ 65 %{mcpu=rios1: -mpwr} \ 66 %{mcpu=rios2: -mpwrx} \ 67 %{mcpu=rsc: -mpwr} \ 68 %{mcpu=rsc1: -mpwr} \ 69 %{mcpu=401: -mppc} \ 70 %{mcpu=403: -m403} \ 71 %{mcpu=405: -m405} \ 72 %{mcpu=505: -mppc} \ 73 %{mcpu=601: -m601} \ 74 %{mcpu=602: -mppc} \ 75 %{mcpu=603: -mppc} \ 76 %{mcpu=603e: -mppc} \ 77 %{mcpu=ec603e: -mppc} \ 78 %{mcpu=604: -mppc} \ 79 %{mcpu=604e: -mppc} \ 80 %{mcpu=620: -mppc} \ 81 %{mcpu=630: -m604} \ 82 %{mcpu=740: -mppc} \ 83 %{mcpu=7400: -mppc} \ 84 %{mcpu=7450: -mppc} \ 85 %{mcpu=750: -mppc} \ 86 %{mcpu=801: -mppc} \ 87 %{mcpu=821: -mppc} \ 88 %{mcpu=823: -mppc} \ 89 %{mcpu=860: -mppc} \ 90 %{mcpu=8540: -me500} \ 91 %{maltivec: -maltivec}" 92 93 #define CPP_DEFAULT_SPEC "" 94 95 #define ASM_DEFAULT_SPEC "" 96 97 /* This macro defines names of additional specifications to put in the specs 98 that can be used in various specifications like CC1_SPEC. Its definition 99 is an initializer with a subgrouping for each command option. 100 101 Each subgrouping contains a string constant, that defines the 102 specification name, and a string constant that used by the GNU CC driver 103 program. 104 105 Do not define this macro if it does not need to do anything. */ 106 107 #define SUBTARGET_EXTRA_SPECS 108 109 #define EXTRA_SPECS \ 110 { "cpp_default", CPP_DEFAULT_SPEC }, \ 111 { "asm_cpu", ASM_CPU_SPEC }, \ 112 { "asm_default", ASM_DEFAULT_SPEC }, \ 113 SUBTARGET_EXTRA_SPECS 114 115 /* Architecture type. */ 116 117 extern int target_flags; 118 119 /* Use POWER architecture instructions and MQ register. */ 120 #define MASK_POWER 0x00000001 121 122 /* Use POWER2 extensions to POWER architecture. */ 123 #define MASK_POWER2 0x00000002 124 125 /* Use PowerPC architecture instructions. */ 126 #define MASK_POWERPC 0x00000004 127 128 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */ 129 #define MASK_PPC_GPOPT 0x00000008 130 131 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */ 132 #define MASK_PPC_GFXOPT 0x00000010 133 134 /* Use PowerPC-64 architecture instructions. */ 135 #define MASK_POWERPC64 0x00000020 136 137 /* Use revised mnemonic names defined for PowerPC architecture. */ 138 #define MASK_NEW_MNEMONICS 0x00000040 139 140 /* Disable placing fp constants in the TOC; can be turned on when the 141 TOC overflows. */ 142 #define MASK_NO_FP_IN_TOC 0x00000080 143 144 /* Disable placing symbol+offset constants in the TOC; can be turned on when 145 the TOC overflows. */ 146 #define MASK_NO_SUM_IN_TOC 0x00000100 147 148 /* Output only one TOC entry per module. Normally linking fails if 149 there are more than 16K unique variables/constants in an executable. With 150 this option, linking fails only if there are more than 16K modules, or 151 if there are more than 16K unique variables/constant in a single module. 152 153 This is at the cost of having 2 extra loads and one extra store per 154 function, and one less allocable register. */ 155 #define MASK_MINIMAL_TOC 0x00000200 156 157 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */ 158 #define MASK_64BIT 0x00000400 159 160 /* Disable use of FPRs. */ 161 #define MASK_SOFT_FLOAT 0x00000800 162 163 /* Enable load/store multiple, even on PowerPC */ 164 #define MASK_MULTIPLE 0x00001000 165 #define MASK_MULTIPLE_SET 0x00002000 166 167 /* Use string instructions for block moves */ 168 #define MASK_STRING 0x00004000 169 #define MASK_STRING_SET 0x00008000 170 171 /* Disable update form of load/store */ 172 #define MASK_NO_UPDATE 0x00010000 173 174 /* Disable fused multiply/add operations */ 175 #define MASK_NO_FUSED_MADD 0x00020000 176 177 /* Nonzero if we need to schedule the prolog and epilog. */ 178 #define MASK_SCHED_PROLOG 0x00040000 179 180 /* Use AltiVec instructions. */ 181 #define MASK_ALTIVEC 0x00080000 182 183 /* Return small structures in memory (as the AIX ABI requires). */ 184 #define MASK_AIX_STRUCT_RET 0x00100000 185 #define MASK_AIX_STRUCT_RET_SET 0x00200000 186 187 /* The only remaining free bit is 0x00400000. sysv4.h uses 188 0x00800000 -> 0x40000000, and 0x80000000 is not available 189 because target_flags is signed. */ 190 191 #define TARGET_POWER (target_flags & MASK_POWER) 192 #define TARGET_POWER2 (target_flags & MASK_POWER2) 193 #define TARGET_POWERPC (target_flags & MASK_POWERPC) 194 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT) 195 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT) 196 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS) 197 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC) 198 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC) 199 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC) 200 #define TARGET_64BIT (target_flags & MASK_64BIT) 201 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT) 202 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE) 203 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET) 204 #define TARGET_STRING (target_flags & MASK_STRING) 205 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET) 206 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE) 207 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) 208 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG) 209 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC) 210 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET) 211 212 #define TARGET_32BIT (! TARGET_64BIT) 213 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) 214 #define TARGET_UPDATE (! TARGET_NO_UPDATE) 215 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD) 216 217 #ifdef IN_LIBGCC2 218 /* For libgcc2 we make sure this is a compile time constant */ 219 #if defined (__64BIT__) || defined (__powerpc64__) 220 #define TARGET_POWERPC64 1 221 #else 222 #define TARGET_POWERPC64 0 223 #endif 224 #else 225 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64) 226 #endif 227 228 #define TARGET_XL_CALL 0 229 230 /* Run-time compilation parameters selecting different hardware subsets. 231 232 Macro to define tables used to set the flags. 233 This is a list in braces of pairs in braces, 234 each pair being { "NAME", VALUE } 235 where VALUE is the bits to set or minus the bits to clear. 236 An empty string NAME is used to identify the default VALUE. */ 237 238 #define TARGET_SWITCHES \ 239 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \ 240 N_("Use POWER instruction set")}, \ 241 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \ 242 | MASK_POWER2), \ 243 N_("Use POWER2 instruction set")}, \ 244 {"no-power2", - MASK_POWER2, \ 245 N_("Do not use POWER2 instruction set")}, \ 246 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \ 247 | MASK_STRING), \ 248 N_("Do not use POWER instruction set")}, \ 249 {"powerpc", MASK_POWERPC, \ 250 N_("Use PowerPC instruction set")}, \ 251 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \ 252 | MASK_PPC_GFXOPT | MASK_POWERPC64), \ 253 N_("Do not use PowerPC instruction set")}, \ 254 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \ 255 N_("Use PowerPC General Purpose group optional instructions")},\ 256 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \ 257 N_("Don't use PowerPC General Purpose group optional instructions")},\ 258 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \ 259 N_("Use PowerPC Graphics group optional instructions")},\ 260 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \ 261 N_("Don't use PowerPC Graphics group optional instructions")},\ 262 {"powerpc64", MASK_POWERPC64, \ 263 N_("Use PowerPC-64 instruction set")}, \ 264 {"no-powerpc64", - MASK_POWERPC64, \ 265 N_("Don't use PowerPC-64 instruction set")}, \ 266 {"altivec", MASK_ALTIVEC , \ 267 N_("Use AltiVec instructions")}, \ 268 {"no-altivec", - MASK_ALTIVEC , \ 269 N_("Don't use AltiVec instructions")}, \ 270 {"new-mnemonics", MASK_NEW_MNEMONICS, \ 271 N_("Use new mnemonics for PowerPC architecture")},\ 272 {"old-mnemonics", -MASK_NEW_MNEMONICS, \ 273 N_("Use old mnemonics for PowerPC architecture")},\ 274 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \ 275 | MASK_MINIMAL_TOC), \ 276 N_("Put everything in the regular TOC")}, \ 277 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \ 278 N_("Place floating point constants in TOC")}, \ 279 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \ 280 N_("Don't place floating point constants in TOC")},\ 281 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \ 282 N_("Place symbol+offset constants in TOC")}, \ 283 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \ 284 N_("Don't place symbol+offset constants in TOC")},\ 285 {"minimal-toc", MASK_MINIMAL_TOC, \ 286 "Use only one TOC entry per procedure"}, \ 287 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \ 288 ""}, \ 289 {"no-minimal-toc", - MASK_MINIMAL_TOC, \ 290 N_("Place variable addresses in the regular TOC")},\ 291 {"hard-float", - MASK_SOFT_FLOAT, \ 292 N_("Use hardware fp")}, \ 293 {"soft-float", MASK_SOFT_FLOAT, \ 294 N_("Do not use hardware fp")}, \ 295 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \ 296 N_("Generate load/store multiple instructions")}, \ 297 {"no-multiple", - MASK_MULTIPLE, \ 298 N_("Do not generate load/store multiple instructions")},\ 299 {"no-multiple", MASK_MULTIPLE_SET, \ 300 ""}, \ 301 {"string", MASK_STRING | MASK_STRING_SET, \ 302 N_("Generate string instructions for block moves")},\ 303 {"no-string", - MASK_STRING, \ 304 N_("Do not generate string instructions for block moves")},\ 305 {"no-string", MASK_STRING_SET, \ 306 ""}, \ 307 {"update", - MASK_NO_UPDATE, \ 308 N_("Generate load/store with update instructions")},\ 309 {"no-update", MASK_NO_UPDATE, \ 310 N_("Do not generate load/store with update instructions")},\ 311 {"fused-madd", - MASK_NO_FUSED_MADD, \ 312 N_("Generate fused multiply/add instructions")},\ 313 {"no-fused-madd", MASK_NO_FUSED_MADD, \ 314 N_("Don't generate fused multiply/add instructions")},\ 315 {"sched-prolog", MASK_SCHED_PROLOG, \ 316 ""}, \ 317 {"no-sched-prolog", -MASK_SCHED_PROLOG, \ 318 N_("Don't schedule the start and end of the procedure")},\ 319 {"sched-epilog", MASK_SCHED_PROLOG, \ 320 ""}, \ 321 {"no-sched-epilog", -MASK_SCHED_PROLOG, \ 322 ""}, \ 323 {"aix-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET, \ 324 N_("Return all structures in memory (AIX default)")},\ 325 {"svr4-struct-return", - MASK_AIX_STRUCT_RET,\ 326 N_("Return small structures in registers (SVR4 default)")},\ 327 {"svr4-struct-return",MASK_AIX_STRUCT_RET_SET,\ 328 ""},\ 329 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,\ 330 ""},\ 331 {"no-aix-struct-return", MASK_AIX_STRUCT_RET_SET,\ 332 ""},\ 333 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET,\ 334 ""},\ 335 SUBTARGET_SWITCHES \ 336 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \ 337 ""}} 338 339 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) 340 341 /* This is meant to be redefined in the host dependent files */ 342 #define SUBTARGET_SWITCHES 343 344 /* Processor type. Order must match cpu attribute in MD file. */ 345 enum processor_type 346 { 347 PROCESSOR_RIOS1, 348 PROCESSOR_RIOS2, 349 PROCESSOR_RS64A, 350 PROCESSOR_MPCCORE, 351 PROCESSOR_PPC403, 352 PROCESSOR_PPC405, 353 PROCESSOR_PPC601, 354 PROCESSOR_PPC603, 355 PROCESSOR_PPC604, 356 PROCESSOR_PPC604e, 357 PROCESSOR_PPC620, 358 PROCESSOR_PPC630, 359 PROCESSOR_PPC750, 360 PROCESSOR_PPC7400, 361 PROCESSOR_PPC7450, 362 PROCESSOR_PPC8540, 363 PROCESSOR_POWER4 364 }; 365 366 extern enum processor_type rs6000_cpu; 367 368 /* Recast the processor type to the cpu attribute. */ 369 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 370 371 /* Define generic processor types based upon current deployment. */ 372 #define PROCESSOR_COMMON PROCESSOR_PPC601 373 #define PROCESSOR_POWER PROCESSOR_RIOS1 374 #define PROCESSOR_POWERPC PROCESSOR_PPC604 375 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 376 377 /* Define the default processor. This is overridden by other tm.h files. */ 378 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1 379 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 380 381 /* Specify the dialect of assembler to use. New mnemonics is dialect one 382 and the old mnemonics are dialect zero. */ 383 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) 384 385 /* This is meant to be overridden in target specific files. */ 386 #define SUBTARGET_OPTIONS 387 388 #define TARGET_OPTIONS \ 389 { \ 390 {"cpu=", &rs6000_select[1].string, \ 391 N_("Use features of and schedule code for given CPU") }, \ 392 {"tune=", &rs6000_select[2].string, \ 393 N_("Schedule code for given CPU") }, \ 394 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \ 395 {"traceback=", &rs6000_traceback_name, \ 396 N_("Select full, part, or no traceback table") }, \ 397 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \ 398 {"long-double-", &rs6000_long_double_size_string, \ 399 N_("Specify size of long double (64 or 128 bits)") }, \ 400 {"isel=", &rs6000_isel_string, \ 401 N_("Specify yes/no if isel instructions should be generated") }, \ 402 {"vrsave=", &rs6000_altivec_vrsave_string, \ 403 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \ 404 {"longcall", &rs6000_longcall_switch, \ 405 N_("Avoid all range limits on call instructions") }, \ 406 {"no-longcall", &rs6000_longcall_switch, "" }, \ 407 SUBTARGET_OPTIONS \ 408 } 409 410 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ 411 struct rs6000_cpu_select 412 { 413 const char *string; 414 const char *name; 415 int set_tune_p; 416 int set_arch_p; 417 }; 418 419 extern struct rs6000_cpu_select rs6000_select[]; 420 421 /* Debug support */ 422 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ 423 extern const char *rs6000_abi_string; /* for -mabi={sysv,darwin,eabi,aix,altivec} */ 424 extern int rs6000_debug_stack; /* debug stack applications */ 425 extern int rs6000_debug_arg; /* debug argument handling */ 426 427 #define TARGET_DEBUG_STACK rs6000_debug_stack 428 #define TARGET_DEBUG_ARG rs6000_debug_arg 429 430 extern const char *rs6000_traceback_name; /* Type of traceback table. */ 431 432 /* These are separate from target_flags because we've run out of bits 433 there. */ 434 extern const char *rs6000_long_double_size_string; 435 extern int rs6000_long_double_type_size; 436 extern int rs6000_altivec_abi; 437 extern int rs6000_spe_abi; 438 extern int rs6000_isel; 439 extern int rs6000_fprs; 440 extern const char *rs6000_isel_string; 441 extern const char *rs6000_altivec_vrsave_string; 442 extern int rs6000_altivec_vrsave; 443 extern const char *rs6000_longcall_switch; 444 extern int rs6000_default_long_calls; 445 446 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 447 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 448 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave 449 450 #define TARGET_SPE_ABI 0 451 #define TARGET_SPE 0 452 #define TARGET_ISEL 0 453 #define TARGET_FPRS 1 454 455 /* Sometimes certain combinations of command options do not make sense 456 on a particular target machine. You can define a macro 457 `OVERRIDE_OPTIONS' to take account of this. This macro, if 458 defined, is executed once just after all the command options have 459 been parsed. 460 461 Don't use this macro to turn on various extra optimizations for 462 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. 463 464 On the RS/6000 this is used to define the target cpu type. */ 465 466 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) 467 468 /* Define this to change the optimizations performed by default. */ 469 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) 470 471 /* Show we can debug even without a frame pointer. */ 472 #define CAN_DEBUG_WITHOUT_FP 473 474 /* Target pragma. */ 475 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \ 476 cpp_register_pragma (PFILE, 0, "longcall", rs6000_pragma_longcall); \ 477 } while (0) 478 479 /* Target #defines. */ 480 #define TARGET_CPU_CPP_BUILTINS() \ 481 rs6000_cpu_cpp_builtins (pfile) 482 483 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 484 we're compiling for. Some configurations may need to override it. */ 485 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 486 do \ 487 { \ 488 if (BYTES_BIG_ENDIAN) \ 489 { \ 490 builtin_define ("__BIG_ENDIAN__"); \ 491 builtin_define ("_BIG_ENDIAN"); \ 492 builtin_assert ("machine=bigendian"); \ 493 } \ 494 else \ 495 { \ 496 builtin_define ("__LITTLE_ENDIAN__"); \ 497 builtin_define ("_LITTLE_ENDIAN"); \ 498 builtin_assert ("machine=littleendian"); \ 499 } \ 500 } \ 501 while (0) 502 503 /* Target machine storage layout. */ 504 505 /* Define this macro if it is advisable to hold scalars in registers 506 in a wider mode than that declared by the program. In such cases, 507 the value is constrained to be within the bounds of the declared 508 type, but kept valid in the wider mode. The signedness of the 509 extension may differ from that of the type. */ 510 511 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 512 if (GET_MODE_CLASS (MODE) == MODE_INT \ 513 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 514 (MODE) = word_mode; 515 516 /* Define this if function arguments should also be promoted using the above 517 procedure. */ 518 519 #define PROMOTE_FUNCTION_ARGS 520 521 /* Likewise, if the function return value is promoted. */ 522 523 #define PROMOTE_FUNCTION_RETURN 524 525 /* Define this if most significant bit is lowest numbered 526 in instructions that operate on numbered bit-fields. */ 527 /* That is true on RS/6000. */ 528 #define BITS_BIG_ENDIAN 1 529 530 /* Define this if most significant byte of a word is the lowest numbered. */ 531 /* That is true on RS/6000. */ 532 #define BYTES_BIG_ENDIAN 1 533 534 /* Define this if most significant word of a multiword number is lowest 535 numbered. 536 537 For RS/6000 we can decide arbitrarily since there are no machine 538 instructions for them. Might as well be consistent with bits and bytes. */ 539 #define WORDS_BIG_ENDIAN 1 540 541 #define MAX_BITS_PER_WORD 64 542 543 /* Width of a word, in units (bytes). */ 544 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 545 #ifdef IN_LIBGCC2 546 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 547 #else 548 #define MIN_UNITS_PER_WORD 4 549 #endif 550 #define UNITS_PER_FP_WORD 8 551 #define UNITS_PER_ALTIVEC_WORD 16 552 #define UNITS_PER_SPE_WORD 8 553 554 /* Type used for ptrdiff_t, as a string used in a declaration. */ 555 #define PTRDIFF_TYPE "int" 556 557 /* Type used for size_t, as a string used in a declaration. */ 558 #define SIZE_TYPE "long unsigned int" 559 560 /* Type used for wchar_t, as a string used in a declaration. */ 561 #define WCHAR_TYPE "short unsigned int" 562 563 /* Width of wchar_t in bits. */ 564 #define WCHAR_TYPE_SIZE 16 565 566 /* A C expression for the size in bits of the type `short' on the 567 target machine. If you don't define this, the default is half a 568 word. (If this would be less than one storage unit, it is 569 rounded up to one unit.) */ 570 #define SHORT_TYPE_SIZE 16 571 572 /* A C expression for the size in bits of the type `int' on the 573 target machine. If you don't define this, the default is one 574 word. */ 575 #define INT_TYPE_SIZE 32 576 577 /* A C expression for the size in bits of the type `long' on the 578 target machine. If you don't define this, the default is one 579 word. */ 580 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 581 #define MAX_LONG_TYPE_SIZE 64 582 583 /* A C expression for the size in bits of the type `long long' on the 584 target machine. If you don't define this, the default is two 585 words. */ 586 #define LONG_LONG_TYPE_SIZE 64 587 588 /* A C expression for the size in bits of the type `float' on the 589 target machine. If you don't define this, the default is one 590 word. */ 591 #define FLOAT_TYPE_SIZE 32 592 593 /* A C expression for the size in bits of the type `double' on the 594 target machine. If you don't define this, the default is two 595 words. */ 596 #define DOUBLE_TYPE_SIZE 64 597 598 /* A C expression for the size in bits of the type `long double' on 599 the target machine. If you don't define this, the default is two 600 words. */ 601 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 602 603 /* Constant which presents upper bound of the above value. */ 604 #define MAX_LONG_DOUBLE_TYPE_SIZE 128 605 606 /* Define this to set long double type size to use in libgcc2.c, which can 607 not depend on target_flags. */ 608 #ifdef __LONG_DOUBLE_128__ 609 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 610 #else 611 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 612 #endif 613 614 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 615 #define WIDEST_HARDWARE_FP_SIZE 64 616 617 /* Width in bits of a pointer. 618 See also the macro `Pmode' defined below. */ 619 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64) 620 621 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 622 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 623 624 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 625 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128) 626 627 /* Allocation boundary (in *bits*) for the code of a function. */ 628 #define FUNCTION_BOUNDARY 32 629 630 /* No data type wants to be aligned rounder than this. */ 631 #define BIGGEST_ALIGNMENT 128 632 633 /* A C expression to compute the alignment for a variables in the 634 local store. TYPE is the data type, and ALIGN is the alignment 635 that the object would ordinarily have. */ 636 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 637 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ 638 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN) 639 640 /* Alignment of field after `int : 0' in a structure. */ 641 #define EMPTY_FIELD_BOUNDARY 32 642 643 /* Every structure's size must be a multiple of this. */ 644 #define STRUCTURE_SIZE_BOUNDARY 8 645 646 /* Return 1 if a structure or array containing FIELD should be 647 accessed using `BLKMODE'. 648 649 For the SPE, simd types are V2SI, and gcc can be tempted to put the 650 entire thing in a DI and use subregs to access the internals. 651 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the 652 back-end. Because a single GPR can hold a V2SI, but not a DI, the 653 best thing to do is set structs to BLKmode and avoid Severe Tire 654 Damage. */ 655 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ 656 (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) 657 658 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 659 #define PCC_BITFIELD_TYPE_MATTERS 1 660 661 /* Make strings word-aligned so strcpy from constants will be faster. 662 Make vector constants quadword aligned. */ 663 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 664 (TREE_CODE (EXP) == STRING_CST \ 665 && (ALIGN) < BITS_PER_WORD \ 666 ? BITS_PER_WORD \ 667 : (ALIGN)) 668 669 /* Make arrays of chars word-aligned for the same reasons. 670 Align vectors to 128 bits. */ 671 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 672 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ 673 : TREE_CODE (TYPE) == ARRAY_TYPE \ 674 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 675 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 676 677 /* Nonzero if move instructions will actually fail to work 678 when given unaligned data. */ 679 #define STRICT_ALIGNMENT 0 680 681 /* Define this macro to be the value 1 if unaligned accesses have a cost 682 many times greater than aligned accesses, for example if they are 683 emulated in a trap handler. */ 684 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 685 (STRICT_ALIGNMENT \ 686 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 687 || (MODE) == DImode) \ 688 && (ALIGN) < 32)) 689 690 /* Standard register usage. */ 691 692 /* Number of actual hardware registers. 693 The hardware registers are assigned numbers for the compiler 694 from 0 to just below FIRST_PSEUDO_REGISTER. 695 All registers that the compiler knows about must be given numbers, 696 even those that are not normally considered general registers. 697 698 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 699 an MQ register, a count register, a link register, and 8 condition 700 register fields, which we view here as separate registers. 701 702 In addition, the difference between the frame and argument pointers is 703 a function of the number of registers saved, so we need to have a 704 register for AP that will later be eliminated in favor of SP or FP. 705 This is a normal register, but it is fixed. 706 707 We also create a pseudo register for float/int conversions, that will 708 really represent the memory location used. It is represented here as 709 a register, in order to work around problems in allocating stack storage 710 in inline functions. */ 711 712 #define FIRST_PSEUDO_REGISTER 113 713 714 /* This must be included for pre gcc 3.0 glibc compatibility. */ 715 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 716 717 /* 1 for registers that have pervasive standard uses 718 and are not available for the register allocator. 719 720 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 721 as a local register; for all other OS's r2 is the TOC pointer. 722 723 cr5 is not supposed to be used. 724 725 On System V implementations, r13 is fixed and not available for use. */ 726 727 #define FIXED_REGISTERS \ 728 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 729 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 730 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 731 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 732 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ 733 /* AltiVec registers. */ \ 734 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 735 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 736 1, 1 \ 737 , 1, 1 \ 738 } 739 740 /* 1 for registers not available across function calls. 741 These must include the FIXED_REGISTERS and also any 742 registers that can be used without being saved. 743 The latter must include the registers where values are returned 744 and the register where structure-value addresses are passed. 745 Aside from that, you can include as many other registers as you like. */ 746 747 #define CALL_USED_REGISTERS \ 748 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 749 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 750 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 751 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 752 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 753 /* AltiVec registers. */ \ 754 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 755 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 756 1, 1 \ 757 , 1, 1 \ 758 } 759 760 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 761 the entire set of `FIXED_REGISTERS' be included. 762 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 763 This macro is optional. If not specified, it defaults to the value 764 of `CALL_USED_REGISTERS'. */ 765 766 #define CALL_REALLY_USED_REGISTERS \ 767 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 769 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 770 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 771 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 772 /* AltiVec registers. */ \ 773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 774 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 775 0, 0 \ 776 , 0, 0 \ 777 } 778 779 #define MQ_REGNO 64 780 #define CR0_REGNO 68 781 #define CR1_REGNO 69 782 #define CR2_REGNO 70 783 #define CR3_REGNO 71 784 #define CR4_REGNO 72 785 #define MAX_CR_REGNO 75 786 #define XER_REGNO 76 787 #define FIRST_ALTIVEC_REGNO 77 788 #define LAST_ALTIVEC_REGNO 108 789 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 790 #define VRSAVE_REGNO 109 791 #define VSCR_REGNO 110 792 #define SPE_ACC_REGNO 111 793 #define SPEFSCR_REGNO 112 794 795 /* List the order in which to allocate registers. Each register must be 796 listed once, even those in FIXED_REGISTERS. 797 798 We allocate in the following order: 799 fp0 (not saved or used for anything) 800 fp13 - fp2 (not saved; incoming fp arg registers) 801 fp1 (not saved; return value) 802 fp31 - fp14 (saved; order given to save least number) 803 cr7, cr6 (not saved or special) 804 cr1 (not saved, but used for FP operations) 805 cr0 (not saved, but used for arithmetic operations) 806 cr4, cr3, cr2 (saved) 807 r0 (not saved; cannot be base reg) 808 r9 (not saved; best for TImode) 809 r11, r10, r8-r4 (not saved; highest used first to make less conflict) 810 r3 (not saved; return value register) 811 r31 - r13 (saved; order given to save least number) 812 r12 (not saved; if used for DImode or DFmode would use r13) 813 mq (not saved; best to use it if we can) 814 ctr (not saved; when we have the choice ctr is better) 815 lr (saved) 816 cr5, r1, r2, ap, xer, vrsave, vscr (fixed) 817 spe_acc, spefscr (fixed) 818 819 AltiVec registers: 820 v0 - v1 (not saved or used for anything) 821 v13 - v3 (not saved; incoming vector arg registers) 822 v2 (not saved; incoming vector arg reg; return value) 823 v19 - v14 (not saved or used for anything) 824 v31 - v20 (saved; order given to save least number) 825 */ 826 827 828 #define REG_ALLOC_ORDER \ 829 {32, \ 830 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ 831 33, \ 832 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 833 50, 49, 48, 47, 46, \ 834 75, 74, 69, 68, 72, 71, 70, \ 835 0, \ 836 9, 11, 10, 8, 7, 6, 5, 4, \ 837 3, \ 838 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 839 18, 17, 16, 15, 14, 13, 12, \ 840 64, 66, 65, \ 841 73, 1, 2, 67, 76, \ 842 /* AltiVec registers. */ \ 843 77, 78, \ 844 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 845 79, \ 846 96, 95, 94, 93, 92, 91, \ 847 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \ 848 97, 109, 110 \ 849 , 111, 112 \ 850 } 851 852 /* True if register is floating-point. */ 853 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 854 855 /* True if register is a condition register. */ 856 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75) 857 858 /* True if register is a condition register, but not cr0. */ 859 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75) 860 861 /* True if register is an integer register. */ 862 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM) 863 864 /* SPE SIMD registers are just the GPRs. */ 865 #define SPE_SIMD_REGNO_P(N) ((N) <= 31) 866 867 /* True if register is the XER register. */ 868 #define XER_REGNO_P(N) ((N) == XER_REGNO) 869 870 /* True if register is an AltiVec register. */ 871 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 872 873 /* Return number of consecutive hard regs needed starting at reg REGNO 874 to hold something of mode MODE. 875 This is ordinarily the length in words of a value of mode MODE 876 but can be less for certain modes in special long registers. 877 878 For the SPE, GPRs are 64 bits but only 32 bits are visible in 879 scalar instructions. The upper 32 bits are only available to the 880 SIMD instructions. 881 882 POWER and PowerPC GPRs hold 32 bits worth; 883 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ 884 885 #define HARD_REGNO_NREGS(REGNO, MODE) \ 886 (FP_REGNO_P (REGNO) \ 887 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ 888 : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ 889 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \ 890 : ALTIVEC_REGNO_P (REGNO) \ 891 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \ 892 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 893 894 #define ALTIVEC_VECTOR_MODE(MODE) \ 895 ((MODE) == V16QImode \ 896 || (MODE) == V8HImode \ 897 || (MODE) == V4SFmode \ 898 || (MODE) == V4SImode) 899 900 #define SPE_VECTOR_MODE(MODE) \ 901 ((MODE) == V4HImode \ 902 || (MODE) == V2SFmode \ 903 || (MODE) == V1DImode \ 904 || (MODE) == V2SImode) 905 906 /* Define this macro to be nonzero if the port is prepared to handle 907 insns involving vector mode MODE. At the very least, it must have 908 move patterns for this mode. */ 909 910 #define VECTOR_MODE_SUPPORTED_P(MODE) \ 911 ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ 912 || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))) 913 914 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 915 For POWER and PowerPC, the GPRs can hold any mode, but the float 916 registers only can hold floating modes and DImode, and CR register only 917 can hold CC modes. We cannot put TImode anywhere except general 918 register and it must be able to fit within the register set. */ 919 920 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 921 (FP_REGNO_P (REGNO) ? \ 922 (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 923 || (GET_MODE_CLASS (MODE) == MODE_INT \ 924 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \ 925 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \ 926 : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \ 927 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \ 928 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \ 929 : ! INT_REGNO_P (REGNO) ? GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ 930 : 1) 931 932 /* Value is 1 if it is a good idea to tie two pseudo registers 933 when one has mode MODE1 and one has mode MODE2. 934 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 935 for any hard reg, then this must be 0 for correct output. */ 936 #define MODES_TIEABLE_P(MODE1, MODE2) \ 937 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 938 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 939 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 940 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 941 : GET_MODE_CLASS (MODE1) == MODE_CC \ 942 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 943 : GET_MODE_CLASS (MODE2) == MODE_CC \ 944 ? GET_MODE_CLASS (MODE1) == MODE_CC \ 945 : ALTIVEC_VECTOR_MODE (MODE1) \ 946 ? ALTIVEC_VECTOR_MODE (MODE2) \ 947 : ALTIVEC_VECTOR_MODE (MODE2) \ 948 ? ALTIVEC_VECTOR_MODE (MODE1) \ 949 : 1) 950 951 /* A C expression returning the cost of moving data from a register of class 952 CLASS1 to one of CLASS2. */ 953 954 #define REGISTER_MOVE_COST rs6000_register_move_cost 955 956 /* A C expressions returning the cost of moving data of MODE from a register to 957 or from memory. */ 958 959 #define MEMORY_MOVE_COST rs6000_memory_move_cost 960 961 /* Specify the cost of a branch insn; roughly the number of extra insns that 962 should be added to avoid a branch. 963 964 Set this to 3 on the RS/6000 since that is roughly the average cost of an 965 unscheduled conditional branch. */ 966 967 #define BRANCH_COST 3 968 969 970 /* A fixed register used at prologue and epilogue generation to fix 971 addressing modes. The SPE needs heavy addressing fixes at the last 972 minute, and it's best to save a register for it. 973 974 AltiVec also needs fixes, but we've gotten around using r11, which 975 is actually wrong because when use_backchain_to_restore_sp is true, 976 we end up clobbering r11. 977 978 The AltiVec case needs to be fixed. Dunno if we should break ABI 979 compatability and reserve a register for it as well.. */ 980 981 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) 982 983 /* Define this macro to change register usage conditional on target flags. 984 Set MQ register fixed (already call_used) if not POWER architecture 985 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. 986 64-bit AIX reserves GPR13 for thread-private data. 987 Conditionally disable FPRs. */ 988 989 #define CONDITIONAL_REGISTER_USAGE \ 990 { \ 991 int i; \ 992 if (! TARGET_POWER) \ 993 fixed_regs[64] = 1; \ 994 if (TARGET_64BIT) \ 995 fixed_regs[13] = call_used_regs[13] \ 996 = call_really_used_regs[13] = 1; \ 997 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \ 998 for (i = 32; i < 64; i++) \ 999 fixed_regs[i] = call_used_regs[i] \ 1000 = call_really_used_regs[i] = 1; \ 1001 if (DEFAULT_ABI == ABI_V4 \ 1002 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ 1003 && flag_pic == 2) \ 1004 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ 1005 if (DEFAULT_ABI == ABI_V4 \ 1006 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ 1007 && flag_pic == 1) \ 1008 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1009 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1010 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ 1011 if (DEFAULT_ABI == ABI_DARWIN \ 1012 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 1013 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1014 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1015 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ 1016 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ 1017 if (TARGET_ALTIVEC) \ 1018 global_regs[VSCR_REGNO] = 1; \ 1019 if (TARGET_SPE) \ 1020 { \ 1021 global_regs[SPEFSCR_REGNO] = 1; \ 1022 fixed_regs[FIXED_SCRATCH] \ 1023 = call_used_regs[FIXED_SCRATCH] \ 1024 = call_really_used_regs[FIXED_SCRATCH] = 1; \ 1025 } \ 1026 if (! TARGET_ALTIVEC) \ 1027 { \ 1028 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \ 1029 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \ 1030 call_really_used_regs[VRSAVE_REGNO] = 1; \ 1031 } \ 1032 if (TARGET_ALTIVEC_ABI) \ 1033 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \ 1034 call_used_regs[i] = call_really_used_regs[i] = 1; \ 1035 } 1036 1037 /* Specify the registers used for certain standard purposes. 1038 The values of these macros are register numbers. */ 1039 1040 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1041 /* #define PC_REGNUM */ 1042 1043 /* Register to use for pushing function arguments. */ 1044 #define STACK_POINTER_REGNUM 1 1045 1046 /* Base register for access to local variables of the function. */ 1047 #define FRAME_POINTER_REGNUM 31 1048 1049 /* Value should be nonzero if functions must have frame pointers. 1050 Zero means the frame pointer need not be set up (and parms 1051 may be accessed via the stack pointer) in functions that seem suitable. 1052 This is computed in `reload', in reload1.c. */ 1053 #define FRAME_POINTER_REQUIRED 0 1054 1055 /* Base register for access to arguments of the function. */ 1056 #define ARG_POINTER_REGNUM 67 1057 1058 /* Place to put static chain when calling a function that requires it. */ 1059 #define STATIC_CHAIN_REGNUM 11 1060 1061 /* Link register number. */ 1062 #define LINK_REGISTER_REGNUM 65 1063 1064 /* Count register number. */ 1065 #define COUNT_REGISTER_REGNUM 66 1066 1067 /* Place that structure value return address is placed. 1068 1069 On the RS/6000, it is passed as an extra parameter. */ 1070 #define STRUCT_VALUE 0 1071 1072 /* Define the classes of registers for register constraints in the 1073 machine description. Also define ranges of constants. 1074 1075 One of the classes must always be named ALL_REGS and include all hard regs. 1076 If there is more than one class, another class must be named NO_REGS 1077 and contain no registers. 1078 1079 The name GENERAL_REGS must be the name of a class (or an alias for 1080 another name such as ALL_REGS). This is the class of registers 1081 that is allowed by "g" or "r" in a register constraint. 1082 Also, registers outside this class are allocated only when 1083 instructions express preferences for them. 1084 1085 The classes must be numbered in nondecreasing order; that is, 1086 a larger-numbered class must never be contained completely 1087 in a smaller-numbered class. 1088 1089 For any two classes, it is very desirable that there be another 1090 class that represents their union. */ 1091 1092 /* The RS/6000 has three types of registers, fixed-point, floating-point, 1093 and condition registers, plus three special registers, MQ, CTR, and the 1094 link register. 1095 1096 However, r0 is special in that it cannot be used as a base register. 1097 So make a class for registers valid as base registers. 1098 1099 Also, cr0 is the only condition code register that can be used in 1100 arithmetic insns, so make a separate class for it. */ 1101 1102 enum reg_class 1103 { 1104 NO_REGS, 1105 BASE_REGS, 1106 GENERAL_REGS, 1107 FLOAT_REGS, 1108 ALTIVEC_REGS, 1109 VRSAVE_REGS, 1110 VSCR_REGS, 1111 SPE_ACC_REGS, 1112 SPEFSCR_REGS, 1113 NON_SPECIAL_REGS, 1114 MQ_REGS, 1115 LINK_REGS, 1116 CTR_REGS, 1117 LINK_OR_CTR_REGS, 1118 SPECIAL_REGS, 1119 SPEC_OR_GEN_REGS, 1120 CR0_REGS, 1121 CR_REGS, 1122 NON_FLOAT_REGS, 1123 XER_REGS, 1124 ALL_REGS, 1125 LIM_REG_CLASSES 1126 }; 1127 1128 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1129 1130 /* Give names of register classes as strings for dump file. */ 1131 1132 #define REG_CLASS_NAMES \ 1133 { \ 1134 "NO_REGS", \ 1135 "BASE_REGS", \ 1136 "GENERAL_REGS", \ 1137 "FLOAT_REGS", \ 1138 "ALTIVEC_REGS", \ 1139 "VRSAVE_REGS", \ 1140 "VSCR_REGS", \ 1141 "SPE_ACC_REGS", \ 1142 "SPEFSCR_REGS", \ 1143 "NON_SPECIAL_REGS", \ 1144 "MQ_REGS", \ 1145 "LINK_REGS", \ 1146 "CTR_REGS", \ 1147 "LINK_OR_CTR_REGS", \ 1148 "SPECIAL_REGS", \ 1149 "SPEC_OR_GEN_REGS", \ 1150 "CR0_REGS", \ 1151 "CR_REGS", \ 1152 "NON_FLOAT_REGS", \ 1153 "XER_REGS", \ 1154 "ALL_REGS" \ 1155 } 1156 1157 /* Define which registers fit in which classes. 1158 This is an initializer for a vector of HARD_REG_SET 1159 of length N_REG_CLASSES. */ 1160 1161 #define REG_CLASS_CONTENTS \ 1162 { \ 1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1164 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \ 1165 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \ 1166 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ 1167 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ 1168 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ 1169 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ 1170 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ 1171 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ 1172 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \ 1173 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ 1174 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ 1175 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ 1176 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ 1177 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ 1178 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \ 1179 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ 1180 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ 1181 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \ 1182 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ 1183 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \ 1184 } 1185 1186 /* The same information, inverted: 1187 Return the class number of the smallest class containing 1188 reg number REGNO. This could be a conditional expression 1189 or could index an array. */ 1190 1191 #define REGNO_REG_CLASS(REGNO) \ 1192 ((REGNO) == 0 ? GENERAL_REGS \ 1193 : (REGNO) < 32 ? BASE_REGS \ 1194 : FP_REGNO_P (REGNO) ? FLOAT_REGS \ 1195 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \ 1196 : (REGNO) == CR0_REGNO ? CR0_REGS \ 1197 : CR_REGNO_P (REGNO) ? CR_REGS \ 1198 : (REGNO) == MQ_REGNO ? MQ_REGS \ 1199 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \ 1200 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \ 1201 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ 1202 : (REGNO) == XER_REGNO ? XER_REGS \ 1203 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \ 1204 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \ 1205 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \ 1206 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \ 1207 : NO_REGS) 1208 1209 /* The class value for index registers, and the one for base regs. */ 1210 #define INDEX_REG_CLASS GENERAL_REGS 1211 #define BASE_REG_CLASS BASE_REGS 1212 1213 /* Get reg_class from a letter such as appears in the machine description. */ 1214 1215 #define REG_CLASS_FROM_LETTER(C) \ 1216 ((C) == 'f' ? FLOAT_REGS \ 1217 : (C) == 'b' ? BASE_REGS \ 1218 : (C) == 'h' ? SPECIAL_REGS \ 1219 : (C) == 'q' ? MQ_REGS \ 1220 : (C) == 'c' ? CTR_REGS \ 1221 : (C) == 'l' ? LINK_REGS \ 1222 : (C) == 'v' ? ALTIVEC_REGS \ 1223 : (C) == 'x' ? CR0_REGS \ 1224 : (C) == 'y' ? CR_REGS \ 1225 : (C) == 'z' ? XER_REGS \ 1226 : NO_REGS) 1227 1228 /* The letters I, J, K, L, M, N, and P in a register constraint string 1229 can be used to stand for particular ranges of immediate operands. 1230 This macro defines what the ranges are. 1231 C is the letter, and VALUE is a constant value. 1232 Return 1 if VALUE is in the range specified by C. 1233 1234 `I' is a signed 16-bit constant 1235 `J' is a constant with only the high-order 16 bits nonzero 1236 `K' is a constant with only the low-order 16 bits nonzero 1237 `L' is a signed 16-bit constant shifted left 16 bits 1238 `M' is a constant that is greater than 31 1239 `N' is a positive constant that is an exact power of two 1240 `O' is the constant zero 1241 `P' is a constant whose negation is a signed 16-bit constant */ 1242 1243 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1244 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \ 1245 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \ 1246 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \ 1247 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \ 1248 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \ 1249 : (C) == 'M' ? (VALUE) > 31 \ 1250 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \ 1251 : (C) == 'O' ? (VALUE) == 0 \ 1252 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \ 1253 : 0) 1254 1255 /* Similar, but for floating constants, and defining letters G and H. 1256 Here VALUE is the CONST_DOUBLE rtx itself. 1257 1258 We flag for special constants when we can copy the constant into 1259 a general register in two insns for DF/DI and one insn for SF. 1260 1261 'H' is used for DI/DF constants that take 3 insns. */ 1262 1263 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1264 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \ 1265 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \ 1266 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \ 1267 : 0) 1268 1269 /* Optional extra constraints for this machine. 1270 1271 'Q' means that is a memory operand that is just an offset from a reg. 1272 'R' is for AIX TOC entries. 1273 'S' is a constant that can be placed into a 64-bit mask operand 1274 'T' is a constant that can be placed into a 32-bit mask operand 1275 'U' is for V.4 small data references. 1276 't' is for AND masks that can be performed by two rldic{l,r} insns. */ 1277 1278 #define EXTRA_CONSTRAINT(OP, C) \ 1279 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ 1280 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \ 1281 : (C) == 'S' ? mask64_operand (OP, DImode) \ 1282 : (C) == 'T' ? mask_operand (OP, SImode) \ 1283 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \ 1284 && small_data_operand (OP, GET_MODE (OP))) \ 1285 : (C) == 't' ? (mask64_2_operand (OP, DImode) \ 1286 && (fixed_regs[CR0_REGNO] \ 1287 || !logical_operand (OP, DImode)) \ 1288 && !mask64_operand (OP, DImode)) \ 1289 : 0) 1290 1291 /* Given an rtx X being reloaded into a reg required to be 1292 in class CLASS, return the class of reg to actually use. 1293 In general this is just CLASS; but on some machines 1294 in some cases it is preferable to use a more restrictive class. 1295 1296 On the RS/6000, we have to return NO_REGS when we want to reload a 1297 floating-point CONST_DOUBLE to force it to be copied to memory. 1298 1299 We also don't want to reload integer values into floating-point 1300 registers if we can at all help it. In fact, this can 1301 cause reload to abort, if it tries to generate a reload of CTR 1302 into a FP register and discovers it doesn't have the memory location 1303 required. 1304 1305 ??? Would it be a good idea to have reload do the converse, that is 1306 try to reload floating modes into FP registers if possible? 1307 */ 1308 1309 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1310 (((GET_CODE (X) == CONST_DOUBLE \ 1311 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ 1312 ? NO_REGS \ 1313 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \ 1314 && (CLASS) == NON_SPECIAL_REGS) \ 1315 ? GENERAL_REGS \ 1316 : (CLASS))) 1317 1318 /* Return the register class of a scratch register needed to copy IN into 1319 or out of a register in CLASS in MODE. If it can be done directly, 1320 NO_REGS is returned. */ 1321 1322 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1323 secondary_reload_class (CLASS, MODE, IN) 1324 1325 /* If we are copying between FP or AltiVec registers and anything 1326 else, we need a memory location. */ 1327 1328 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1329 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \ 1330 || (CLASS2) == FLOAT_REGS \ 1331 || (CLASS1) == ALTIVEC_REGS \ 1332 || (CLASS2) == ALTIVEC_REGS)) 1333 1334 /* Return the maximum number of consecutive registers 1335 needed to represent mode MODE in a register of class CLASS. 1336 1337 On RS/6000, this is the size of MODE in words, 1338 except in the FP regs, where a single reg is enough for two words. */ 1339 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1340 (((CLASS) == FLOAT_REGS) \ 1341 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ 1342 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1343 1344 1345 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1346 1347 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1348 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1349 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \ 1350 : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 \ 1351 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \ 1352 : 0) 1353 1354 /* Stack layout; function entry, exit and calling. */ 1355 1356 /* Enumeration to give which calling sequence to use. */ 1357 enum rs6000_abi { 1358 ABI_NONE, 1359 ABI_AIX, /* IBM's AIX */ 1360 ABI_AIX_NODESC, /* AIX calling sequence minus 1361 function descriptors */ 1362 ABI_V4, /* System V.4/eabi */ 1363 ABI_DARWIN /* Apple's Darwin (OS X kernel) */ 1364 }; 1365 1366 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ 1367 1368 /* Structure used to define the rs6000 stack */ 1369 typedef struct rs6000_stack { 1370 int first_gp_reg_save; /* first callee saved GP register used */ 1371 int first_fp_reg_save; /* first callee saved FP register used */ 1372 int first_altivec_reg_save; /* first callee saved AltiVec register used */ 1373 int lr_save_p; /* true if the link reg needs to be saved */ 1374 int cr_save_p; /* true if the CR reg needs to be saved */ 1375 unsigned int vrsave_mask; /* mask of vec registers to save */ 1376 int toc_save_p; /* true if the TOC needs to be saved */ 1377 int push_p; /* true if we need to allocate stack space */ 1378 int calls_p; /* true if the function makes any calls */ 1379 enum rs6000_abi abi; /* which ABI to use */ 1380 int gp_save_offset; /* offset to save GP regs from initial SP */ 1381 int fp_save_offset; /* offset to save FP regs from initial SP */ 1382 int altivec_save_offset; /* offset to save AltiVec regs from inital SP */ 1383 int lr_save_offset; /* offset to save LR from initial SP */ 1384 int cr_save_offset; /* offset to save CR from initial SP */ 1385 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ 1386 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ 1387 int toc_save_offset; /* offset to save the TOC pointer */ 1388 int varargs_save_offset; /* offset to save the varargs registers */ 1389 int ehrd_offset; /* offset to EH return data */ 1390 int reg_size; /* register size (4 or 8) */ 1391 int varargs_size; /* size to hold V.4 args passed in regs */ 1392 int vars_size; /* variable save area size */ 1393 int parm_size; /* outgoing parameter size */ 1394 int save_size; /* save area size */ 1395 int fixed_size; /* fixed size of stack frame */ 1396 int gp_size; /* size of saved GP registers */ 1397 int fp_size; /* size of saved FP registers */ 1398 int altivec_size; /* size of saved AltiVec registers */ 1399 int cr_size; /* size to hold CR if not in save_size */ 1400 int lr_size; /* size to hold LR if not in save_size */ 1401 int vrsave_size; /* size to hold VRSAVE if not in save_size */ 1402 int altivec_padding_size; /* size of altivec alignment padding if 1403 not in save_size */ 1404 int spe_gp_size; /* size of 64-bit GPR save size for SPE */ 1405 int spe_padding_size; 1406 int toc_size; /* size to hold TOC if not in save_size */ 1407 int total_size; /* total bytes allocated for stack */ 1408 } rs6000_stack_t; 1409 1410 /* Define this if pushing a word on the stack 1411 makes the stack pointer a smaller address. */ 1412 #define STACK_GROWS_DOWNWARD 1413 1414 /* Define this if the nominal address of the stack frame 1415 is at the high-address end of the local variables; 1416 that is, each additional local variable allocated 1417 goes at a more negative offset in the frame. 1418 1419 On the RS/6000, we grow upwards, from the area after the outgoing 1420 arguments. */ 1421 /* #define FRAME_GROWS_DOWNWARD */ 1422 1423 /* Size of the outgoing register save area */ 1424 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ 1425 || DEFAULT_ABI == ABI_AIX_NODESC \ 1426 || DEFAULT_ABI == ABI_DARWIN) \ 1427 ? (TARGET_64BIT ? 64 : 32) \ 1428 : 0) 1429 1430 /* Size of the fixed area on the stack */ 1431 #define RS6000_SAVE_AREA \ 1432 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ 1433 << (TARGET_64BIT ? 1 : 0)) 1434 1435 /* MEM representing address to save the TOC register */ 1436 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ 1437 plus_constant (stack_pointer_rtx, \ 1438 (TARGET_32BIT ? 20 : 40))) 1439 1440 /* Size of the V.4 varargs area if needed */ 1441 #define RS6000_VARARGS_AREA 0 1442 1443 /* Align an address */ 1444 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1445 1446 /* Size of V.4 varargs area in bytes */ 1447 #define RS6000_VARARGS_SIZE \ 1448 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8) 1449 1450 /* Offset within stack frame to start allocating local variables at. 1451 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1452 first local allocated. Otherwise, it is the offset to the BEGINNING 1453 of the first local allocated. 1454 1455 On the RS/6000, the frame pointer is the same as the stack pointer, 1456 except for dynamic allocations. So we start after the fixed area and 1457 outgoing parameter area. */ 1458 1459 #define STARTING_FRAME_OFFSET \ 1460 (RS6000_ALIGN (current_function_outgoing_args_size, \ 1461 TARGET_ALTIVEC ? 16 : 8) \ 1462 + RS6000_VARARGS_AREA \ 1463 + RS6000_SAVE_AREA) 1464 1465 /* Offset from the stack pointer register to an item dynamically 1466 allocated on the stack, e.g., by `alloca'. 1467 1468 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1469 length of the outgoing arguments. The default is correct for most 1470 machines. See `function.c' for details. */ 1471 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1472 (RS6000_ALIGN (current_function_outgoing_args_size, \ 1473 TARGET_ALTIVEC ? 16 : 8) \ 1474 + (STACK_POINTER_OFFSET)) 1475 1476 /* If we generate an insn to push BYTES bytes, 1477 this says how many the stack pointer really advances by. 1478 On RS/6000, don't define this because there are no push insns. */ 1479 /* #define PUSH_ROUNDING(BYTES) */ 1480 1481 /* Offset of first parameter from the argument pointer register value. 1482 On the RS/6000, we define the argument pointer to the start of the fixed 1483 area. */ 1484 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1485 1486 /* Offset from the argument pointer register value to the top of 1487 stack. This is different from FIRST_PARM_OFFSET because of the 1488 register save area. */ 1489 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1490 1491 /* Define this if stack space is still allocated for a parameter passed 1492 in a register. The value is the number of bytes allocated to this 1493 area. */ 1494 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE 1495 1496 /* Define this if the above stack space is to be considered part of the 1497 space allocated by the caller. */ 1498 #define OUTGOING_REG_PARM_STACK_SPACE 1499 1500 /* This is the difference between the logical top of stack and the actual sp. 1501 1502 For the RS/6000, sp points past the fixed area. */ 1503 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1504 1505 /* Define this if the maximum size of all the outgoing args is to be 1506 accumulated and pushed during the prologue. The amount can be 1507 found in the variable current_function_outgoing_args_size. */ 1508 #define ACCUMULATE_OUTGOING_ARGS 1 1509 1510 /* Value is the number of bytes of arguments automatically 1511 popped when returning from a subroutine call. 1512 FUNDECL is the declaration node of the function (as a tree), 1513 FUNTYPE is the data type of the function (as a tree), 1514 or for a library call it is an identifier node for the subroutine name. 1515 SIZE is the number of bytes of arguments passed on the stack. */ 1516 1517 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1518 1519 /* Define how to find the value returned by a function. 1520 VALTYPE is the data type of the value (as a tree). 1521 If the precise function being called is known, FUNC is its FUNCTION_DECL; 1522 otherwise, FUNC is 0. 1523 1524 On the SPE, both FPs and vectors are returned in r3. 1525 1526 On RS/6000 an integer value is in r3 and a floating-point value is in 1527 fp1, unless -msoft-float. */ 1528 1529 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1530 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ 1531 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ 1532 || POINTER_TYPE_P (VALTYPE) \ 1533 ? word_mode : TYPE_MODE (VALTYPE), \ 1534 TREE_CODE (VALTYPE) == VECTOR_TYPE \ 1535 && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \ 1536 : TREE_CODE (VALTYPE) == REAL_TYPE \ 1537 && TARGET_SPE_ABI && !TARGET_FPRS \ 1538 ? GP_ARG_RETURN \ 1539 : TREE_CODE (VALTYPE) == REAL_TYPE \ 1540 && TARGET_HARD_FLOAT && TARGET_FPRS \ 1541 ? FP_ARG_RETURN : GP_ARG_RETURN) 1542 1543 /* Define how to find the value returned by a library function 1544 assuming the value has mode MODE. */ 1545 1546 #define LIBCALL_VALUE(MODE) \ 1547 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \ 1548 : GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1549 && TARGET_HARD_FLOAT && TARGET_FPRS \ 1550 ? FP_ARG_RETURN : GP_ARG_RETURN) 1551 1552 /* The AIX ABI for the RS/6000 specifies that all structures are 1553 returned in memory. The Darwin ABI does the same. The SVR4 ABI 1554 specifies that structures <= 8 bytes are returned in r3/r4, but a 1555 draft put them in memory, and GCC used to implement the draft 1556 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET 1557 controls this instead of DEFAULT_ABI; V.4 targets needing backward 1558 compatibility can change DRAFT_V4_STRUCT_RET to override the 1559 default, and -m switches get the final word. See 1560 rs6000_override_options for more details. 1561 1562 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit 1563 long double support is enabled. These values are returned in memory. 1564 1565 int_size_in_bytes returns -1 for variable size objects, which go in 1566 memory always. The cast to unsigned makes -1 > 8. */ 1567 1568 #define RETURN_IN_MEMORY(TYPE) \ 1569 ((AGGREGATE_TYPE_P (TYPE) \ 1570 && (TARGET_AIX_STRUCT_RET \ 1571 || (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8)) \ 1572 || (DEFAULT_ABI == ABI_V4 && TYPE_MODE (TYPE) == TFmode)) 1573 1574 /* DRAFT_V4_STRUCT_RET defaults off. */ 1575 #define DRAFT_V4_STRUCT_RET 0 1576 1577 /* Let RETURN_IN_MEMORY control what happens. */ 1578 #define DEFAULT_PCC_STRUCT_RETURN 0 1579 1580 /* Mode of stack savearea. 1581 FUNCTION is VOIDmode because calling convention maintains SP. 1582 BLOCK needs Pmode for SP. 1583 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1584 #define STACK_SAVEAREA_MODE(LEVEL) \ 1585 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1586 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) 1587 1588 /* Minimum and maximum general purpose registers used to hold arguments. */ 1589 #define GP_ARG_MIN_REG 3 1590 #define GP_ARG_MAX_REG 10 1591 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1592 1593 /* Minimum and maximum floating point registers used to hold arguments. */ 1594 #define FP_ARG_MIN_REG 33 1595 #define FP_ARG_AIX_MAX_REG 45 1596 #define FP_ARG_V4_MAX_REG 40 1597 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ 1598 || DEFAULT_ABI == ABI_AIX_NODESC \ 1599 || DEFAULT_ABI == ABI_DARWIN) \ 1600 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) 1601 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1602 1603 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1604 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1605 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1606 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1607 1608 /* Return registers */ 1609 #define GP_ARG_RETURN GP_ARG_MIN_REG 1610 #define FP_ARG_RETURN FP_ARG_MIN_REG 1611 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1612 1613 /* Flags for the call/call_value rtl operations set up by function_arg */ 1614 #define CALL_NORMAL 0x00000000 /* no special processing */ 1615 /* Bits in 0x00000001 are unused. */ 1616 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1617 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1618 #define CALL_LONG 0x00000008 /* always call indirect */ 1619 #define CALL_LIBCALL 0x00000010 /* libcall */ 1620 1621 /* 1 if N is a possible register number for a function value 1622 as seen by the caller. 1623 1624 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1625 #define FUNCTION_VALUE_REGNO_P(N) \ 1626 ((N) == GP_ARG_RETURN \ 1627 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \ 1628 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC)) 1629 1630 /* 1 if N is a possible register number for function argument passing. 1631 On RS/6000, these are r3-r10 and fp1-fp13. 1632 On AltiVec, v2 - v13 are used for passing vectors. */ 1633 #define FUNCTION_ARG_REGNO_P(N) \ 1634 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1635 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1636 && TARGET_ALTIVEC) \ 1637 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1638 && TARGET_HARD_FLOAT)) 1639 1640 /* A C structure for machine-specific, per-function data. 1641 This is added to the cfun structure. */ 1642 typedef struct machine_function GTY(()) 1643 { 1644 /* Whether a System V.4 varargs area was created. */ 1645 int sysv_varargs_p; 1646 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ 1647 int ra_needs_full_frame; 1648 } machine_function; 1649 1650 /* Define a data type for recording info about an argument list 1651 during the scan of that argument list. This data type should 1652 hold all necessary information about the function itself 1653 and about the args processed so far, enough to enable macros 1654 such as FUNCTION_ARG to determine where the next arg should go. 1655 1656 On the RS/6000, this is a structure. The first element is the number of 1657 total argument words, the second is used to store the next 1658 floating-point register number, and the third says how many more args we 1659 have prototype types for. 1660 1661 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1662 the next availible GP register, `fregno' is the next available FP 1663 register, and `words' is the number of words used on the stack. 1664 1665 The varargs/stdarg support requires that this structure's size 1666 be a multiple of sizeof(int). */ 1667 1668 typedef struct rs6000_args 1669 { 1670 int words; /* # words used for passing GP registers */ 1671 int fregno; /* next available FP register */ 1672 int vregno; /* next available AltiVec register */ 1673 int nargs_prototype; /* # args left in the current prototype */ 1674 int orig_nargs; /* Original value of nargs_prototype */ 1675 int prototype; /* Whether a prototype was defined */ 1676 int call_cookie; /* Do special things for this call */ 1677 int sysv_gregno; /* next available GP register */ 1678 } CUMULATIVE_ARGS; 1679 1680 /* Define intermediate macro to compute the size (in registers) of an argument 1681 for the RS/6000. */ 1682 1683 #define RS6000_ARG_SIZE(MODE, TYPE) \ 1684 ((MODE) != BLKmode \ 1685 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ 1686 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 1687 1688 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1689 for a call to a function whose data type is FNTYPE. 1690 For a library call, FNTYPE is 0. */ 1691 1692 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ 1693 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE) 1694 1695 /* Similar, but when scanning the definition of a procedure. We always 1696 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1697 1698 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \ 1699 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE) 1700 1701 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1702 1703 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1704 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE) 1705 1706 /* Update the data in CUM to advance over an argument 1707 of mode MODE and data type TYPE. 1708 (TYPE is null for libcalls where that information may not be available.) */ 1709 1710 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1711 function_arg_advance (&CUM, MODE, TYPE, NAMED) 1712 1713 /* Nonzero if we can use a floating-point register to pass this arg. */ 1714 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ 1715 (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1716 && (CUM).fregno <= FP_ARG_MAX_REG \ 1717 && TARGET_HARD_FLOAT && TARGET_FPRS) 1718 1719 /* Nonzero if we can use an AltiVec register to pass this arg. */ 1720 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \ 1721 (ALTIVEC_VECTOR_MODE (MODE) \ 1722 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \ 1723 && TARGET_ALTIVEC_ABI) 1724 1725 /* Determine where to put an argument to a function. 1726 Value is zero to push the argument on the stack, 1727 or a hard register in which to store the argument. 1728 1729 MODE is the argument's machine mode. 1730 TYPE is the data type of the argument (as a tree). 1731 This is null for libcalls where that information may 1732 not be available. 1733 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1734 the preceding args and about the function being called. 1735 NAMED is nonzero if this argument is a named parameter 1736 (otherwise it is an extra parameter matching an ellipsis). 1737 1738 On RS/6000 the first eight words of non-FP are normally in registers 1739 and the rest are pushed. The first 13 FP args are in registers. 1740 1741 If this is floating-point and no prototype is specified, we use 1742 both an FP and integer register (or possibly FP reg and stack). Library 1743 functions (when TYPE is zero) always have the proper types for args, 1744 so we can pass the FP value just in one register. emit_library_function 1745 doesn't support EXPR_LIST anyway. */ 1746 1747 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1748 function_arg (&CUM, MODE, TYPE, NAMED) 1749 1750 /* For an arg passed partly in registers and partly in memory, 1751 this is the number of registers used. 1752 For args passed entirely in registers or entirely in memory, zero. */ 1753 1754 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1755 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) 1756 1757 /* A C expression that indicates when an argument must be passed by 1758 reference. If nonzero for an argument, a copy of that argument is 1759 made in memory and a pointer to the argument is passed instead of 1760 the argument itself. The pointer is passed in whatever way is 1761 appropriate for passing a pointer to that type. */ 1762 1763 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1764 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED) 1765 1766 /* If defined, a C expression which determines whether, and in which 1767 direction, to pad out an argument with extra space. The value 1768 should be of type `enum direction': either `upward' to pad above 1769 the argument, `downward' to pad below, or `none' to inhibit 1770 padding. */ 1771 1772 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1773 1774 /* If defined, a C expression that gives the alignment boundary, in bits, 1775 of an argument with the specified mode and type. If it is not defined, 1776 PARM_BOUNDARY is used for all arguments. */ 1777 1778 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1779 function_arg_boundary (MODE, TYPE) 1780 1781 /* Perform any needed actions needed for a function that is receiving a 1782 variable number of arguments. 1783 1784 CUM is as above. 1785 1786 MODE and TYPE are the mode and type of the current parameter. 1787 1788 PRETEND_SIZE is a variable that should be set to the amount of stack 1789 that must be pushed by the prolog to pretend that our caller pushed 1790 it. 1791 1792 Normally, this macro will push all remaining incoming registers on the 1793 stack and set PRETEND_SIZE to the length of the registers pushed. */ 1794 1795 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ 1796 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL) 1797 1798 /* Define the `__builtin_va_list' type for the ABI. */ 1799 #define BUILD_VA_LIST_TYPE(VALIST) \ 1800 (VALIST) = rs6000_build_va_list () 1801 1802 /* Implement `va_start' for varargs and stdarg. */ 1803 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ 1804 rs6000_va_start (valist, nextarg) 1805 1806 /* Implement `va_arg'. */ 1807 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1808 rs6000_va_arg (valist, type) 1809 1810 /* For AIX, the rule is that structures are passed left-aligned in 1811 their stack slot. However, GCC does not presently do this: 1812 structures which are the same size as integer types are passed 1813 right-aligned, as if they were in fact integers. This only 1814 matters for structures of size 1 or 2, or 4 when TARGET_64BIT. 1815 ABI_V4 does not use std_expand_builtin_va_arg. */ 1816 #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode) 1817 1818 /* Define this macro to be a nonzero value if the location where a function 1819 argument is passed depends on whether or not it is a named argument. */ 1820 #define STRICT_ARGUMENT_NAMING 1 1821 1822 /* We do not allow indirect calls to be optimized into sibling calls, nor 1823 do we allow calls with vector parameters. */ 1824 #define FUNCTION_OK_FOR_SIBCALL(DECL) function_ok_for_sibcall ((DECL)) 1825 1826 /* Output assembler code to FILE to increment profiler label # LABELNO 1827 for profiling a function entry. */ 1828 1829 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1830 output_function_profiler ((FILE), (LABELNO)); 1831 1832 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1833 the stack pointer does not matter. No definition is equivalent to 1834 always zero. 1835 1836 On the RS/6000, this is nonzero because we can restore the stack from 1837 its backpointer, which we maintain. */ 1838 #define EXIT_IGNORE_STACK 1 1839 1840 /* Define this macro as a C expression that is nonzero for registers 1841 that are used by the epilogue or the return' pattern. The stack 1842 and frame pointer registers are already be assumed to be used as 1843 needed. */ 1844 1845 #define EPILOGUE_USES(REGNO) \ 1846 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ 1847 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1848 || (current_function_calls_eh_return \ 1849 && TARGET_AIX \ 1850 && (REGNO) == 2)) 1851 1852 1853 /* TRAMPOLINE_TEMPLATE deleted */ 1854 1855 /* Length in units of the trampoline for entering a nested function. */ 1856 1857 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1858 1859 /* Emit RTL insns to initialize the variable parts of a trampoline. 1860 FNADDR is an RTX for the address of the function's pure code. 1861 CXT is an RTX for the static chain value for the function. */ 1862 1863 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ 1864 rs6000_initialize_trampoline (ADDR, FNADDR, CXT) 1865 1866 /* Definitions for __builtin_return_address and __builtin_frame_address. 1867 __builtin_return_address (0) should give link register (65), enable 1868 this. */ 1869 /* This should be uncommented, so that the link register is used, but 1870 currently this would result in unmatched insns and spilling fixed 1871 registers so we'll leave it for another day. When these problems are 1872 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1873 (mrs) */ 1874 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1875 1876 /* Number of bytes into the frame return addresses can be found. See 1877 rs6000_stack_info in rs6000.c for more information on how the different 1878 abi's store the return address. */ 1879 #define RETURN_ADDRESS_OFFSET \ 1880 ((DEFAULT_ABI == ABI_AIX \ 1881 || DEFAULT_ABI == ABI_DARWIN \ 1882 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \ 1883 (DEFAULT_ABI == ABI_V4) ? 4 : \ 1884 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) 1885 1886 /* The current return address is in link register (65). The return address 1887 of anything farther back is accessed normally at an offset of 8 from the 1888 frame pointer. */ 1889 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1890 (rs6000_return_addr (COUNT, FRAME)) 1891 1892 1893 /* Definitions for register eliminations. 1894 1895 We have two registers that can be eliminated on the RS/6000. First, the 1896 frame pointer register can often be eliminated in favor of the stack 1897 pointer register. Secondly, the argument pointer register can always be 1898 eliminated; it is replaced with either the stack or frame pointer. 1899 1900 In addition, we use the elimination mechanism to see if r30 is needed 1901 Initially we assume that it isn't. If it is, we spill it. This is done 1902 by making it an eliminable register. We replace it with itself so that 1903 if it isn't needed, then existing uses won't be modified. */ 1904 1905 /* This is an array of structures. Each structure initializes one pair 1906 of eliminable registers. The "from" register number is given first, 1907 followed by "to". Eliminations of the same "from" register are listed 1908 in order of preference. */ 1909 #define ELIMINABLE_REGS \ 1910 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1911 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1912 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 1913 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1914 1915 /* Given FROM and TO register numbers, say whether this elimination is allowed. 1916 Frame pointer elimination is automatically handled. 1917 1918 For the RS/6000, if frame pointer elimination is being done, we would like 1919 to convert ap into fp, not sp. 1920 1921 We need r30 if -mminimal-toc was specified, and there are constant pool 1922 references. */ 1923 1924 #define CAN_ELIMINATE(FROM, TO) \ 1925 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ 1926 ? ! frame_pointer_needed \ 1927 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \ 1928 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ 1929 : 1) 1930 1931 /* Define the offset between two registers, one to be eliminated, and the other 1932 its replacement, at the start of a routine. */ 1933 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1934 { \ 1935 rs6000_stack_t *info = rs6000_stack_info (); \ 1936 \ 1937 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 1938 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \ 1939 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ 1940 (OFFSET) = info->total_size; \ 1941 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 1942 (OFFSET) = (info->push_p) ? info->total_size : 0; \ 1943 else if ((FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM) \ 1944 (OFFSET) = 0; \ 1945 else \ 1946 abort (); \ 1947 } 1948 1949 /* Addressing modes, and classification of registers for them. */ 1950 1951 /* #define HAVE_POST_INCREMENT 0 */ 1952 /* #define HAVE_POST_DECREMENT 0 */ 1953 1954 #define HAVE_PRE_DECREMENT 1 1955 #define HAVE_PRE_INCREMENT 1 1956 1957 /* Macros to check register numbers against specific register classes. */ 1958 1959 /* These assume that REGNO is a hard or pseudo reg number. 1960 They give nonzero only if REGNO is a hard reg of the suitable class 1961 or a pseudo reg currently allocated to a suitable hard reg. 1962 Since they use reg_renumber, they are safe only once reg_renumber 1963 has been allocated, which happens in local-alloc.c. */ 1964 1965 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1966 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1967 ? (REGNO) <= 31 || (REGNO) == 67 \ 1968 : (reg_renumber[REGNO] >= 0 \ 1969 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) 1970 1971 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1972 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1973 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1974 : (reg_renumber[REGNO] > 0 \ 1975 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67))) 1976 1977 /* Maximum number of registers that can appear in a valid memory address. */ 1978 1979 #define MAX_REGS_PER_ADDRESS 2 1980 1981 /* Recognize any constant value that is a valid address. */ 1982 1983 #define CONSTANT_ADDRESS_P(X) \ 1984 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1985 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1986 || GET_CODE (X) == HIGH) 1987 1988 /* Nonzero if the constant value X is a legitimate general operand. 1989 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1990 1991 On the RS/6000, all integer constants are acceptable, most won't be valid 1992 for particular insns, though. Only easy FP constants are 1993 acceptable. */ 1994 1995 #define LEGITIMATE_CONSTANT_P(X) \ 1996 ((GET_CODE (X) != CONST_VECTOR \ 1997 || zero_constant (X, GET_MODE (X))) \ 1998 && (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \ 1999 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ 2000 || easy_fp_constant (X, GET_MODE (X)))) 2001 2002 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2003 and check its validity for a certain class. 2004 We have two alternate definitions for each of them. 2005 The usual definition accepts all pseudo regs; the other rejects 2006 them unless they have been allocated suitable hard regs. 2007 The symbol REG_OK_STRICT causes the latter definition to be used. 2008 2009 Most source files want to accept pseudo regs in the hope that 2010 they will get allocated to the class that the insn wants them to be in. 2011 Source files for reload pass need to be strict. 2012 After reload, it makes no difference, since pseudo regs have 2013 been eliminated by then. */ 2014 2015 #ifdef REG_OK_STRICT 2016 # define REG_OK_STRICT_FLAG 1 2017 #else 2018 # define REG_OK_STRICT_FLAG 0 2019 #endif 2020 2021 /* Nonzero if X is a hard reg that can be used as an index 2022 or if it is a pseudo reg in the non-strict case. */ 2023 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 2024 ((! (STRICT) \ 2025 && (REGNO (X) <= 31 \ 2026 || REGNO (X) == ARG_POINTER_REGNUM \ 2027 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \ 2028 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X)))) 2029 2030 /* Nonzero if X is a hard reg that can be used as a base reg 2031 or if it is a pseudo reg in the non-strict case. */ 2032 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 2033 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT))) 2034 2035 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG) 2036 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG) 2037 2038 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 2039 that is a valid memory address for an instruction. 2040 The MODE argument is the machine mode for the MEM expression 2041 that wants to use this address. 2042 2043 On the RS/6000, there are four valid address: a SYMBOL_REF that 2044 refers to a constant pool entry of an address (or the sum of it 2045 plus a constant), a short (16-bit signed) constant plus a register, 2046 the sum of two registers, or a register indirect, possibly with an 2047 auto-increment. For DFmode and DImode with an constant plus register, 2048 we must ensure that both words are addressable or PowerPC64 with offset 2049 word aligned. 2050 2051 For modes spanning multiple registers (DFmode in 32-bit GPRs, 2052 32-bit DImode, TImode), indexed addressing cannot be used because 2053 adjacent memory cells are accessed by adding word-sized offsets 2054 during assembly output. */ 2055 2056 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X)) 2057 2058 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X)) 2059 2060 /* SPE offset addressing is limited to 5-bits worth of double words. */ 2061 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) 2062 2063 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \ 2064 (TARGET_TOC \ 2065 && GET_CODE (X) == PLUS \ 2066 && GET_CODE (XEXP (X, 0)) == REG \ 2067 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \ 2068 && CONSTANT_POOL_EXPR_P (XEXP (X, 1))) 2069 2070 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \ 2071 (DEFAULT_ABI == ABI_V4 \ 2072 && !flag_pic && !TARGET_TOC \ 2073 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \ 2074 && small_data_operand (X, MODE)) 2075 2076 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \ 2077 (GET_CODE (X) == CONST_INT \ 2078 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000) 2079 2080 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \ 2081 (GET_CODE (X) == PLUS \ 2082 && GET_CODE (XEXP (X, 0)) == REG \ 2083 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ 2084 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \ 2085 && (! ALTIVEC_VECTOR_MODE (MODE) \ 2086 || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \ 2087 && (! SPE_VECTOR_MODE (MODE) \ 2088 || (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2089 && SPE_CONST_OFFSET_OK (INTVAL (XEXP (X, 1))))) \ 2090 && (((MODE) != DFmode && (MODE) != DImode) \ 2091 || (TARGET_32BIT \ 2092 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \ 2093 : ! (INTVAL (XEXP (X, 1)) & 3))) \ 2094 && (((MODE) != TFmode && (MODE) != TImode) \ 2095 || (TARGET_32BIT \ 2096 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \ 2097 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \ 2098 && ! (INTVAL (XEXP (X, 1)) & 3))))) 2099 2100 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \ 2101 (GET_CODE (X) == PLUS \ 2102 && GET_CODE (XEXP (X, 0)) == REG \ 2103 && GET_CODE (XEXP (X, 1)) == REG \ 2104 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ 2105 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \ 2106 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \ 2107 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT))))) 2108 2109 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \ 2110 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT))) 2111 2112 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \ 2113 (((TARGET_ELF && ! flag_pic) || TARGET_MACHO) \ 2114 && ! TARGET_TOC \ 2115 && GET_MODE_NUNITS (MODE) == 1 \ 2116 && (GET_MODE_BITSIZE (MODE) <= 32 \ 2117 || (TARGET_HARD_FLOAT && TARGET_FPRS && (MODE) == DFmode)) \ 2118 && GET_CODE (X) == LO_SUM \ 2119 && GET_CODE (XEXP (X, 0)) == REG \ 2120 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ 2121 && CONSTANT_P (XEXP (X, 1))) 2122 2123 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 2124 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \ 2125 goto ADDR; \ 2126 } 2127 2128 /* Try machine-dependent ways of modifying an illegitimate address 2129 to be legitimate. If we find one, return the new, valid address. 2130 This macro is used in only one place: `memory_address' in explow.c. 2131 2132 OLDX is the address as it was before break_out_memory_refs was called. 2133 In some cases it is useful to look at this to decide what needs to be done. 2134 2135 MODE and WIN are passed so that this macro can use 2136 GO_IF_LEGITIMATE_ADDRESS. 2137 2138 It is always safe for this macro to do nothing. It exists to recognize 2139 opportunities to optimize the output. 2140 2141 On RS/6000, first check for the sum of a register with a constant 2142 integer that is out of range. If so, generate code to add the 2143 constant with the low-order 16 bits masked to the register and force 2144 this result into another register (this can be done with `cau'). 2145 Then generate an address of REG+(CONST&0xffff), allowing for the 2146 possibility of bit 16 being a one. 2147 2148 Then check for the sum of a register and something not constant, try to 2149 load the other things into a register and return the sum. */ 2150 2151 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 2152 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \ 2153 if (result != NULL_RTX) \ 2154 { \ 2155 (X) = result; \ 2156 goto WIN; \ 2157 } \ 2158 } 2159 2160 /* Try a machine-dependent way of reloading an illegitimate address 2161 operand. If we find one, push the reload and jump to WIN. This 2162 macro is used in only one place: `find_reloads_address' in reload.c. 2163 2164 Implemented on rs6000 by rs6000_legitimize_reload_address. 2165 Note that (X) is evaluated twice; this is safe in current usage. */ 2166 2167 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 2168 do { \ 2169 int win; \ 2170 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \ 2171 (int)(TYPE), (IND_LEVELS), &win); \ 2172 if ( win ) \ 2173 goto WIN; \ 2174 } while (0) 2175 2176 /* Go to LABEL if ADDR (a legitimate address expression) 2177 has an effect that depends on the machine mode it is used for. 2178 2179 On the RS/6000 this is true if the address is valid with a zero offset 2180 but not with an offset of four (this means it cannot be used as an 2181 address for DImode or DFmode) or is a pre-increment or decrement. Since 2182 we know it is valid, we just check for an address that is not valid with 2183 an offset of four. */ 2184 2185 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 2186 { if (GET_CODE (ADDR) == PLUS \ 2187 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \ 2188 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \ 2189 (TARGET_32BIT ? 4 : 8))) \ 2190 goto LABEL; \ 2191 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \ 2192 goto LABEL; \ 2193 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \ 2194 goto LABEL; \ 2195 if (GET_CODE (ADDR) == LO_SUM) \ 2196 goto LABEL; \ 2197 } 2198 2199 /* The register number of the register used to address a table of 2200 static data addresses in memory. In some cases this register is 2201 defined by a processor's "application binary interface" (ABI). 2202 When this macro is defined, RTL is generated for this register 2203 once, as with the stack pointer and frame pointer registers. If 2204 this macro is not defined, it is up to the machine-dependent files 2205 to allocate such a register (if necessary). */ 2206 2207 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 2208 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 2209 2210 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 2211 2212 /* Define this macro if the register defined by 2213 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 2214 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 2215 2216 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 2217 2218 /* By generating position-independent code, when two different 2219 programs (A and B) share a common library (libC.a), the text of 2220 the library can be shared whether or not the library is linked at 2221 the same address for both programs. In some of these 2222 environments, position-independent code requires not only the use 2223 of different addressing modes, but also special code to enable the 2224 use of these addressing modes. 2225 2226 The `FINALIZE_PIC' macro serves as a hook to emit these special 2227 codes once the function is being compiled into assembly code, but 2228 not before. (It is not done before, because in the case of 2229 compiling an inline function, it would lead to multiple PIC 2230 prologues being included in functions which used inline functions 2231 and were compiled to assembly language.) */ 2232 2233 /* #define FINALIZE_PIC */ 2234 2235 /* A C expression that is nonzero if X is a legitimate immediate 2236 operand on the target machine when generating position independent 2237 code. You can assume that X satisfies `CONSTANT_P', so you need 2238 not check this. You can also assume FLAG_PIC is true, so you need 2239 not check it either. You need not define this macro if all 2240 constants (including `SYMBOL_REF') can be immediate operands when 2241 generating position independent code. */ 2242 2243 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 2244 2245 /* In rare cases, correct code generation requires extra machine 2246 dependent processing between the second jump optimization pass and 2247 delayed branch scheduling. On those machines, define this macro 2248 as a C statement to act on the code starting at INSN. */ 2249 2250 /* #define MACHINE_DEPENDENT_REORG(INSN) */ 2251 2252 2253 /* Define this if some processing needs to be done immediately before 2254 emitting code for an insn. */ 2255 2256 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */ 2257 2258 /* Specify the machine mode that this machine uses 2259 for the index in the tablejump instruction. */ 2260 #define CASE_VECTOR_MODE SImode 2261 2262 /* Define as C expression which evaluates to nonzero if the tablejump 2263 instruction expects the table to contain offsets from the address of the 2264 table. 2265 Do not define this if the table should contain absolute addresses. */ 2266 #define CASE_VECTOR_PC_RELATIVE 1 2267 2268 /* Define this as 1 if `char' should by default be signed; else as 0. */ 2269 #define DEFAULT_SIGNED_CHAR 0 2270 2271 /* This flag, if defined, says the same insns that convert to a signed fixnum 2272 also convert validly to an unsigned one. */ 2273 2274 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ 2275 2276 /* Max number of bytes we can move from memory to memory 2277 in one reasonably fast instruction. */ 2278 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 2279 #define MAX_MOVE_MAX 8 2280 2281 /* Nonzero if access to memory by bytes is no faster than for words. 2282 Also nonzero if doing byte operations (specifically shifts) in registers 2283 is undesirable. */ 2284 #define SLOW_BYTE_ACCESS 1 2285 2286 /* Define if operations between registers always perform the operation 2287 on the full register even if a narrower mode is specified. */ 2288 #define WORD_REGISTER_OPERATIONS 2289 2290 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2291 will either zero-extend or sign-extend. The value of this macro should 2292 be the code that says which one of the two operations is implicitly 2293 done, NIL if none. */ 2294 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2295 2296 /* Define if loading short immediate values into registers sign extends. */ 2297 #define SHORT_IMMEDIATES_SIGN_EXTEND 2298 2299 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2300 is done just by pretending it is already truncated. */ 2301 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2302 2303 /* Specify the machine mode that pointers have. 2304 After generation of rtl, the compiler makes no further distinction 2305 between pointers and any other objects of this machine mode. */ 2306 #define Pmode (TARGET_32BIT ? SImode : DImode) 2307 2308 /* Mode of a function address in a call instruction (for indexing purposes). 2309 Doesn't matter on RS/6000. */ 2310 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode) 2311 2312 /* Define this if addresses of constant functions 2313 shouldn't be put through pseudo regs where they can be cse'd. 2314 Desirable on machines where ordinary constants are expensive 2315 but a CALL with constant address is cheap. */ 2316 #define NO_FUNCTION_CSE 2317 2318 /* Define this to be nonzero if shift instructions ignore all but the low-order 2319 few bits. 2320 2321 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 2322 have been dropped from the PowerPC architecture. */ 2323 2324 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) 2325 2326 /* Compute the cost of computing a constant rtl expression RTX 2327 whose rtx-code is CODE. The body of this macro is a portion 2328 of a switch statement. If the code is computed here, 2329 return it with a return statement. Otherwise, break from the switch. 2330 2331 On the RS/6000, if it is valid in the insn, it is free. So this 2332 always returns 0. */ 2333 2334 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 2335 case CONST_INT: \ 2336 case CONST: \ 2337 case LABEL_REF: \ 2338 case SYMBOL_REF: \ 2339 case CONST_DOUBLE: \ 2340 case HIGH: \ 2341 return 0; 2342 2343 /* Provide the costs of a rtl expression. This is in the body of a 2344 switch on CODE. */ 2345 2346 #define RTX_COSTS(X,CODE,OUTER_CODE) \ 2347 case PLUS: \ 2348 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \ 2349 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \ 2350 + 0x8000) >= 0x10000) \ 2351 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \ 2352 ? COSTS_N_INSNS (2) \ 2353 : COSTS_N_INSNS (1)); \ 2354 case AND: \ 2355 case IOR: \ 2356 case XOR: \ 2357 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \ 2358 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \ 2359 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \ 2360 ? COSTS_N_INSNS (2) \ 2361 : COSTS_N_INSNS (1)); \ 2362 case MULT: \ 2363 if (optimize_size) \ 2364 return COSTS_N_INSNS (2); \ 2365 switch (rs6000_cpu) \ 2366 { \ 2367 case PROCESSOR_RIOS1: \ 2368 case PROCESSOR_PPC405: \ 2369 return (GET_CODE (XEXP (X, 1)) != CONST_INT \ 2370 ? COSTS_N_INSNS (5) \ 2371 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ 2372 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ 2373 case PROCESSOR_RS64A: \ 2374 return (GET_CODE (XEXP (X, 1)) != CONST_INT \ 2375 ? GET_MODE (XEXP (X, 1)) != DImode \ 2376 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \ 2377 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ 2378 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); \ 2379 case PROCESSOR_RIOS2: \ 2380 case PROCESSOR_MPCCORE: \ 2381 case PROCESSOR_PPC604e: \ 2382 return COSTS_N_INSNS (2); \ 2383 case PROCESSOR_PPC601: \ 2384 return COSTS_N_INSNS (5); \ 2385 case PROCESSOR_PPC603: \ 2386 case PROCESSOR_PPC7400: \ 2387 case PROCESSOR_PPC750: \ 2388 return (GET_CODE (XEXP (X, 1)) != CONST_INT \ 2389 ? COSTS_N_INSNS (5) \ 2390 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ 2391 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \ 2392 case PROCESSOR_PPC7450: \ 2393 return (GET_CODE (XEXP (X, 1)) != CONST_INT \ 2394 ? COSTS_N_INSNS (4) \ 2395 : COSTS_N_INSNS (3)); \ 2396 case PROCESSOR_PPC403: \ 2397 case PROCESSOR_PPC604: \ 2398 case PROCESSOR_PPC8540: \ 2399 return COSTS_N_INSNS (4); \ 2400 case PROCESSOR_PPC620: \ 2401 case PROCESSOR_PPC630: \ 2402 return (GET_CODE (XEXP (X, 1)) != CONST_INT \ 2403 ? GET_MODE (XEXP (X, 1)) != DImode \ 2404 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \ 2405 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ 2406 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ 2407 case PROCESSOR_POWER4: \ 2408 return (GET_CODE (XEXP (X, 1)) != CONST_INT \ 2409 ? GET_MODE (XEXP (X, 1)) != DImode \ 2410 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4) \ 2411 : COSTS_N_INSNS (2)); \ 2412 } \ 2413 case DIV: \ 2414 case MOD: \ 2415 if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 2416 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \ 2417 return COSTS_N_INSNS (2); \ 2418 /* otherwise fall through to normal divide. */ \ 2419 case UDIV: \ 2420 case UMOD: \ 2421 switch (rs6000_cpu) \ 2422 { \ 2423 case PROCESSOR_RIOS1: \ 2424 return COSTS_N_INSNS (19); \ 2425 case PROCESSOR_RIOS2: \ 2426 return COSTS_N_INSNS (13); \ 2427 case PROCESSOR_RS64A: \ 2428 return (GET_MODE (XEXP (X, 1)) != DImode \ 2429 ? COSTS_N_INSNS (65) \ 2430 : COSTS_N_INSNS (67)); \ 2431 case PROCESSOR_MPCCORE: \ 2432 return COSTS_N_INSNS (6); \ 2433 case PROCESSOR_PPC403: \ 2434 return COSTS_N_INSNS (33); \ 2435 case PROCESSOR_PPC405: \ 2436 return COSTS_N_INSNS (35); \ 2437 case PROCESSOR_PPC601: \ 2438 return COSTS_N_INSNS (36); \ 2439 case PROCESSOR_PPC603: \ 2440 return COSTS_N_INSNS (37); \ 2441 case PROCESSOR_PPC604: \ 2442 case PROCESSOR_PPC604e: \ 2443 return COSTS_N_INSNS (20); \ 2444 case PROCESSOR_PPC620: \ 2445 case PROCESSOR_PPC630: \ 2446 case PROCESSOR_POWER4: \ 2447 return (GET_MODE (XEXP (X, 1)) != DImode \ 2448 ? COSTS_N_INSNS (21) \ 2449 : COSTS_N_INSNS (37)); \ 2450 case PROCESSOR_PPC750: \ 2451 case PROCESSOR_PPC8540: \ 2452 case PROCESSOR_PPC7400: \ 2453 return COSTS_N_INSNS (19); \ 2454 case PROCESSOR_PPC7450: \ 2455 return COSTS_N_INSNS (23); \ 2456 } \ 2457 case FFS: \ 2458 return COSTS_N_INSNS (4); \ 2459 case MEM: \ 2460 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \ 2461 return 5; 2462 2463 /* Compute the cost of an address. This is meant to approximate the size 2464 and/or execution delay of an insn using that address. If the cost is 2465 approximated by the RTL complexity, including CONST_COSTS above, as 2466 is usually the case for CISC machines, this macro should not be defined. 2467 For aggressively RISCy machines, only one insn format is allowed, so 2468 this macro should be a constant. The value of this macro only matters 2469 for valid addresses. 2470 2471 For the RS/6000, everything is cost 0. */ 2472 2473 #define ADDRESS_COST(RTX) 0 2474 2475 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 2476 should be adjusted to reflect any required changes. This macro is used when 2477 there is some systematic length adjustment required that would be difficult 2478 to express in the length attribute. */ 2479 2480 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 2481 2482 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 2483 COMPARE, return the mode to be used for the comparison. For 2484 floating-point, CCFPmode should be used. CCUNSmode should be used 2485 for unsigned comparisons. CCEQmode should be used when we are 2486 doing an inequality comparison on the result of a 2487 comparison. CCmode should be used in all other cases. */ 2488 2489 #define SELECT_CC_MODE(OP,X,Y) \ 2490 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \ 2491 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 2492 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \ 2493 ? CCEQmode : CCmode)) 2494 2495 /* Define the information needed to generate branch and scc insns. This is 2496 stored from the compare operation. Note that we can't use "rtx" here 2497 since it hasn't been defined! */ 2498 2499 extern GTY(()) rtx rs6000_compare_op0; 2500 extern GTY(()) rtx rs6000_compare_op1; 2501 extern int rs6000_compare_fp_p; 2502 2503 /* Control the assembler format that we output. */ 2504 2505 /* A C string constant describing how to begin a comment in the target 2506 assembler language. The compiler assumes that the comment will end at 2507 the end of the line. */ 2508 #define ASM_COMMENT_START " #" 2509 2510 /* Implicit library calls should use memcpy, not bcopy, etc. */ 2511 2512 #define TARGET_MEM_FUNCTIONS 2513 2514 /* Flag to say the TOC is initialized */ 2515 extern int toc_initialized; 2516 2517 /* Macro to output a special constant pool entry. Go to WIN if we output 2518 it. Otherwise, it is written the usual way. 2519 2520 On the RS/6000, toc entries are handled this way. */ 2521 2522 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 2523 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 2524 { \ 2525 output_toc (FILE, X, LABELNO, MODE); \ 2526 goto WIN; \ 2527 } \ 2528 } 2529 2530 #ifdef HAVE_GAS_WEAK 2531 #define RS6000_WEAK 1 2532 #else 2533 #define RS6000_WEAK 0 2534 #endif 2535 2536 #if RS6000_WEAK 2537 /* Used in lieu of ASM_WEAKEN_LABEL. */ 2538 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 2539 do \ 2540 { \ 2541 fputs ("\t.weak\t", (FILE)); \ 2542 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2543 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2544 && DEFAULT_ABI == ABI_AIX) \ 2545 { \ 2546 if (TARGET_XCOFF) \ 2547 fputs ("[DS]", (FILE)); \ 2548 fputs ("\n\t.weak\t.", (FILE)); \ 2549 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2550 } \ 2551 fputc ('\n', (FILE)); \ 2552 if (VAL) \ 2553 { \ 2554 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 2555 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2556 && DEFAULT_ABI == ABI_AIX) \ 2557 { \ 2558 fputs ("\t.set\t.", (FILE)); \ 2559 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2560 fputs (",.", (FILE)); \ 2561 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 2562 fputc ('\n', (FILE)); \ 2563 } \ 2564 } \ 2565 } \ 2566 while (0) 2567 #endif 2568 2569 /* This implements the `alias' attribute. */ 2570 #undef ASM_OUTPUT_DEF_FROM_DECLS 2571 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2572 do \ 2573 { \ 2574 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2575 const char *name = IDENTIFIER_POINTER (TARGET); \ 2576 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2577 && DEFAULT_ABI == ABI_AIX) \ 2578 { \ 2579 if (TREE_PUBLIC (DECL)) \ 2580 { \ 2581 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2582 { \ 2583 fputs ("\t.globl\t.", FILE); \ 2584 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2585 putc ('\n', FILE); \ 2586 } \ 2587 } \ 2588 else if (TARGET_XCOFF) \ 2589 { \ 2590 fputs ("\t.lglobl\t.", FILE); \ 2591 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2592 putc ('\n', FILE); \ 2593 } \ 2594 fputs ("\t.set\t.", FILE); \ 2595 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2596 fputs (",.", FILE); \ 2597 RS6000_OUTPUT_BASENAME (FILE, name); \ 2598 fputc ('\n', FILE); \ 2599 } \ 2600 ASM_OUTPUT_DEF (FILE, alias, name); \ 2601 } \ 2602 while (0) 2603 2604 /* Output to assembler file text saying following lines 2605 may contain character constants, extra white space, comments, etc. */ 2606 2607 #define ASM_APP_ON "" 2608 2609 /* Output to assembler file text saying following lines 2610 no longer contain unusual constructs. */ 2611 2612 #define ASM_APP_OFF "" 2613 2614 /* How to refer to registers in assembler output. 2615 This sequence is indexed by compiler's hard-register-number (see above). */ 2616 2617 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2618 2619 #define REGISTER_NAMES \ 2620 { \ 2621 &rs6000_reg_names[ 0][0], /* r0 */ \ 2622 &rs6000_reg_names[ 1][0], /* r1 */ \ 2623 &rs6000_reg_names[ 2][0], /* r2 */ \ 2624 &rs6000_reg_names[ 3][0], /* r3 */ \ 2625 &rs6000_reg_names[ 4][0], /* r4 */ \ 2626 &rs6000_reg_names[ 5][0], /* r5 */ \ 2627 &rs6000_reg_names[ 6][0], /* r6 */ \ 2628 &rs6000_reg_names[ 7][0], /* r7 */ \ 2629 &rs6000_reg_names[ 8][0], /* r8 */ \ 2630 &rs6000_reg_names[ 9][0], /* r9 */ \ 2631 &rs6000_reg_names[10][0], /* r10 */ \ 2632 &rs6000_reg_names[11][0], /* r11 */ \ 2633 &rs6000_reg_names[12][0], /* r12 */ \ 2634 &rs6000_reg_names[13][0], /* r13 */ \ 2635 &rs6000_reg_names[14][0], /* r14 */ \ 2636 &rs6000_reg_names[15][0], /* r15 */ \ 2637 &rs6000_reg_names[16][0], /* r16 */ \ 2638 &rs6000_reg_names[17][0], /* r17 */ \ 2639 &rs6000_reg_names[18][0], /* r18 */ \ 2640 &rs6000_reg_names[19][0], /* r19 */ \ 2641 &rs6000_reg_names[20][0], /* r20 */ \ 2642 &rs6000_reg_names[21][0], /* r21 */ \ 2643 &rs6000_reg_names[22][0], /* r22 */ \ 2644 &rs6000_reg_names[23][0], /* r23 */ \ 2645 &rs6000_reg_names[24][0], /* r24 */ \ 2646 &rs6000_reg_names[25][0], /* r25 */ \ 2647 &rs6000_reg_names[26][0], /* r26 */ \ 2648 &rs6000_reg_names[27][0], /* r27 */ \ 2649 &rs6000_reg_names[28][0], /* r28 */ \ 2650 &rs6000_reg_names[29][0], /* r29 */ \ 2651 &rs6000_reg_names[30][0], /* r30 */ \ 2652 &rs6000_reg_names[31][0], /* r31 */ \ 2653 \ 2654 &rs6000_reg_names[32][0], /* fr0 */ \ 2655 &rs6000_reg_names[33][0], /* fr1 */ \ 2656 &rs6000_reg_names[34][0], /* fr2 */ \ 2657 &rs6000_reg_names[35][0], /* fr3 */ \ 2658 &rs6000_reg_names[36][0], /* fr4 */ \ 2659 &rs6000_reg_names[37][0], /* fr5 */ \ 2660 &rs6000_reg_names[38][0], /* fr6 */ \ 2661 &rs6000_reg_names[39][0], /* fr7 */ \ 2662 &rs6000_reg_names[40][0], /* fr8 */ \ 2663 &rs6000_reg_names[41][0], /* fr9 */ \ 2664 &rs6000_reg_names[42][0], /* fr10 */ \ 2665 &rs6000_reg_names[43][0], /* fr11 */ \ 2666 &rs6000_reg_names[44][0], /* fr12 */ \ 2667 &rs6000_reg_names[45][0], /* fr13 */ \ 2668 &rs6000_reg_names[46][0], /* fr14 */ \ 2669 &rs6000_reg_names[47][0], /* fr15 */ \ 2670 &rs6000_reg_names[48][0], /* fr16 */ \ 2671 &rs6000_reg_names[49][0], /* fr17 */ \ 2672 &rs6000_reg_names[50][0], /* fr18 */ \ 2673 &rs6000_reg_names[51][0], /* fr19 */ \ 2674 &rs6000_reg_names[52][0], /* fr20 */ \ 2675 &rs6000_reg_names[53][0], /* fr21 */ \ 2676 &rs6000_reg_names[54][0], /* fr22 */ \ 2677 &rs6000_reg_names[55][0], /* fr23 */ \ 2678 &rs6000_reg_names[56][0], /* fr24 */ \ 2679 &rs6000_reg_names[57][0], /* fr25 */ \ 2680 &rs6000_reg_names[58][0], /* fr26 */ \ 2681 &rs6000_reg_names[59][0], /* fr27 */ \ 2682 &rs6000_reg_names[60][0], /* fr28 */ \ 2683 &rs6000_reg_names[61][0], /* fr29 */ \ 2684 &rs6000_reg_names[62][0], /* fr30 */ \ 2685 &rs6000_reg_names[63][0], /* fr31 */ \ 2686 \ 2687 &rs6000_reg_names[64][0], /* mq */ \ 2688 &rs6000_reg_names[65][0], /* lr */ \ 2689 &rs6000_reg_names[66][0], /* ctr */ \ 2690 &rs6000_reg_names[67][0], /* ap */ \ 2691 \ 2692 &rs6000_reg_names[68][0], /* cr0 */ \ 2693 &rs6000_reg_names[69][0], /* cr1 */ \ 2694 &rs6000_reg_names[70][0], /* cr2 */ \ 2695 &rs6000_reg_names[71][0], /* cr3 */ \ 2696 &rs6000_reg_names[72][0], /* cr4 */ \ 2697 &rs6000_reg_names[73][0], /* cr5 */ \ 2698 &rs6000_reg_names[74][0], /* cr6 */ \ 2699 &rs6000_reg_names[75][0], /* cr7 */ \ 2700 \ 2701 &rs6000_reg_names[76][0], /* xer */ \ 2702 \ 2703 &rs6000_reg_names[77][0], /* v0 */ \ 2704 &rs6000_reg_names[78][0], /* v1 */ \ 2705 &rs6000_reg_names[79][0], /* v2 */ \ 2706 &rs6000_reg_names[80][0], /* v3 */ \ 2707 &rs6000_reg_names[81][0], /* v4 */ \ 2708 &rs6000_reg_names[82][0], /* v5 */ \ 2709 &rs6000_reg_names[83][0], /* v6 */ \ 2710 &rs6000_reg_names[84][0], /* v7 */ \ 2711 &rs6000_reg_names[85][0], /* v8 */ \ 2712 &rs6000_reg_names[86][0], /* v9 */ \ 2713 &rs6000_reg_names[87][0], /* v10 */ \ 2714 &rs6000_reg_names[88][0], /* v11 */ \ 2715 &rs6000_reg_names[89][0], /* v12 */ \ 2716 &rs6000_reg_names[90][0], /* v13 */ \ 2717 &rs6000_reg_names[91][0], /* v14 */ \ 2718 &rs6000_reg_names[92][0], /* v15 */ \ 2719 &rs6000_reg_names[93][0], /* v16 */ \ 2720 &rs6000_reg_names[94][0], /* v17 */ \ 2721 &rs6000_reg_names[95][0], /* v18 */ \ 2722 &rs6000_reg_names[96][0], /* v19 */ \ 2723 &rs6000_reg_names[97][0], /* v20 */ \ 2724 &rs6000_reg_names[98][0], /* v21 */ \ 2725 &rs6000_reg_names[99][0], /* v22 */ \ 2726 &rs6000_reg_names[100][0], /* v23 */ \ 2727 &rs6000_reg_names[101][0], /* v24 */ \ 2728 &rs6000_reg_names[102][0], /* v25 */ \ 2729 &rs6000_reg_names[103][0], /* v26 */ \ 2730 &rs6000_reg_names[104][0], /* v27 */ \ 2731 &rs6000_reg_names[105][0], /* v28 */ \ 2732 &rs6000_reg_names[106][0], /* v29 */ \ 2733 &rs6000_reg_names[107][0], /* v30 */ \ 2734 &rs6000_reg_names[108][0], /* v31 */ \ 2735 &rs6000_reg_names[109][0], /* vrsave */ \ 2736 &rs6000_reg_names[110][0], /* vscr */ \ 2737 &rs6000_reg_names[111][0], /* spe_acc */ \ 2738 &rs6000_reg_names[112][0], /* spefscr */ \ 2739 } 2740 2741 /* print-rtl can't handle the above REGISTER_NAMES, so define the 2742 following for it. Switch to use the alternate names since 2743 they are more mnemonic. */ 2744 2745 #define DEBUG_REGISTER_NAMES \ 2746 { \ 2747 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 2748 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2749 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 2750 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 2751 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 2752 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 2753 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ 2754 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \ 2755 "mq", "lr", "ctr", "ap", \ 2756 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \ 2757 "xer", \ 2758 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 2759 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 2760 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 2761 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 2762 "vrsave", "vscr", \ 2763 "spe_acc", "spefscr" \ 2764 } 2765 2766 /* Table of additional register names to use in user input. */ 2767 2768 #define ADDITIONAL_REGISTER_NAMES \ 2769 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2770 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2771 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2772 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2773 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2774 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2775 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2776 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2777 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2778 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2779 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2780 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2781 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2782 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2783 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2784 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2785 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2786 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2787 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2788 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2789 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2790 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2791 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2792 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2793 {"vrsave", 109}, {"vscr", 110}, \ 2794 {"spe_acc", 111}, {"spefscr", 112}, \ 2795 /* no additional names for: mq, lr, ctr, ap */ \ 2796 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2797 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2798 {"cc", 68}, {"sp", 1}, {"toc", 2} } 2799 2800 /* Text to write out after a CALL that may be replaced by glue code by 2801 the loader. This depends on the AIX version. */ 2802 #define RS6000_CALL_GLUE "cror 31,31,31" 2803 2804 /* This is how to output an element of a case-vector that is relative. */ 2805 2806 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2807 do { char buf[100]; \ 2808 fputs ("\t.long ", FILE); \ 2809 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2810 assemble_name (FILE, buf); \ 2811 putc ('-', FILE); \ 2812 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2813 assemble_name (FILE, buf); \ 2814 putc ('\n', FILE); \ 2815 } while (0) 2816 2817 /* This is how to output an assembler line 2818 that says to advance the location counter 2819 to a multiple of 2**LOG bytes. */ 2820 2821 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2822 if ((LOG) != 0) \ 2823 fprintf (FILE, "\t.align %d\n", (LOG)) 2824 2825 /* Store in OUTPUT a string (made with alloca) containing 2826 an assembler-name for a local static variable named NAME. 2827 LABELNO is an integer which is different for each call. */ 2828 2829 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 2830 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 2831 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 2832 2833 /* Pick up the return address upon entry to a procedure. Used for 2834 dwarf2 unwind information. This also enables the table driven 2835 mechanism. */ 2836 2837 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) 2838 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) 2839 2840 /* Describe how we implement __builtin_eh_return. */ 2841 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2842 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2843 2844 /* Print operand X (an rtx) in assembler syntax to file FILE. 2845 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2846 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2847 2848 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2849 2850 /* Define which CODE values are valid. */ 2851 2852 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2853 ((CODE) == '.') 2854 2855 /* Print a memory address as an operand to reference that memory location. */ 2856 2857 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2858 2859 /* Define the codes that are matched by predicates in rs6000.c. */ 2860 2861 #define PREDICATE_CODES \ 2862 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2863 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \ 2864 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ 2865 LABEL_REF, SUBREG, REG, MEM}}, \ 2866 {"short_cint_operand", {CONST_INT}}, \ 2867 {"u_short_cint_operand", {CONST_INT}}, \ 2868 {"non_short_cint_operand", {CONST_INT}}, \ 2869 {"exact_log2_cint_operand", {CONST_INT}}, \ 2870 {"gpc_reg_operand", {SUBREG, REG}}, \ 2871 {"cc_reg_operand", {SUBREG, REG}}, \ 2872 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \ 2873 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ 2874 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ 2875 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \ 2876 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ 2877 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ 2878 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \ 2879 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \ 2880 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \ 2881 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2882 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ 2883 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ 2884 {"easy_fp_constant", {CONST_DOUBLE}}, \ 2885 {"zero_fp_constant", {CONST_DOUBLE}}, \ 2886 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \ 2887 {"lwa_operand", {SUBREG, MEM, REG}}, \ 2888 {"volatile_mem_operand", {MEM}}, \ 2889 {"offsettable_mem_operand", {MEM}}, \ 2890 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \ 2891 {"add_operand", {SUBREG, REG, CONST_INT}}, \ 2892 {"non_add_cint_operand", {CONST_INT}}, \ 2893 {"and_operand", {SUBREG, REG, CONST_INT}}, \ 2894 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2895 {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \ 2896 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ 2897 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ 2898 {"mask_operand", {CONST_INT}}, \ 2899 {"mask_operand_wrap", {CONST_INT}}, \ 2900 {"mask64_operand", {CONST_INT}}, \ 2901 {"mask64_2_operand", {CONST_INT}}, \ 2902 {"count_register_operand", {REG}}, \ 2903 {"xer_operand", {REG}}, \ 2904 {"symbol_ref_operand", {SYMBOL_REF}}, \ 2905 {"call_operand", {SYMBOL_REF, REG}}, \ 2906 {"current_file_function_operand", {SYMBOL_REF}}, \ 2907 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ 2908 CONST_DOUBLE, SYMBOL_REF}}, \ 2909 {"load_multiple_operation", {PARALLEL}}, \ 2910 {"store_multiple_operation", {PARALLEL}}, \ 2911 {"vrsave_operation", {PARALLEL}}, \ 2912 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \ 2913 GT, LEU, LTU, GEU, GTU, \ 2914 UNORDERED, ORDERED, \ 2915 UNGE, UNLE }}, \ 2916 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \ 2917 UNORDERED }}, \ 2918 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \ 2919 GT, LEU, LTU, GEU, GTU, \ 2920 UNORDERED, ORDERED, \ 2921 UNGE, UNLE }}, \ 2922 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \ 2923 GT, LEU, LTU, GEU, GTU}}, \ 2924 {"boolean_operator", {AND, IOR, XOR}}, \ 2925 {"boolean_or_operator", {IOR, XOR}}, \ 2926 {"altivec_register_operand", {REG}}, \ 2927 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}}, 2928 2929 /* uncomment for disabling the corresponding default options */ 2930 /* #define MACHINE_no_sched_interblock */ 2931 /* #define MACHINE_no_sched_speculative */ 2932 /* #define MACHINE_no_sched_speculative_load */ 2933 2934 /* General flags. */ 2935 extern int flag_pic; 2936 extern int optimize; 2937 extern int flag_expensive_optimizations; 2938 extern int frame_pointer_needed; 2939 2940 enum rs6000_builtins 2941 { 2942 /* AltiVec builtins. */ 2943 ALTIVEC_BUILTIN_ST_INTERNAL_4si, 2944 ALTIVEC_BUILTIN_LD_INTERNAL_4si, 2945 ALTIVEC_BUILTIN_ST_INTERNAL_8hi, 2946 ALTIVEC_BUILTIN_LD_INTERNAL_8hi, 2947 ALTIVEC_BUILTIN_ST_INTERNAL_16qi, 2948 ALTIVEC_BUILTIN_LD_INTERNAL_16qi, 2949 ALTIVEC_BUILTIN_ST_INTERNAL_4sf, 2950 ALTIVEC_BUILTIN_LD_INTERNAL_4sf, 2951 ALTIVEC_BUILTIN_VADDUBM, 2952 ALTIVEC_BUILTIN_VADDUHM, 2953 ALTIVEC_BUILTIN_VADDUWM, 2954 ALTIVEC_BUILTIN_VADDFP, 2955 ALTIVEC_BUILTIN_VADDCUW, 2956 ALTIVEC_BUILTIN_VADDUBS, 2957 ALTIVEC_BUILTIN_VADDSBS, 2958 ALTIVEC_BUILTIN_VADDUHS, 2959 ALTIVEC_BUILTIN_VADDSHS, 2960 ALTIVEC_BUILTIN_VADDUWS, 2961 ALTIVEC_BUILTIN_VADDSWS, 2962 ALTIVEC_BUILTIN_VAND, 2963 ALTIVEC_BUILTIN_VANDC, 2964 ALTIVEC_BUILTIN_VAVGUB, 2965 ALTIVEC_BUILTIN_VAVGSB, 2966 ALTIVEC_BUILTIN_VAVGUH, 2967 ALTIVEC_BUILTIN_VAVGSH, 2968 ALTIVEC_BUILTIN_VAVGUW, 2969 ALTIVEC_BUILTIN_VAVGSW, 2970 ALTIVEC_BUILTIN_VCFUX, 2971 ALTIVEC_BUILTIN_VCFSX, 2972 ALTIVEC_BUILTIN_VCTSXS, 2973 ALTIVEC_BUILTIN_VCTUXS, 2974 ALTIVEC_BUILTIN_VCMPBFP, 2975 ALTIVEC_BUILTIN_VCMPEQUB, 2976 ALTIVEC_BUILTIN_VCMPEQUH, 2977 ALTIVEC_BUILTIN_VCMPEQUW, 2978 ALTIVEC_BUILTIN_VCMPEQFP, 2979 ALTIVEC_BUILTIN_VCMPGEFP, 2980 ALTIVEC_BUILTIN_VCMPGTUB, 2981 ALTIVEC_BUILTIN_VCMPGTSB, 2982 ALTIVEC_BUILTIN_VCMPGTUH, 2983 ALTIVEC_BUILTIN_VCMPGTSH, 2984 ALTIVEC_BUILTIN_VCMPGTUW, 2985 ALTIVEC_BUILTIN_VCMPGTSW, 2986 ALTIVEC_BUILTIN_VCMPGTFP, 2987 ALTIVEC_BUILTIN_VEXPTEFP, 2988 ALTIVEC_BUILTIN_VLOGEFP, 2989 ALTIVEC_BUILTIN_VMADDFP, 2990 ALTIVEC_BUILTIN_VMAXUB, 2991 ALTIVEC_BUILTIN_VMAXSB, 2992 ALTIVEC_BUILTIN_VMAXUH, 2993 ALTIVEC_BUILTIN_VMAXSH, 2994 ALTIVEC_BUILTIN_VMAXUW, 2995 ALTIVEC_BUILTIN_VMAXSW, 2996 ALTIVEC_BUILTIN_VMAXFP, 2997 ALTIVEC_BUILTIN_VMHADDSHS, 2998 ALTIVEC_BUILTIN_VMHRADDSHS, 2999 ALTIVEC_BUILTIN_VMLADDUHM, 3000 ALTIVEC_BUILTIN_VMRGHB, 3001 ALTIVEC_BUILTIN_VMRGHH, 3002 ALTIVEC_BUILTIN_VMRGHW, 3003 ALTIVEC_BUILTIN_VMRGLB, 3004 ALTIVEC_BUILTIN_VMRGLH, 3005 ALTIVEC_BUILTIN_VMRGLW, 3006 ALTIVEC_BUILTIN_VMSUMUBM, 3007 ALTIVEC_BUILTIN_VMSUMMBM, 3008 ALTIVEC_BUILTIN_VMSUMUHM, 3009 ALTIVEC_BUILTIN_VMSUMSHM, 3010 ALTIVEC_BUILTIN_VMSUMUHS, 3011 ALTIVEC_BUILTIN_VMSUMSHS, 3012 ALTIVEC_BUILTIN_VMINUB, 3013 ALTIVEC_BUILTIN_VMINSB, 3014 ALTIVEC_BUILTIN_VMINUH, 3015 ALTIVEC_BUILTIN_VMINSH, 3016 ALTIVEC_BUILTIN_VMINUW, 3017 ALTIVEC_BUILTIN_VMINSW, 3018 ALTIVEC_BUILTIN_VMINFP, 3019 ALTIVEC_BUILTIN_VMULEUB, 3020 ALTIVEC_BUILTIN_VMULESB, 3021 ALTIVEC_BUILTIN_VMULEUH, 3022 ALTIVEC_BUILTIN_VMULESH, 3023 ALTIVEC_BUILTIN_VMULOUB, 3024 ALTIVEC_BUILTIN_VMULOSB, 3025 ALTIVEC_BUILTIN_VMULOUH, 3026 ALTIVEC_BUILTIN_VMULOSH, 3027 ALTIVEC_BUILTIN_VNMSUBFP, 3028 ALTIVEC_BUILTIN_VNOR, 3029 ALTIVEC_BUILTIN_VOR, 3030 ALTIVEC_BUILTIN_VSEL_4SI, 3031 ALTIVEC_BUILTIN_VSEL_4SF, 3032 ALTIVEC_BUILTIN_VSEL_8HI, 3033 ALTIVEC_BUILTIN_VSEL_16QI, 3034 ALTIVEC_BUILTIN_VPERM_4SI, 3035 ALTIVEC_BUILTIN_VPERM_4SF, 3036 ALTIVEC_BUILTIN_VPERM_8HI, 3037 ALTIVEC_BUILTIN_VPERM_16QI, 3038 ALTIVEC_BUILTIN_VPKUHUM, 3039 ALTIVEC_BUILTIN_VPKUWUM, 3040 ALTIVEC_BUILTIN_VPKPX, 3041 ALTIVEC_BUILTIN_VPKUHSS, 3042 ALTIVEC_BUILTIN_VPKSHSS, 3043 ALTIVEC_BUILTIN_VPKUWSS, 3044 ALTIVEC_BUILTIN_VPKSWSS, 3045 ALTIVEC_BUILTIN_VPKUHUS, 3046 ALTIVEC_BUILTIN_VPKSHUS, 3047 ALTIVEC_BUILTIN_VPKUWUS, 3048 ALTIVEC_BUILTIN_VPKSWUS, 3049 ALTIVEC_BUILTIN_VREFP, 3050 ALTIVEC_BUILTIN_VRFIM, 3051 ALTIVEC_BUILTIN_VRFIN, 3052 ALTIVEC_BUILTIN_VRFIP, 3053 ALTIVEC_BUILTIN_VRFIZ, 3054 ALTIVEC_BUILTIN_VRLB, 3055 ALTIVEC_BUILTIN_VRLH, 3056 ALTIVEC_BUILTIN_VRLW, 3057 ALTIVEC_BUILTIN_VRSQRTEFP, 3058 ALTIVEC_BUILTIN_VSLB, 3059 ALTIVEC_BUILTIN_VSLH, 3060 ALTIVEC_BUILTIN_VSLW, 3061 ALTIVEC_BUILTIN_VSL, 3062 ALTIVEC_BUILTIN_VSLO, 3063 ALTIVEC_BUILTIN_VSPLTB, 3064 ALTIVEC_BUILTIN_VSPLTH, 3065 ALTIVEC_BUILTIN_VSPLTW, 3066 ALTIVEC_BUILTIN_VSPLTISB, 3067 ALTIVEC_BUILTIN_VSPLTISH, 3068 ALTIVEC_BUILTIN_VSPLTISW, 3069 ALTIVEC_BUILTIN_VSRB, 3070 ALTIVEC_BUILTIN_VSRH, 3071 ALTIVEC_BUILTIN_VSRW, 3072 ALTIVEC_BUILTIN_VSRAB, 3073 ALTIVEC_BUILTIN_VSRAH, 3074 ALTIVEC_BUILTIN_VSRAW, 3075 ALTIVEC_BUILTIN_VSR, 3076 ALTIVEC_BUILTIN_VSRO, 3077 ALTIVEC_BUILTIN_VSUBUBM, 3078 ALTIVEC_BUILTIN_VSUBUHM, 3079 ALTIVEC_BUILTIN_VSUBUWM, 3080 ALTIVEC_BUILTIN_VSUBFP, 3081 ALTIVEC_BUILTIN_VSUBCUW, 3082 ALTIVEC_BUILTIN_VSUBUBS, 3083 ALTIVEC_BUILTIN_VSUBSBS, 3084 ALTIVEC_BUILTIN_VSUBUHS, 3085 ALTIVEC_BUILTIN_VSUBSHS, 3086 ALTIVEC_BUILTIN_VSUBUWS, 3087 ALTIVEC_BUILTIN_VSUBSWS, 3088 ALTIVEC_BUILTIN_VSUM4UBS, 3089 ALTIVEC_BUILTIN_VSUM4SBS, 3090 ALTIVEC_BUILTIN_VSUM4SHS, 3091 ALTIVEC_BUILTIN_VSUM2SWS, 3092 ALTIVEC_BUILTIN_VSUMSWS, 3093 ALTIVEC_BUILTIN_VXOR, 3094 ALTIVEC_BUILTIN_VSLDOI_16QI, 3095 ALTIVEC_BUILTIN_VSLDOI_8HI, 3096 ALTIVEC_BUILTIN_VSLDOI_4SI, 3097 ALTIVEC_BUILTIN_VSLDOI_4SF, 3098 ALTIVEC_BUILTIN_VUPKHSB, 3099 ALTIVEC_BUILTIN_VUPKHPX, 3100 ALTIVEC_BUILTIN_VUPKHSH, 3101 ALTIVEC_BUILTIN_VUPKLSB, 3102 ALTIVEC_BUILTIN_VUPKLPX, 3103 ALTIVEC_BUILTIN_VUPKLSH, 3104 ALTIVEC_BUILTIN_MTVSCR, 3105 ALTIVEC_BUILTIN_MFVSCR, 3106 ALTIVEC_BUILTIN_DSSALL, 3107 ALTIVEC_BUILTIN_DSS, 3108 ALTIVEC_BUILTIN_LVSL, 3109 ALTIVEC_BUILTIN_LVSR, 3110 ALTIVEC_BUILTIN_DSTT, 3111 ALTIVEC_BUILTIN_DSTST, 3112 ALTIVEC_BUILTIN_DSTSTT, 3113 ALTIVEC_BUILTIN_DST, 3114 ALTIVEC_BUILTIN_LVEBX, 3115 ALTIVEC_BUILTIN_LVEHX, 3116 ALTIVEC_BUILTIN_LVEWX, 3117 ALTIVEC_BUILTIN_LVXL, 3118 ALTIVEC_BUILTIN_LVX, 3119 ALTIVEC_BUILTIN_STVX, 3120 ALTIVEC_BUILTIN_STVEBX, 3121 ALTIVEC_BUILTIN_STVEHX, 3122 ALTIVEC_BUILTIN_STVEWX, 3123 ALTIVEC_BUILTIN_STVXL, 3124 ALTIVEC_BUILTIN_VCMPBFP_P, 3125 ALTIVEC_BUILTIN_VCMPEQFP_P, 3126 ALTIVEC_BUILTIN_VCMPEQUB_P, 3127 ALTIVEC_BUILTIN_VCMPEQUH_P, 3128 ALTIVEC_BUILTIN_VCMPEQUW_P, 3129 ALTIVEC_BUILTIN_VCMPGEFP_P, 3130 ALTIVEC_BUILTIN_VCMPGTFP_P, 3131 ALTIVEC_BUILTIN_VCMPGTSB_P, 3132 ALTIVEC_BUILTIN_VCMPGTSH_P, 3133 ALTIVEC_BUILTIN_VCMPGTSW_P, 3134 ALTIVEC_BUILTIN_VCMPGTUB_P, 3135 ALTIVEC_BUILTIN_VCMPGTUH_P, 3136 ALTIVEC_BUILTIN_VCMPGTUW_P, 3137 ALTIVEC_BUILTIN_ABSS_V4SI, 3138 ALTIVEC_BUILTIN_ABSS_V8HI, 3139 ALTIVEC_BUILTIN_ABSS_V16QI, 3140 ALTIVEC_BUILTIN_ABS_V4SI, 3141 ALTIVEC_BUILTIN_ABS_V4SF, 3142 ALTIVEC_BUILTIN_ABS_V8HI, 3143 ALTIVEC_BUILTIN_ABS_V16QI 3144 /* SPE builtins. */ 3145 , SPE_BUILTIN_EVADDW, 3146 SPE_BUILTIN_EVAND, 3147 SPE_BUILTIN_EVANDC, 3148 SPE_BUILTIN_EVDIVWS, 3149 SPE_BUILTIN_EVDIVWU, 3150 SPE_BUILTIN_EVEQV, 3151 SPE_BUILTIN_EVFSADD, 3152 SPE_BUILTIN_EVFSDIV, 3153 SPE_BUILTIN_EVFSMUL, 3154 SPE_BUILTIN_EVFSSUB, 3155 SPE_BUILTIN_EVLDDX, 3156 SPE_BUILTIN_EVLDHX, 3157 SPE_BUILTIN_EVLDWX, 3158 SPE_BUILTIN_EVLHHESPLATX, 3159 SPE_BUILTIN_EVLHHOSSPLATX, 3160 SPE_BUILTIN_EVLHHOUSPLATX, 3161 SPE_BUILTIN_EVLWHEX, 3162 SPE_BUILTIN_EVLWHOSX, 3163 SPE_BUILTIN_EVLWHOUX, 3164 SPE_BUILTIN_EVLWHSPLATX, 3165 SPE_BUILTIN_EVLWWSPLATX, 3166 SPE_BUILTIN_EVMERGEHI, 3167 SPE_BUILTIN_EVMERGEHILO, 3168 SPE_BUILTIN_EVMERGELO, 3169 SPE_BUILTIN_EVMERGELOHI, 3170 SPE_BUILTIN_EVMHEGSMFAA, 3171 SPE_BUILTIN_EVMHEGSMFAN, 3172 SPE_BUILTIN_EVMHEGSMIAA, 3173 SPE_BUILTIN_EVMHEGSMIAN, 3174 SPE_BUILTIN_EVMHEGUMIAA, 3175 SPE_BUILTIN_EVMHEGUMIAN, 3176 SPE_BUILTIN_EVMHESMF, 3177 SPE_BUILTIN_EVMHESMFA, 3178 SPE_BUILTIN_EVMHESMFAAW, 3179 SPE_BUILTIN_EVMHESMFANW, 3180 SPE_BUILTIN_EVMHESMI, 3181 SPE_BUILTIN_EVMHESMIA, 3182 SPE_BUILTIN_EVMHESMIAAW, 3183 SPE_BUILTIN_EVMHESMIANW, 3184 SPE_BUILTIN_EVMHESSF, 3185 SPE_BUILTIN_EVMHESSFA, 3186 SPE_BUILTIN_EVMHESSFAAW, 3187 SPE_BUILTIN_EVMHESSFANW, 3188 SPE_BUILTIN_EVMHESSIAAW, 3189 SPE_BUILTIN_EVMHESSIANW, 3190 SPE_BUILTIN_EVMHEUMI, 3191 SPE_BUILTIN_EVMHEUMIA, 3192 SPE_BUILTIN_EVMHEUMIAAW, 3193 SPE_BUILTIN_EVMHEUMIANW, 3194 SPE_BUILTIN_EVMHEUSIAAW, 3195 SPE_BUILTIN_EVMHEUSIANW, 3196 SPE_BUILTIN_EVMHOGSMFAA, 3197 SPE_BUILTIN_EVMHOGSMFAN, 3198 SPE_BUILTIN_EVMHOGSMIAA, 3199 SPE_BUILTIN_EVMHOGSMIAN, 3200 SPE_BUILTIN_EVMHOGUMIAA, 3201 SPE_BUILTIN_EVMHOGUMIAN, 3202 SPE_BUILTIN_EVMHOSMF, 3203 SPE_BUILTIN_EVMHOSMFA, 3204 SPE_BUILTIN_EVMHOSMFAAW, 3205 SPE_BUILTIN_EVMHOSMFANW, 3206 SPE_BUILTIN_EVMHOSMI, 3207 SPE_BUILTIN_EVMHOSMIA, 3208 SPE_BUILTIN_EVMHOSMIAAW, 3209 SPE_BUILTIN_EVMHOSMIANW, 3210 SPE_BUILTIN_EVMHOSSF, 3211 SPE_BUILTIN_EVMHOSSFA, 3212 SPE_BUILTIN_EVMHOSSFAAW, 3213 SPE_BUILTIN_EVMHOSSFANW, 3214 SPE_BUILTIN_EVMHOSSIAAW, 3215 SPE_BUILTIN_EVMHOSSIANW, 3216 SPE_BUILTIN_EVMHOUMI, 3217 SPE_BUILTIN_EVMHOUMIA, 3218 SPE_BUILTIN_EVMHOUMIAAW, 3219 SPE_BUILTIN_EVMHOUMIANW, 3220 SPE_BUILTIN_EVMHOUSIAAW, 3221 SPE_BUILTIN_EVMHOUSIANW, 3222 SPE_BUILTIN_EVMWHSMF, 3223 SPE_BUILTIN_EVMWHSMFA, 3224 SPE_BUILTIN_EVMWHSMI, 3225 SPE_BUILTIN_EVMWHSMIA, 3226 SPE_BUILTIN_EVMWHSSF, 3227 SPE_BUILTIN_EVMWHSSFA, 3228 SPE_BUILTIN_EVMWHUMI, 3229 SPE_BUILTIN_EVMWHUMIA, 3230 SPE_BUILTIN_EVMWLSMIAAW, 3231 SPE_BUILTIN_EVMWLSMIANW, 3232 SPE_BUILTIN_EVMWLSSIAAW, 3233 SPE_BUILTIN_EVMWLSSIANW, 3234 SPE_BUILTIN_EVMWLUMI, 3235 SPE_BUILTIN_EVMWLUMIA, 3236 SPE_BUILTIN_EVMWLUMIAAW, 3237 SPE_BUILTIN_EVMWLUMIANW, 3238 SPE_BUILTIN_EVMWLUSIAAW, 3239 SPE_BUILTIN_EVMWLUSIANW, 3240 SPE_BUILTIN_EVMWSMF, 3241 SPE_BUILTIN_EVMWSMFA, 3242 SPE_BUILTIN_EVMWSMFAA, 3243 SPE_BUILTIN_EVMWSMFAN, 3244 SPE_BUILTIN_EVMWSMI, 3245 SPE_BUILTIN_EVMWSMIA, 3246 SPE_BUILTIN_EVMWSMIAA, 3247 SPE_BUILTIN_EVMWSMIAN, 3248 SPE_BUILTIN_EVMWHSSFAA, 3249 SPE_BUILTIN_EVMWSSF, 3250 SPE_BUILTIN_EVMWSSFA, 3251 SPE_BUILTIN_EVMWSSFAA, 3252 SPE_BUILTIN_EVMWSSFAN, 3253 SPE_BUILTIN_EVMWUMI, 3254 SPE_BUILTIN_EVMWUMIA, 3255 SPE_BUILTIN_EVMWUMIAA, 3256 SPE_BUILTIN_EVMWUMIAN, 3257 SPE_BUILTIN_EVNAND, 3258 SPE_BUILTIN_EVNOR, 3259 SPE_BUILTIN_EVOR, 3260 SPE_BUILTIN_EVORC, 3261 SPE_BUILTIN_EVRLW, 3262 SPE_BUILTIN_EVSLW, 3263 SPE_BUILTIN_EVSRWS, 3264 SPE_BUILTIN_EVSRWU, 3265 SPE_BUILTIN_EVSTDDX, 3266 SPE_BUILTIN_EVSTDHX, 3267 SPE_BUILTIN_EVSTDWX, 3268 SPE_BUILTIN_EVSTWHEX, 3269 SPE_BUILTIN_EVSTWHOX, 3270 SPE_BUILTIN_EVSTWWEX, 3271 SPE_BUILTIN_EVSTWWOX, 3272 SPE_BUILTIN_EVSUBFW, 3273 SPE_BUILTIN_EVXOR, 3274 SPE_BUILTIN_EVABS, 3275 SPE_BUILTIN_EVADDSMIAAW, 3276 SPE_BUILTIN_EVADDSSIAAW, 3277 SPE_BUILTIN_EVADDUMIAAW, 3278 SPE_BUILTIN_EVADDUSIAAW, 3279 SPE_BUILTIN_EVCNTLSW, 3280 SPE_BUILTIN_EVCNTLZW, 3281 SPE_BUILTIN_EVEXTSB, 3282 SPE_BUILTIN_EVEXTSH, 3283 SPE_BUILTIN_EVFSABS, 3284 SPE_BUILTIN_EVFSCFSF, 3285 SPE_BUILTIN_EVFSCFSI, 3286 SPE_BUILTIN_EVFSCFUF, 3287 SPE_BUILTIN_EVFSCFUI, 3288 SPE_BUILTIN_EVFSCTSF, 3289 SPE_BUILTIN_EVFSCTSI, 3290 SPE_BUILTIN_EVFSCTSIZ, 3291 SPE_BUILTIN_EVFSCTUF, 3292 SPE_BUILTIN_EVFSCTUI, 3293 SPE_BUILTIN_EVFSCTUIZ, 3294 SPE_BUILTIN_EVFSNABS, 3295 SPE_BUILTIN_EVFSNEG, 3296 SPE_BUILTIN_EVMRA, 3297 SPE_BUILTIN_EVNEG, 3298 SPE_BUILTIN_EVRNDW, 3299 SPE_BUILTIN_EVSUBFSMIAAW, 3300 SPE_BUILTIN_EVSUBFSSIAAW, 3301 SPE_BUILTIN_EVSUBFUMIAAW, 3302 SPE_BUILTIN_EVSUBFUSIAAW, 3303 SPE_BUILTIN_EVADDIW, 3304 SPE_BUILTIN_EVLDD, 3305 SPE_BUILTIN_EVLDH, 3306 SPE_BUILTIN_EVLDW, 3307 SPE_BUILTIN_EVLHHESPLAT, 3308 SPE_BUILTIN_EVLHHOSSPLAT, 3309 SPE_BUILTIN_EVLHHOUSPLAT, 3310 SPE_BUILTIN_EVLWHE, 3311 SPE_BUILTIN_EVLWHOS, 3312 SPE_BUILTIN_EVLWHOU, 3313 SPE_BUILTIN_EVLWHSPLAT, 3314 SPE_BUILTIN_EVLWWSPLAT, 3315 SPE_BUILTIN_EVRLWI, 3316 SPE_BUILTIN_EVSLWI, 3317 SPE_BUILTIN_EVSRWIS, 3318 SPE_BUILTIN_EVSRWIU, 3319 SPE_BUILTIN_EVSTDD, 3320 SPE_BUILTIN_EVSTDH, 3321 SPE_BUILTIN_EVSTDW, 3322 SPE_BUILTIN_EVSTWHE, 3323 SPE_BUILTIN_EVSTWHO, 3324 SPE_BUILTIN_EVSTWWE, 3325 SPE_BUILTIN_EVSTWWO, 3326 SPE_BUILTIN_EVSUBIFW, 3327 3328 /* Compares. */ 3329 SPE_BUILTIN_EVCMPEQ, 3330 SPE_BUILTIN_EVCMPGTS, 3331 SPE_BUILTIN_EVCMPGTU, 3332 SPE_BUILTIN_EVCMPLTS, 3333 SPE_BUILTIN_EVCMPLTU, 3334 SPE_BUILTIN_EVFSCMPEQ, 3335 SPE_BUILTIN_EVFSCMPGT, 3336 SPE_BUILTIN_EVFSCMPLT, 3337 SPE_BUILTIN_EVFSTSTEQ, 3338 SPE_BUILTIN_EVFSTSTGT, 3339 SPE_BUILTIN_EVFSTSTLT, 3340 3341 /* EVSEL compares. */ 3342 SPE_BUILTIN_EVSEL_CMPEQ, 3343 SPE_BUILTIN_EVSEL_CMPGTS, 3344 SPE_BUILTIN_EVSEL_CMPGTU, 3345 SPE_BUILTIN_EVSEL_CMPLTS, 3346 SPE_BUILTIN_EVSEL_CMPLTU, 3347 SPE_BUILTIN_EVSEL_FSCMPEQ, 3348 SPE_BUILTIN_EVSEL_FSCMPGT, 3349 SPE_BUILTIN_EVSEL_FSCMPLT, 3350 SPE_BUILTIN_EVSEL_FSTSTEQ, 3351 SPE_BUILTIN_EVSEL_FSTSTGT, 3352 SPE_BUILTIN_EVSEL_FSTSTLT, 3353 3354 SPE_BUILTIN_EVSPLATFI, 3355 SPE_BUILTIN_EVSPLATI, 3356 SPE_BUILTIN_EVMWHSSMAA, 3357 SPE_BUILTIN_EVMWHSMFAA, 3358 SPE_BUILTIN_EVMWHSMIAA, 3359 SPE_BUILTIN_EVMWHUSIAA, 3360 SPE_BUILTIN_EVMWHUMIAA, 3361 SPE_BUILTIN_EVMWHSSFAN, 3362 SPE_BUILTIN_EVMWHSSIAN, 3363 SPE_BUILTIN_EVMWHSMFAN, 3364 SPE_BUILTIN_EVMWHSMIAN, 3365 SPE_BUILTIN_EVMWHUSIAN, 3366 SPE_BUILTIN_EVMWHUMIAN, 3367 SPE_BUILTIN_EVMWHGSSFAA, 3368 SPE_BUILTIN_EVMWHGSMFAA, 3369 SPE_BUILTIN_EVMWHGSMIAA, 3370 SPE_BUILTIN_EVMWHGUMIAA, 3371 SPE_BUILTIN_EVMWHGSSFAN, 3372 SPE_BUILTIN_EVMWHGSMFAN, 3373 SPE_BUILTIN_EVMWHGSMIAN, 3374 SPE_BUILTIN_EVMWHGUMIAN, 3375 SPE_BUILTIN_MTSPEFSCR, 3376 SPE_BUILTIN_MFSPEFSCR, 3377 SPE_BUILTIN_BRINC 3378 }; 3379