1 /*
2 * QEMU PowerPC Booke hardware System Emulator
3 *
4 * Copyright (c) 2011 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "cpu.h"
27 #include "hw/ppc/ppc.h"
28 #include "qemu/timer.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
31 #include "hw/loader.h"
32 #include "kvm_ppc.h"
33
booke_set_tlb(ppcemb_tlb_t * tlb,target_ulong va,hwaddr pa,target_ulong size)34 void booke_set_tlb(ppcemb_tlb_t *tlb, target_ulong va, hwaddr pa,
35 target_ulong size)
36 {
37 tlb->attr = 0;
38 tlb->prot = PAGE_RWX << 4 | PAGE_VALID;
39 tlb->size = size;
40 tlb->EPN = va & TARGET_PAGE_MASK;
41 tlb->RPN = pa & TARGET_PAGE_MASK;
42 tlb->PID = 0;
43 }
44
45 /* Timer Control Register */
46
47 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
48 #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
49 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
50 #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
51 #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
52 #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
53 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
54 #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
55 #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
56 #define TCR_ARE (1U << 22) /* Auto-Reload Enable */
57
58 /* Timer Control Register (e500 specific fields) */
59
60 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
61 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
62 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
63 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
64
65 /* Timer Status Register */
66
67 #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
68 #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
69 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
70 #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
71 #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
72 #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
73
74 typedef struct booke_timer_t booke_timer_t;
75 struct booke_timer_t {
76
77 uint64_t fit_next;
78 QEMUTimer *fit_timer;
79
80 uint64_t wdt_next;
81 QEMUTimer *wdt_timer;
82
83 uint32_t flags;
84 };
85
booke_update_irq(PowerPCCPU * cpu)86 static void booke_update_irq(PowerPCCPU *cpu)
87 {
88 CPUPPCState *env = &cpu->env;
89
90 ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
91 (env->spr[SPR_BOOKE_TSR] & TSR_DIS
92 && env->spr[SPR_BOOKE_TCR] & TCR_DIE));
93
94 ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
95 (env->spr[SPR_BOOKE_TSR] & TSR_WIS
96 && env->spr[SPR_BOOKE_TCR] & TCR_WIE));
97
98 ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
99 (env->spr[SPR_BOOKE_TSR] & TSR_FIS
100 && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
101 }
102
103 /* Return the location of the bit of time base at which the FIT will raise an
104 interrupt */
booke_get_fit_target(CPUPPCState * env,ppc_tb_t * tb_env)105 static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
106 {
107 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
108
109 if (tb_env->flags & PPC_TIMER_E500) {
110 /* e500 Fixed-interval timer period extension */
111 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
112 >> TCR_E500_FPEXT_SHIFT;
113 fp = 63 - (fp | fpext << 2);
114 } else {
115 fp = env->fit_period[fp];
116 }
117
118 return fp;
119 }
120
121 /* Return the location of the bit of time base at which the WDT will raise an
122 interrupt */
booke_get_wdt_target(CPUPPCState * env,ppc_tb_t * tb_env)123 static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
124 {
125 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
126
127 if (tb_env->flags & PPC_TIMER_E500) {
128 /* e500 Watchdog timer period extension */
129 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
130 >> TCR_E500_WPEXT_SHIFT;
131 wp = 63 - (wp | wpext << 2);
132 } else {
133 wp = env->wdt_period[wp];
134 }
135
136 return wp;
137 }
138
booke_update_fixed_timer(CPUPPCState * env,uint8_t target_bit,uint64_t * next,QEMUTimer * timer,int tsr_bit)139 static void booke_update_fixed_timer(CPUPPCState *env,
140 uint8_t target_bit,
141 uint64_t *next,
142 QEMUTimer *timer,
143 int tsr_bit)
144 {
145 ppc_tb_t *tb_env = env->tb_env;
146 uint64_t delta_tick, ticks = 0;
147 uint64_t tb;
148 uint64_t period;
149 uint64_t now;
150
151 if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
152 /*
153 * Don't arm the timer again when the guest has the current
154 * interrupt still pending. Wait for it to ack it.
155 */
156 return;
157 }
158
159 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
160 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
161 period = 1ULL << target_bit;
162 delta_tick = period - (tb & (period - 1));
163
164 /* the timer triggers only when the selected bit toggles from 0 to 1 */
165 if (tb & period) {
166 ticks = period;
167 }
168
169 if (ticks + delta_tick < ticks) {
170 /* Overflow, so assume the biggest number we can express. */
171 ticks = UINT64_MAX;
172 } else {
173 ticks += delta_tick;
174 }
175
176 *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
177 if ((*next < now) || (*next > INT64_MAX)) {
178 /* Overflow, so assume the biggest number the qemu timer supports. */
179 *next = INT64_MAX;
180 }
181
182 /* XXX: If expire time is now. We can't run the callback because we don't
183 * have access to it. So we just set the timer one nanosecond later.
184 */
185
186 if (*next == now) {
187 (*next)++;
188 } else {
189 /*
190 * There's no point to fake any granularity that's more fine grained
191 * than milliseconds. Anything beyond that just overloads the system.
192 */
193 *next = MAX(*next, now + SCALE_MS);
194 }
195
196 /* Fire the next timer */
197 timer_mod(timer, *next);
198 }
199
booke_decr_cb(void * opaque)200 static void booke_decr_cb(void *opaque)
201 {
202 PowerPCCPU *cpu = opaque;
203 CPUPPCState *env = &cpu->env;
204
205 env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
206 booke_update_irq(cpu);
207
208 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
209 /* Do not reload 0, it is already there. It would just trigger
210 * the timer again and lead to infinite loop */
211 if (env->spr[SPR_BOOKE_DECAR] != 0) {
212 /* Auto Reload */
213 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
214 }
215 }
216 }
217
booke_fit_cb(void * opaque)218 static void booke_fit_cb(void *opaque)
219 {
220 PowerPCCPU *cpu = opaque;
221 CPUPPCState *env = &cpu->env;
222 ppc_tb_t *tb_env;
223 booke_timer_t *booke_timer;
224
225 tb_env = env->tb_env;
226 booke_timer = tb_env->opaque;
227 env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
228
229 booke_update_irq(cpu);
230
231 booke_update_fixed_timer(env,
232 booke_get_fit_target(env, tb_env),
233 &booke_timer->fit_next,
234 booke_timer->fit_timer,
235 TSR_FIS);
236 }
237
booke_wdt_cb(void * opaque)238 static void booke_wdt_cb(void *opaque)
239 {
240 PowerPCCPU *cpu = opaque;
241 CPUPPCState *env = &cpu->env;
242 ppc_tb_t *tb_env;
243 booke_timer_t *booke_timer;
244
245 tb_env = env->tb_env;
246 booke_timer = tb_env->opaque;
247
248 /* TODO: There's lots of complicated stuff to do here */
249
250 booke_update_irq(cpu);
251
252 booke_update_fixed_timer(env,
253 booke_get_wdt_target(env, tb_env),
254 &booke_timer->wdt_next,
255 booke_timer->wdt_timer,
256 TSR_WIS);
257 }
258
store_booke_tsr(CPUPPCState * env,target_ulong val)259 void store_booke_tsr(CPUPPCState *env, target_ulong val)
260 {
261 PowerPCCPU *cpu = env_archcpu(env);
262 ppc_tb_t *tb_env = env->tb_env;
263 booke_timer_t *booke_timer = tb_env->opaque;
264
265 env->spr[SPR_BOOKE_TSR] &= ~val;
266 kvmppc_clear_tsr_bits(cpu, val);
267
268 if (val & TSR_FIS) {
269 booke_update_fixed_timer(env,
270 booke_get_fit_target(env, tb_env),
271 &booke_timer->fit_next,
272 booke_timer->fit_timer,
273 TSR_FIS);
274 }
275
276 if (val & TSR_WIS) {
277 booke_update_fixed_timer(env,
278 booke_get_wdt_target(env, tb_env),
279 &booke_timer->wdt_next,
280 booke_timer->wdt_timer,
281 TSR_WIS);
282 }
283
284 booke_update_irq(cpu);
285 }
286
store_booke_tcr(CPUPPCState * env,target_ulong val)287 void store_booke_tcr(CPUPPCState *env, target_ulong val)
288 {
289 PowerPCCPU *cpu = env_archcpu(env);
290 ppc_tb_t *tb_env = env->tb_env;
291 booke_timer_t *booke_timer = tb_env->opaque;
292
293 env->spr[SPR_BOOKE_TCR] = val;
294 kvmppc_set_tcr(cpu);
295
296 booke_update_irq(cpu);
297
298 booke_update_fixed_timer(env,
299 booke_get_fit_target(env, tb_env),
300 &booke_timer->fit_next,
301 booke_timer->fit_timer,
302 TSR_FIS);
303
304 booke_update_fixed_timer(env,
305 booke_get_wdt_target(env, tb_env),
306 &booke_timer->wdt_next,
307 booke_timer->wdt_timer,
308 TSR_WIS);
309 }
310
ppc_booke_timer_reset_handle(void * opaque)311 static void ppc_booke_timer_reset_handle(void *opaque)
312 {
313 PowerPCCPU *cpu = opaque;
314 CPUPPCState *env = &cpu->env;
315
316 store_booke_tcr(env, 0);
317 store_booke_tsr(env, -1);
318 }
319
320 /*
321 * This function will be called whenever the CPU state changes.
322 * CPU states are defined "typedef enum RunState".
323 * Regarding timer, When CPU state changes to running after debug halt
324 * or similar cases which takes time then in between final watchdog
325 * expiry happenes. This will cause exit to QEMU and configured watchdog
326 * action will be taken. To avoid this we always clear the watchdog state when
327 * state changes to running.
328 */
cpu_state_change_handler(void * opaque,bool running,RunState state)329 static void cpu_state_change_handler(void *opaque, bool running, RunState state)
330 {
331 PowerPCCPU *cpu = opaque;
332 CPUPPCState *env = &cpu->env;
333
334 if (!running) {
335 return;
336 }
337
338 /*
339 * Clear watchdog interrupt condition by clearing TSR.
340 */
341 store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
342 }
343
ppc_booke_timers_init(PowerPCCPU * cpu,uint32_t freq,uint32_t flags)344 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
345 {
346 ppc_tb_t *tb_env;
347 booke_timer_t *booke_timer;
348 int ret = 0;
349
350 tb_env = g_new0(ppc_tb_t, 1);
351 booke_timer = g_new0(booke_timer_t, 1);
352
353 cpu->env.tb_env = tb_env;
354 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
355
356 tb_env->tb_freq = freq;
357 tb_env->decr_freq = freq;
358 tb_env->opaque = booke_timer;
359 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);
360
361 booke_timer->fit_timer =
362 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
363 booke_timer->wdt_timer =
364 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);
365
366 ret = kvmppc_booke_watchdog_enable(cpu);
367
368 if (ret) {
369 /* TODO: Start the QEMU emulated watchdog if not running on KVM.
370 * Also start the QEMU emulated watchdog if KVM does not support
371 * emulated watchdog or somehow it is not enabled (supported but
372 * not enabled is though some bug and requires debugging :)).
373 */
374 }
375
376 qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
377
378 qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
379 }
380