1 /* $OpenBSD: if_tlreg.h,v 1.10 2014/01/31 06:05:40 brad Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: src/sys/pci/if_tlreg.h,v 1.17 2001/02/09 06:11:21 bmilekic Exp $ 35 */ 36 37 38 struct tl_type { 39 u_int16_t tl_vid; 40 u_int16_t tl_did; 41 char *tl_name; 42 }; 43 44 /* 45 * ThunderLAN TX/RX list format. The TX and RX lists are pretty much 46 * identical: the list begins with a 32-bit forward pointer which points 47 * at the next list in the chain, followed by 16 bits for the total 48 * frame size, and a 16 bit status field. This is followed by a series 49 * of 10 32-bit data count/data address pairs that point to the fragments 50 * that make up the complete frame. 51 */ 52 53 #define TL_MAXFRAGS 10 54 #define TL_RX_LIST_CNT 20 55 #define TL_TX_LIST_CNT 64 56 #define TL_MIN_FRAMELEN 128 57 58 struct tl_frag { 59 u_int32_t tlist_dcnt; 60 u_int32_t tlist_dadr; 61 }; 62 63 struct tl_list { 64 u_int32_t tlist_fptr; /* phys address of next list */ 65 u_int16_t tlist_cstat; /* status word */ 66 u_int16_t tlist_frsize; /* size of data in frame */ 67 struct tl_frag tl_frag[TL_MAXFRAGS]; 68 }; 69 70 /* 71 * This is a special case of an RX list. By setting the One_Frag 72 * bit in the NETCONFIG register, the driver can force the ThunderLAN 73 * chip to use only one fragment when DMAing RX frames. 74 */ 75 76 struct tl_list_onefrag { 77 u_int32_t tlist_fptr; 78 u_int16_t tlist_cstat; 79 u_int16_t tlist_frsize; 80 struct tl_frag tl_frag; 81 }; 82 83 struct tl_list_data { 84 struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT]; 85 struct tl_list tl_tx_list[TL_TX_LIST_CNT]; 86 unsigned char tl_pad[TL_MIN_FRAMELEN]; 87 }; 88 89 struct tl_chain { 90 struct tl_list *tl_ptr; 91 struct mbuf *tl_mbuf; 92 struct tl_chain *tl_next; 93 }; 94 95 struct tl_chain_onefrag { 96 struct tl_list_onefrag *tl_ptr; 97 struct mbuf *tl_mbuf; 98 struct tl_chain_onefrag *tl_next; 99 }; 100 101 struct tl_chain_data { 102 struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT]; 103 struct tl_chain tl_tx_chain[TL_TX_LIST_CNT]; 104 105 struct tl_chain_onefrag *tl_rx_head; 106 struct tl_chain_onefrag *tl_rx_tail; 107 108 struct tl_chain *tl_tx_head; 109 struct tl_chain *tl_tx_tail; 110 struct tl_chain *tl_tx_free; 111 }; 112 113 struct tl_products { 114 u_int16_t tp_vend; 115 u_int16_t tp_prod; 116 u_int32_t tp_tlphymedia; 117 }; 118 119 struct tl_softc { 120 struct device sc_dev; /* generic device structure */ 121 void * sc_ih; /* interrupt handler cookie */ 122 struct arpcom arpcom; /* interface info */ 123 struct ifmedia ifmedia; /* media info */ 124 struct timeout tl_stats_tmo, tl_wait_tmo; 125 bus_space_handle_t tl_bhandle; 126 bus_space_tag_t tl_btag; 127 bus_dma_tag_t sc_dmat; 128 struct tl_type *tl_dinfo; /* ThunderLAN adapter info */ 129 struct tl_type *tl_pinfo; /* PHY info struct */ 130 u_int8_t tl_ctlr; /* chip number */ 131 u_int8_t tl_eeaddr; 132 struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */ 133 struct tl_chain_data tl_cdata; 134 u_int8_t tl_txeoc; 135 u_int8_t tl_bitrate; 136 struct mii_data sc_mii; 137 const struct tl_products *tl_product; 138 }; 139 140 /* 141 * Transmit interrupt threshold. 142 */ 143 #define TX_THR 0x00000004 144 145 /* 146 * General constants that are fun to know. 147 * 148 * The ThunderLAN controller is made by Texas Instruments. The 149 * manual indicates that if the EEPROM checksum fails, the PCI 150 * vendor and device ID registers will be loaded with TI-specific 151 * values. 152 */ 153 #define TI_VENDORID 0x104C 154 #define TI_DEVICEID_THUNDERLAN 0x0500 155 156 /* 157 * These are the PCI vendor and device IDs for Compaq ethernet 158 * adapters based on the ThunderLAN controller. 159 */ 160 #define COMPAQ_VENDORID 0x0E11 161 #define COMPAQ_DEVICEID_NETEL_10_100 0xAE32 162 #define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33 163 #define COMPAQ_DEVICEID_NETEL_10 0xAE34 164 #define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35 165 #define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40 166 #define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43 167 #define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011 168 #define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012 169 #define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030 170 #define COMPAQ_DEVICEID_NETFLEX_3P 0xF130 171 #define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150 172 173 /* 174 * These are the PCI vendor and device IDs for Olicom 175 * adapters based on the ThunderLAN controller. 176 */ 177 #define OLICOM_VENDORID 0x108D 178 #define OLICOM_DEVICEID_OC2183 0x0013 179 #define OLICOM_DEVICEID_OC2325 0x0012 180 #define OLICOM_DEVICEID_OC2326 0x0014 181 182 /* 183 * PCI low memory base and low I/O base 184 */ 185 #define TL_PCI_LOIO 0x10 186 #define TL_PCI_LOMEM 0x14 187 188 /* 189 * PCI latency timer (it's actually 0x0D, but we want a value 190 * that's longword aligned). 191 */ 192 #define TL_PCI_LATENCY_TIMER 0x0C 193 194 #define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */ 195 #define TL_DIO_RAM_SEL 0x4000 /* RAM address select */ 196 #define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */ 197 198 /* 199 * Interrupt types 200 */ 201 #define TL_INTR_INVALID 0x0 202 #define TL_INTR_TXEOF 0x1 203 #define TL_INTR_STATOFLOW 0x2 204 #define TL_INTR_RXEOF 0x3 205 #define TL_INTR_DUMMY 0x4 206 #define TL_INTR_TXEOC 0x5 207 #define TL_INTR_ADCHK 0x6 208 #define TL_INTR_RXEOC 0x7 209 210 #define TL_INT_MASK 0x001C 211 #define TL_VEC_MASK 0x1FE0 212 /* 213 * Host command register bits 214 */ 215 #define TL_CMD_GO 0x80000000 216 #define TL_CMD_STOP 0x40000000 217 #define TL_CMD_ACK 0x20000000 218 #define TL_CMD_CHSEL7 0x10000000 219 #define TL_CMD_CHSEL6 0x08000000 220 #define TL_CMD_CHSEL5 0x04000000 221 #define TL_CMD_CHSEL4 0x02000000 222 #define TL_CMD_CHSEL3 0x01000000 223 #define TL_CMD_CHSEL2 0x00800000 224 #define TL_CMD_CHSEL1 0x00400000 225 #define TL_CMD_CHSEL0 0x00200000 226 #define TL_CMD_EOC 0x00100000 227 #define TL_CMD_RT 0x00080000 228 #define TL_CMD_NES 0x00040000 229 #define TL_CMD_ZERO0 0x00020000 230 #define TL_CMD_ZERO1 0x00010000 231 #define TL_CMD_ADRST 0x00008000 232 #define TL_CMD_LDTMR 0x00004000 233 #define TL_CMD_LDTHR 0x00002000 234 #define TL_CMD_REQINT 0x00001000 235 #define TL_CMD_INTSOFF 0x00000800 236 #define TL_CMD_INTSON 0x00000400 237 #define TL_CMD_RSVD0 0x00000200 238 #define TL_CMD_RSVD1 0x00000100 239 #define TL_CMD_ACK7 0x00000080 240 #define TL_CMD_ACK6 0x00000040 241 #define TL_CMD_ACK5 0x00000020 242 #define TL_CMD_ACK4 0x00000010 243 #define TL_CMD_ACK3 0x00000008 244 #define TL_CMD_ACK2 0x00000004 245 #define TL_CMD_ACK1 0x00000002 246 #define TL_CMD_ACK0 0x00000001 247 248 #define TL_CMD_CHSEL_MASK 0x01FE0000 249 #define TL_CMD_ACK_MASK 0xFF 250 251 /* 252 * EEPROM address where station address resides. 253 */ 254 #define TL_EEPROM_EADDR 0x83 255 #define TL_EEPROM_EADDR2 0x99 256 #define TL_EEPROM_EADDR3 0xAF 257 #define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different 258 address than Compaqs. */ 259 /* 260 * ThunderLAN host command register offsets. 261 * (Can be accessed either by IO ports or memory map.) 262 */ 263 #define TL_HOSTCMD 0x00 264 #define TL_CH_PARM 0x04 265 #define TL_DIO_ADDR 0x08 266 #define TL_HOST_INT 0x0A 267 #define TL_DIO_DATA 0x0C 268 269 /* 270 * ThunderLAN internal registers 271 */ 272 #define TL_NETCMD 0x00 273 #define TL_NETSIO 0x01 274 #define TL_NETSTS 0x02 275 #define TL_NETMASK 0x03 276 277 #define TL_NETCONFIG 0x04 278 #define TL_MANTEST 0x06 279 280 #define TL_VENID_LSB 0x08 281 #define TL_VENID_MSB 0x09 282 #define TL_DEVID_LSB 0x0A 283 #define TL_DEVID_MSB 0x0B 284 285 #define TL_REVISION 0x0C 286 #define TL_SUBCLASS 0x0D 287 #define TL_MINLAT 0x0E 288 #define TL_MAXLAT 0x0F 289 290 #define TL_AREG0_B5 0x10 291 #define TL_AREG0_B4 0x11 292 #define TL_AREG0_B3 0x12 293 #define TL_AREG0_B2 0x13 294 295 #define TL_AREG0_B1 0x14 296 #define TL_AREG0_B0 0x15 297 #define TL_AREG1_B5 0x16 298 #define TL_AREG1_B4 0x17 299 300 #define TL_AREG1_B3 0x18 301 #define TL_AREG1_B2 0x19 302 #define TL_AREG1_B1 0x1A 303 #define TL_AREG1_B0 0x1B 304 305 #define TL_AREG2_B5 0x1C 306 #define TL_AREG2_B4 0x1D 307 #define TL_AREG2_B3 0x1E 308 #define TL_AREG2_B2 0x1F 309 310 #define TL_AREG2_B1 0x20 311 #define TL_AREG2_B0 0x21 312 #define TL_AREG3_B5 0x22 313 #define TL_AREG3_B4 0x23 314 315 #define TL_AREG3_B3 0x24 316 #define TL_AREG3_B2 0x25 317 #define TL_AREG3_B1 0x26 318 #define TL_AREG3_B0 0x27 319 320 #define TL_HASH1 0x28 321 #define TL_HASH2 0x2C 322 #define TL_TXGOODFRAMES 0x30 323 #define TL_TXUNDERRUN 0x33 324 #define TL_RXGOODFRAMES 0x34 325 #define TL_RXOVERRUN 0x37 326 #define TL_DEFEREDTX 0x38 327 #define TL_CRCERROR 0x3A 328 #define TL_CODEERROR 0x3B 329 #define TL_MULTICOLTX 0x3C 330 #define TL_SINGLECOLTX 0x3E 331 #define TL_EXCESSIVECOL 0x40 332 #define TL_LATECOL 0x41 333 #define TL_CARRIERLOSS 0x42 334 #define TL_ACOMMIT 0x43 335 #define TL_LDREG 0x44 336 #define TL_BSIZEREG 0x45 337 #define TL_MAXRX 0x46 338 339 /* 340 * ThunderLAN SIO register bits 341 */ 342 #define TL_SIO_MINTEN 0x80 343 #define TL_SIO_ECLOK 0x40 344 #define TL_SIO_ETXEN 0x20 345 #define TL_SIO_EDATA 0x10 346 #define TL_SIO_NMRST 0x08 347 #define TL_SIO_MCLK 0x04 348 #define TL_SIO_MTXEN 0x02 349 #define TL_SIO_MDATA 0x01 350 351 /* 352 * Thunderlan NETCONFIG bits 353 */ 354 #define TL_CFG_RCLKTEST 0x8000 355 #define TL_CFG_TCLKTEST 0x4000 356 #define TL_CFG_BITRATE 0x2000 357 #define TL_CFG_RXCRC 0x1000 358 #define TL_CFG_PEF 0x0800 359 #define TL_CFG_ONEFRAG 0x0400 360 #define TL_CFG_ONECHAN 0x0200 361 #define TL_CFG_MTEST 0x0100 362 #define TL_CFG_PHYEN 0x0080 363 #define TL_CFG_MACSEL6 0x0040 364 #define TL_CFG_MACSEL5 0x0020 365 #define TL_CFG_MACSEL4 0x0010 366 #define TL_CFG_MACSEL3 0x0008 367 #define TL_CFG_MACSEL2 0x0004 368 #define TL_CFG_MACSEL1 0x0002 369 #define TL_CFG_MACSEL0 0x0001 370 371 /* 372 * ThunderLAN NETSTS bits 373 */ 374 #define TL_STS_MIRQ 0x80 375 #define TL_STS_HBEAT 0x40 376 #define TL_STS_TXSTOP 0x20 377 #define TL_STS_RXSTOP 0x10 378 379 /* 380 * ThunderLAN NETCMD bits 381 */ 382 #define TL_CMD_NRESET 0x80 383 #define TL_CMD_NWRAP 0x40 384 #define TL_CMD_CSF 0x20 385 #define TL_CMD_CAF 0x10 386 #define TL_CMD_NOBRX 0x08 387 #define TL_CMD_DUPLEX 0x04 388 #define TL_CMD_TRFRAM 0x02 389 #define TL_CMD_TXPACE 0x01 390 391 /* 392 * ThunderLAN NETMASK bits 393 */ 394 #define TL_MASK_MASK7 0x80 395 #define TL_MASK_MASK6 0x40 396 #define TL_MASK_MASK5 0x20 397 #define TL_MASK_MASK4 0x10 398 399 /* 400 * MII frame format 401 */ 402 #ifdef ANSI_DOESNT_ALLOW_BITFIELDS 403 struct tl_mii_frame { 404 u_int16_t mii_stdelim:2, 405 mii_opcode:2, 406 mii_phyaddr:5, 407 mii_regaddr:5, 408 mii_turnaround:2; 409 u_int16_t mii_data; 410 }; 411 #else 412 struct tl_mii_frame { 413 u_int8_t mii_stdelim; 414 u_int8_t mii_opcode; 415 u_int8_t mii_phyaddr; 416 u_int8_t mii_regaddr; 417 u_int8_t mii_turnaround; 418 u_int16_t mii_data; 419 }; 420 #endif 421 /* 422 * MII constants 423 */ 424 #define TL_MII_STARTDELIM 0x01 425 #define TL_MII_READOP 0x02 426 #define TL_MII_WRITEOP 0x01 427 #define TL_MII_TURNAROUND 0x02 428 429 #define TL_LAST_FRAG 0x80000000 430 #define TL_CSTAT_UNUSED 0x8000 431 #define TL_CSTAT_FRAMECMP 0x4000 432 #define TL_CSTAT_READY 0x3000 433 #define TL_CSTAT_UNUSED13 0x2000 434 #define TL_CSTAT_UNUSED12 0x1000 435 #define TL_CSTAT_EOC 0x0800 436 #define TL_CSTAT_RXERROR 0x0400 437 #define TL_CSTAT_PASSCRC 0x0200 438 #define TL_CSTAT_DPRIO 0x0100 439 440 #define TL_FRAME_MASK 0x00FFFFFF 441 #define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK) 442 #define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24) 443 #define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK) 444 #define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24) 445 446 struct tl_stats { 447 u_int32_t tl_txstat; 448 u_int32_t tl_rxstat; 449 u_int16_t tl_deferred; 450 u_int8_t tl_crc_errors; 451 u_int8_t tl_code_errors; 452 u_int16_t tl_tx_multi_collision; 453 u_int16_t tl_tx_single_collision; 454 u_int8_t tl_excessive_collision; 455 u_int8_t tl_late_collision; 456 u_int8_t tl_carrier_loss; 457 u_int8_t acommit; 458 }; 459 460 /* 461 * ACOMMIT register bits. These are used only when a bitrate 462 * PHY is selected ('bitrate' bit in netconfig register is set). 463 */ 464 #define TL_AC_MTXER 0x01 /* reserved */ 465 #define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */ 466 #define TL_AC_MTXD2 0x04 /* loopback disable */ 467 #define TL_AC_MTXD3 0x08 /* full duplex disable */ 468 469 #define TL_AC_TXTHRESH 0xF0 470 #define TL_AC_TXTHRESH_16LONG 0x00 471 #define TL_AC_TXTHRESH_32LONG 0x10 472 #define TL_AC_TXTHRESH_64LONG 0x20 473 #define TL_AC_TXTHRESH_128LONG 0x30 474 #define TL_AC_TXTHRESH_256LONG 0x40 475 #define TL_AC_TXTHRESH_WHOLEPKT 0x50 476 477 /* 478 * PCI burst size register (TL_BSIZEREG). 479 */ 480 #define TL_RXBURST 0x0F 481 #define TL_TXBURST 0xF0 482 483 #define TL_RXBURST_4LONG 0x00 484 #define TL_RXBURST_8LONG 0x01 485 #define TL_RXBURST_16LONG 0x02 486 #define TL_RXBURST_32LONG 0x03 487 #define TL_RXBURST_64LONG 0x04 488 #define TL_RXBURST_128LONG 0x05 489 490 #define TL_TXBURST_4LONG 0x00 491 #define TL_TXBURST_8LONG 0x10 492 #define TL_TXBURST_16LONG 0x20 493 #define TL_TXBURST_32LONG 0x30 494 #define TL_TXBURST_64LONG 0x40 495 #define TL_TXBURST_128LONG 0x50 496 497 /* 498 * register space access macros 499 */ 500 #define CSR_WRITE_4(sc, reg, val) \ 501 bus_space_write_4(sc->tl_btag, sc->tl_bhandle, reg, val) 502 #define CSR_WRITE_2(sc, reg, val) \ 503 bus_space_write_2(sc->tl_btag, sc->tl_bhandle, reg, val) 504 #define CSR_WRITE_1(sc, reg, val) \ 505 bus_space_write_1(sc->tl_btag, sc->tl_bhandle, reg, val) 506 507 #define CSR_READ_4(sc, reg) \ 508 bus_space_read_4(sc->tl_btag, sc->tl_bhandle, reg) 509 #define CSR_READ_2(sc, reg) \ 510 bus_space_read_2(sc->tl_btag, sc->tl_bhandle, reg) 511 #define CSR_READ_1(sc, reg) \ 512 bus_space_read_1(sc->tl_btag, sc->tl_bhandle, reg) 513 514 #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) 515 #define CMD_SET(sc, x) \ 516 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) 517 #define CMD_CLR(sc, x) \ 518 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) 519 520 /* 521 * ThunderLAN adapters typically have a serial EEPROM containing 522 * configuration information. The main reason we're interested in 523 * it is because it also contains the adapters's station address. 524 * 525 * Access to the EEPROM is a bit goofy since it is a serial device: 526 * you have to do reads and writes one bit at a time. The state of 527 * the DATA bit can only change while the CLOCK line is held low. 528 * Transactions work basically like this: 529 * 530 * 1) Send the EEPROM_START sequence to prepare the EEPROM for 531 * accepting commands. This pulls the clock high, sets 532 * the data bit to 0, enables transmission to the EEPROM, 533 * pulls the data bit up to 1, then pulls the clock low. 534 * The idea is to do a 0 to 1 transition of the data bit 535 * while the clock pin is held high. 536 * 537 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 538 * set the EDATA bit to send a 1 or clear it to send a 0. 539 * Finally, set and then clear ECLOK. Strobing the clock 540 * transmits the bit. After 8 bits have been written, the 541 * EEPROM should respond with an ACK, which should be read. 542 * 543 * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 544 * then set ECLOK. The bit can then be read by reading EDATA. 545 * ECLOCK should then be cleared again. This can be repeated 546 * 8 times to read a whole byte, after which the 547 * 548 * 4) We need to send the address byte to the EEPROM. For this 549 * we have to send the write control byte to the EEPROM to 550 * tell it to accept data. The byte is 0xA0. The EEPROM should 551 * ack this. The address byte can be send after that. 552 * 553 * 5) Now we have to tell the EEPROM to send us data. For that we 554 * have to transmit the read control byte, which is 0xA1. This 555 * byte should also be acked. We can then read the data bits 556 * from the EEPROM. 557 * 558 * 6) When we're all finished, send the EEPROM_STOP sequence. 559 * 560 * Note that we use the ThunderLAN's NetSio register to access the 561 * EEPROM, however there is an alternate method. There is a PCI NVRAM 562 * register at PCI offset 0xB4 which can also be used with minor changes. 563 * The difference is that access to PCI registers via pci_conf_read() 564 * and pci_conf_write() is done using programmed I/O, which we want to 565 * avoid. 566 */ 567 568 /* 569 * Note that EEPROM_START leaves transmission enabled. 570 */ 571 #define EEPROM_START \ 572 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\ 573 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 574 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\ 575 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\ 576 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 577 578 /* 579 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 580 * that no further data can be written to the EEPROM I/O pin. 581 */ 582 #define EEPROM_STOP \ 583 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \ 584 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \ 585 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \ 586 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \ 587 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 588 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \ 589 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 590 591 /* 592 * Microchip Technology 24Cxx EEPROM control bytes 593 */ 594 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 595 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 596 597 #ifdef __alpha__ 598 #undef vtophys 599 #define vtophys(va) alpha_XXX_dmamap((vaddr_t)va) 600 #endif 601