1 /** @file 2 CPUID leaf definitions. 3 4 Provides defines for CPUID leaf indexes. Data structures are provided for 5 registers returned by a CPUID leaf that contain one or more bit fields. 6 If a register returned is a single 32-bit value, then a data structure is 7 not provided for that register. 8 9 Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR> 10 11 SPDX-License-Identifier: BSD-2-Clause-Patent 12 13 @par Specification Reference: 14 AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34 15 16 **/ 17 18 #ifndef __AMD_CPUID_H__ 19 #define __AMD_CPUID_H__ 20 21 /** 22 CPUID Signature Information 23 24 @param EAX CPUID_SIGNATURE (0x00) 25 26 @retval EAX Returns the highest value the CPUID instruction recognizes for 27 returning basic processor information. The value is returned is 28 processor specific. 29 @retval EBX First 4 characters of a vendor identification string. 30 @retval ECX Last 4 characters of a vendor identification string. 31 @retval EDX Middle 4 characters of a vendor identification string. 32 33 **/ 34 35 /// 36 /// @{ CPUID signature values returned by AMD processors 37 /// 38 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h') 39 #define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i') 40 #define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D') 41 /// 42 /// @} 43 /// 44 45 /** 46 CPUID Extended Processor Signature and Features 47 48 @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001) 49 50 @retval EAX Extended Family, Model, Stepping Identifiers 51 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX. 52 @retval EBX Brand Identifier 53 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX. 54 @retval ECX Extended Feature Identifiers 55 described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX. 56 @retval EDX Extended Feature Identifiers 57 described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. 58 **/ 59 60 /** 61 CPUID Extended Processor Signature and Features EAX for CPUID leaf 62 #CPUID_EXTENDED_CPU_SIG. 63 **/ 64 typedef union { 65 /// 66 /// Individual bit fields 67 /// 68 struct { 69 /// 70 /// [Bits 3:0] Stepping. 71 /// 72 UINT32 Stepping : 4; 73 /// 74 /// [Bits 7:4] Base Model. 75 /// 76 UINT32 BaseModel : 4; 77 /// 78 /// [Bits 11:8] Base Family. 79 /// 80 UINT32 BaseFamily : 4; 81 /// 82 /// [Bit 15:12] Reserved. 83 /// 84 UINT32 Reserved1 : 4; 85 /// 86 /// [Bits 19:16] Extended Model. 87 /// 88 UINT32 ExtModel : 4; 89 /// 90 /// [Bits 27:20] Extended Family. 91 /// 92 UINT32 ExtFamily : 8; 93 /// 94 /// [Bit 31:28] Reserved. 95 /// 96 UINT32 Reserved2 : 4; 97 } Bits; 98 /// 99 /// All bit fields as a 32-bit value 100 /// 101 UINT32 Uint32; 102 } CPUID_AMD_EXTENDED_CPU_SIG_EAX; 103 104 /** 105 CPUID Extended Processor Signature and Features EBX for CPUID leaf 106 #CPUID_EXTENDED_CPU_SIG. 107 **/ 108 typedef union { 109 /// 110 /// Individual bit fields 111 /// 112 struct { 113 /// 114 /// [Bits 27:0] Reserved. 115 /// 116 UINT32 Reserved : 28; 117 /// 118 /// [Bit 31:28] Package Type. 119 /// 120 UINT32 PkgType : 4; 121 } Bits; 122 /// 123 /// All bit fields as a 32-bit value 124 /// 125 UINT32 Uint32; 126 } CPUID_AMD_EXTENDED_CPU_SIG_EBX; 127 128 /** 129 CPUID Extended Processor Signature and Features ECX for CPUID leaf 130 #CPUID_EXTENDED_CPU_SIG. 131 **/ 132 typedef union { 133 /// 134 /// Individual bit fields 135 /// 136 struct { 137 /// 138 /// [Bit 0] LAHF/SAHF available in 64-bit mode. 139 /// 140 UINT32 LAHF_SAHF : 1; 141 /// 142 /// [Bit 1] Core multi-processing legacy mode. 143 /// 144 UINT32 CmpLegacy : 1; 145 /// 146 /// [Bit 2] Secure Virtual Mode feature. 147 /// 148 UINT32 SVM : 1; 149 /// 150 /// [Bit 3] Extended APIC register space. 151 /// 152 UINT32 ExtApicSpace : 1; 153 /// 154 /// [Bit 4] LOCK MOV CR0 means MOV CR8. 155 /// 156 UINT32 AltMovCr8 : 1; 157 /// 158 /// [Bit 5] LZCNT instruction support. 159 /// 160 UINT32 LZCNT : 1; 161 /// 162 /// [Bit 6] SSE4A instruction support. 163 /// 164 UINT32 SSE4A : 1; 165 /// 166 /// [Bit 7] Misaligned SSE Mode. 167 /// 168 UINT32 MisAlignSse : 1; 169 /// 170 /// [Bit 8] ThreeDNow Prefetch instructions. 171 /// 172 UINT32 PREFETCHW : 1; 173 /// 174 /// [Bit 9] OS Visible Work-around support. 175 /// 176 UINT32 OSVW : 1; 177 /// 178 /// [Bit 10] Instruction Based Sampling. 179 /// 180 UINT32 IBS : 1; 181 /// 182 /// [Bit 11] Extended Operation Support. 183 /// 184 UINT32 XOP : 1; 185 /// 186 /// [Bit 12] SKINIT and STGI support. 187 /// 188 UINT32 SKINIT : 1; 189 /// 190 /// [Bit 13] Watchdog Timer support. 191 /// 192 UINT32 WDT : 1; 193 /// 194 /// [Bit 14] Reserved. 195 /// 196 UINT32 Reserved1 : 1; 197 /// 198 /// [Bit 15] Lightweight Profiling support. 199 /// 200 UINT32 LWP : 1; 201 /// 202 /// [Bit 16] 4-Operand FMA instruction support. 203 /// 204 UINT32 FMA4 : 1; 205 /// 206 /// [Bit 17] Translation Cache Extension. 207 /// 208 UINT32 TCE : 1; 209 /// 210 /// [Bit 21:18] Reserved. 211 /// 212 UINT32 Reserved2 : 4; 213 /// 214 /// [Bit 22] Topology Extensions support. 215 /// 216 UINT32 TopologyExtensions : 1; 217 /// 218 /// [Bit 23] Core Performance Counter Extensions. 219 /// 220 UINT32 PerfCtrExtCore : 1; 221 /// 222 /// [Bit 25:24] Reserved. 223 /// 224 UINT32 Reserved3 : 2; 225 /// 226 /// [Bit 26] Data Breakpoint Extension. 227 /// 228 UINT32 DataBreakpointExtension : 1; 229 /// 230 /// [Bit 27] Performance Time-Stamp Counter. 231 /// 232 UINT32 PerfTsc : 1; 233 /// 234 /// [Bit 28] L3 Performance Counter Extensions. 235 /// 236 UINT32 PerfCtrExtL3 : 1; 237 /// 238 /// [Bit 29] MWAITX and MONITORX capability. 239 /// 240 UINT32 MwaitExtended : 1; 241 /// 242 /// [Bit 31:30] Reserved. 243 /// 244 UINT32 Reserved4 : 2; 245 } Bits; 246 /// 247 /// All bit fields as a 32-bit value 248 /// 249 UINT32 Uint32; 250 } CPUID_AMD_EXTENDED_CPU_SIG_ECX; 251 252 /** 253 CPUID Extended Processor Signature and Features EDX for CPUID leaf 254 #CPUID_EXTENDED_CPU_SIG. 255 **/ 256 typedef union { 257 /// 258 /// Individual bit fields 259 /// 260 struct { 261 /// 262 /// [Bit 0] x87 floating point unit on-chip. 263 /// 264 UINT32 FPU : 1; 265 /// 266 /// [Bit 1] Virtual-mode enhancements. 267 /// 268 UINT32 VME : 1; 269 /// 270 /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE. 271 /// 272 UINT32 DE : 1; 273 /// 274 /// [Bit 3] Page-size extensions (4 MB pages). 275 /// 276 UINT32 PSE : 1; 277 /// 278 /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD. 279 /// 280 UINT32 TSC : 1; 281 /// 282 /// [Bit 5] MSRs, with RDMSR and WRMSR instructions. 283 /// 284 UINT32 MSR : 1; 285 /// 286 /// [Bit 6] Physical-address extensions (PAE). 287 /// 288 UINT32 PAE : 1; 289 /// 290 /// [Bit 7] Machine check exception, CR4.MCE. 291 /// 292 UINT32 MCE : 1; 293 /// 294 /// [Bit 8] CMPXCHG8B instruction. 295 /// 296 UINT32 CMPXCHG8B : 1; 297 /// 298 /// [Bit 9] APIC exists and is enabled. 299 /// 300 UINT32 APIC : 1; 301 /// 302 /// [Bit 10] Reserved. 303 /// 304 UINT32 Reserved1 : 1; 305 /// 306 /// [Bit 11] SYSCALL and SYSRET instructions. 307 /// 308 UINT32 SYSCALL_SYSRET : 1; 309 /// 310 /// [Bit 12] Memory-type range registers. 311 /// 312 UINT32 MTRR : 1; 313 /// 314 /// [Bit 13] Page global extension, CR4.PGE. 315 /// 316 UINT32 PGE : 1; 317 /// 318 /// [Bit 14] Machine check architecture, MCG_CAP. 319 /// 320 UINT32 MCA : 1; 321 /// 322 /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV. 323 /// 324 UINT32 CMOV : 1; 325 /// 326 /// [Bit 16] Page attribute table. 327 /// 328 UINT32 PAT : 1; 329 /// 330 /// [Bit 17] Page-size extensions. 331 /// 332 UINT32 PSE36 : 1; 333 /// 334 /// [Bit 19:18] Reserved. 335 /// 336 UINT32 Reserved2 : 2; 337 /// 338 /// [Bit 20] No-execute page protection. 339 /// 340 UINT32 NX : 1; 341 /// 342 /// [Bit 21] Reserved. 343 /// 344 UINT32 Reserved3 : 1; 345 /// 346 /// [Bit 22] AMD Extensions to MMX instructions. 347 /// 348 UINT32 MmxExt : 1; 349 /// 350 /// [Bit 23] MMX instructions. 351 /// 352 UINT32 MMX : 1; 353 /// 354 /// [Bit 24] FXSAVE and FXRSTOR instructions. 355 /// 356 UINT32 FFSR : 1; 357 /// 358 /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations. 359 /// 360 UINT32 FFXSR : 1; 361 /// 362 /// [Bit 26] 1-GByte large page support. 363 /// 364 UINT32 Page1GB : 1; 365 /// 366 /// [Bit 27] RDTSCP instructions. 367 /// 368 UINT32 RDTSCP : 1; 369 /// 370 /// [Bit 28] Reserved. 371 /// 372 UINT32 Reserved4 : 1; 373 /// 374 /// [Bit 29] Long Mode. 375 /// 376 UINT32 LM : 1; 377 /// 378 /// [Bit 30] 3DNow! instructions. 379 /// 380 UINT32 ThreeDNow : 1; 381 /// 382 /// [Bit 31] AMD Extensions to 3DNow! instructions. 383 /// 384 UINT32 ThreeDNowExt : 1; 385 } Bits; 386 /// 387 /// All bit fields as a 32-bit value 388 /// 389 UINT32 Uint32; 390 } CPUID_AMD_EXTENDED_CPU_SIG_EDX; 391 392 /** 393 CPUID Linear Physical Address Size 394 395 @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) 396 397 @retval EAX Linear/Physical Address Size described by the type 398 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX. 399 @retval EBX Linear/Physical Address Size described by the type 400 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX. 401 @retval ECX Linear/Physical Address Size described by the type 402 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX. 403 @retval EDX Reserved. 404 **/ 405 406 /** 407 CPUID Linear Physical Address Size EAX for CPUID leaf 408 #CPUID_VIR_PHY_ADDRESS_SIZE. 409 **/ 410 typedef union { 411 /// 412 /// Individual bit fields 413 /// 414 struct { 415 /// 416 /// [Bits 7:0] Maximum physical byte address size in bits. 417 /// 418 UINT32 PhysicalAddressBits : 8; 419 /// 420 /// [Bits 15:8] Maximum linear byte address size in bits. 421 /// 422 UINT32 LinearAddressBits : 8; 423 /// 424 /// [Bits 23:16] Maximum guest physical byte address size in bits. 425 /// 426 UINT32 GuestPhysAddrSize : 8; 427 /// 428 /// [Bit 31:24] Reserved. 429 /// 430 UINT32 Reserved : 8; 431 } Bits; 432 /// 433 /// All bit fields as a 32-bit value 434 /// 435 UINT32 Uint32; 436 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX; 437 438 /** 439 CPUID Linear Physical Address Size EBX for CPUID leaf 440 #CPUID_VIR_PHY_ADDRESS_SIZE. 441 **/ 442 typedef union { 443 /// 444 /// Individual bit fields 445 /// 446 struct { 447 /// 448 /// [Bits 0] Clear Zero Instruction. 449 /// 450 UINT32 CLZERO : 1; 451 /// 452 /// [Bits 1] Instructions retired count support. 453 /// 454 UINT32 IRPerf : 1; 455 /// 456 /// [Bits 2] Restore error pointers for XSave instructions. 457 /// 458 UINT32 XSaveErPtr : 1; 459 /// 460 /// [Bit 31:3] Reserved. 461 /// 462 UINT32 Reserved : 29; 463 } Bits; 464 /// 465 /// All bit fields as a 32-bit value 466 /// 467 UINT32 Uint32; 468 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX; 469 470 /** 471 CPUID Linear Physical Address Size ECX for CPUID leaf 472 #CPUID_VIR_PHY_ADDRESS_SIZE. 473 **/ 474 typedef union { 475 /// 476 /// Individual bit fields 477 /// 478 struct { 479 /// 480 /// [Bits 7:0] Number of threads - 1. 481 /// 482 UINT32 NC : 8; 483 /// 484 /// [Bit 11:8] Reserved. 485 /// 486 UINT32 Reserved1 : 4; 487 /// 488 /// [Bits 15:12] APIC ID size. 489 /// 490 UINT32 ApicIdCoreIdSize : 4; 491 /// 492 /// [Bits 17:16] Performance time-stamp counter size. 493 /// 494 UINT32 PerfTscSize : 2; 495 /// 496 /// [Bit 31:18] Reserved. 497 /// 498 UINT32 Reserved2 : 14; 499 } Bits; 500 /// 501 /// All bit fields as a 32-bit value 502 /// 503 UINT32 Uint32; 504 } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX; 505 506 /** 507 CPUID AMD Processor Topology 508 509 @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E) 510 511 @retval EAX Extended APIC ID described by the type 512 CPUID_AMD_PROCESSOR_TOPOLOGY_EAX. 513 @retval EBX Core Identifiers described by the type 514 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX. 515 @retval ECX Node Identifiers described by the type 516 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX. 517 @retval EDX Reserved. 518 **/ 519 #define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E 520 521 /** 522 CPUID AMD Processor Topology EAX for CPUID leaf 523 #CPUID_AMD_PROCESSOR_TOPOLOGY. 524 **/ 525 typedef union { 526 /// 527 /// Individual bit fields 528 /// 529 struct { 530 /// 531 /// [Bit 31:0] Extended APIC Id. 532 /// 533 UINT32 ExtendedApicId; 534 } Bits; 535 /// 536 /// All bit fields as a 32-bit value 537 /// 538 UINT32 Uint32; 539 } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX; 540 541 /** 542 CPUID AMD Processor Topology EBX for CPUID leaf 543 #CPUID_AMD_PROCESSOR_TOPOLOGY. 544 **/ 545 typedef union { 546 /// 547 /// Individual bit fields 548 /// 549 struct { 550 /// 551 /// [Bits 7:0] Core Id. 552 /// 553 UINT32 CoreId : 8; 554 /// 555 /// [Bits 15:8] Threads per core. 556 /// 557 UINT32 ThreadsPerCore : 8; 558 /// 559 /// [Bit 31:16] Reserved. 560 /// 561 UINT32 Reserved : 16; 562 } Bits; 563 /// 564 /// All bit fields as a 32-bit value 565 /// 566 UINT32 Uint32; 567 } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX; 568 569 /** 570 CPUID AMD Processor Topology ECX for CPUID leaf 571 #CPUID_AMD_PROCESSOR_TOPOLOGY. 572 **/ 573 typedef union { 574 /// 575 /// Individual bit fields 576 /// 577 struct { 578 /// 579 /// [Bits 7:0] Node Id. 580 /// 581 UINT32 NodeId : 8; 582 /// 583 /// [Bits 10:8] Nodes per processor. 584 /// 585 UINT32 NodesPerProcessor : 3; 586 /// 587 /// [Bit 31:11] Reserved. 588 /// 589 UINT32 Reserved : 21; 590 } Bits; 591 /// 592 /// All bit fields as a 32-bit value 593 /// 594 UINT32 Uint32; 595 } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX; 596 597 /** 598 CPUID Memory Encryption Information 599 600 @param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F) 601 602 @retval EAX Returns the memory encryption feature support status. 603 @retval EBX If memory encryption feature is present then return 604 the page table bit number used to enable memory encryption support 605 and reducing of physical address space in bits. 606 @retval ECX Returns number of encrypted guest supported simultaneously. 607 @retval EDX Returns minimum SEV enabled and SEV disabled ASID. 608 609 <b>Example usage</b> 610 @code 611 UINT32 Eax; 612 UINT32 Ebx; 613 UINT32 Ecx; 614 UINT32 Edx; 615 616 AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx); 617 @endcode 618 **/ 619 620 #define CPUID_MEMORY_ENCRYPTION_INFO 0x8000001F 621 622 /** 623 CPUID Memory Encryption support information EAX for CPUID leaf 624 #CPUID_MEMORY_ENCRYPTION_INFO. 625 **/ 626 typedef union { 627 /// 628 /// Individual bit fields 629 /// 630 struct { 631 /// 632 /// [Bit 0] Secure Memory Encryption (Sme) Support 633 /// 634 UINT32 SmeBit : 1; 635 636 /// 637 /// [Bit 1] Secure Encrypted Virtualization (Sev) Support 638 /// 639 UINT32 SevBit : 1; 640 641 /// 642 /// [Bit 2] Page flush MSR support 643 /// 644 UINT32 PageFlushMsrBit : 1; 645 646 /// 647 /// [Bit 3] Encrypted state support 648 /// 649 UINT32 SevEsBit : 1; 650 651 /// 652 /// [Bit 31:4] Reserved 653 /// 654 UINT32 ReservedBits : 28; 655 } Bits; 656 /// 657 /// All bit fields as a 32-bit value 658 /// 659 UINT32 Uint32; 660 } CPUID_MEMORY_ENCRYPTION_INFO_EAX; 661 662 /** 663 CPUID Memory Encryption support information EBX for CPUID leaf 664 #CPUID_MEMORY_ENCRYPTION_INFO. 665 **/ 666 typedef union { 667 /// 668 /// Individual bit fields 669 /// 670 struct { 671 /// 672 /// [Bit 5:0] Page table bit number used to enable memory encryption 673 /// 674 UINT32 PtePosBits : 6; 675 676 /// 677 /// [Bit 11:6] Reduction of system physical address space bits when 678 /// memory encryption is enabled 679 /// 680 UINT32 ReducedPhysBits : 5; 681 682 /// 683 /// [Bit 31:12] Reserved 684 /// 685 UINT32 ReservedBits : 21; 686 } Bits; 687 /// 688 /// All bit fields as a 32-bit value 689 /// 690 UINT32 Uint32; 691 } CPUID_MEMORY_ENCRYPTION_INFO_EBX; 692 693 /** 694 CPUID Memory Encryption support information ECX for CPUID leaf 695 #CPUID_MEMORY_ENCRYPTION_INFO. 696 **/ 697 typedef union { 698 /// 699 /// Individual bit fields 700 /// 701 struct { 702 /// 703 /// [Bit 31:0] Number of encrypted guest supported simultaneously 704 /// 705 UINT32 NumGuests; 706 } Bits; 707 /// 708 /// All bit fields as a 32-bit value 709 /// 710 UINT32 Uint32; 711 } CPUID_MEMORY_ENCRYPTION_INFO_ECX; 712 713 /** 714 CPUID Memory Encryption support information EDX for CPUID leaf 715 #CPUID_MEMORY_ENCRYPTION_INFO. 716 **/ 717 typedef union { 718 /// 719 /// Individual bit fields 720 /// 721 struct { 722 /// 723 /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID 724 /// 725 UINT32 MinAsid; 726 } Bits; 727 /// 728 /// All bit fields as a 32-bit value 729 /// 730 UINT32 Uint32; 731 } CPUID_MEMORY_ENCRYPTION_INFO_EDX; 732 733 #endif 734