1 /** 2 * \ingroup <FILEGROUP> 3 * 4 * \file msp430x16x.h 5 * 6 * \brief <FILEBRIEF> 7 * 8 */ 9 /* 10 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 11 * 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 20 * Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the 23 * distribution. 24 * 25 * Neither the name of Texas Instruments Incorporated nor the names of 26 * its contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 #ifndef __msp430x16x 43 #define __msp430x16x 44 45 #ifdef __IAR_SYSTEMS_ICC__ 46 #ifndef _SYSTEM_BUILD 47 #pragma system_include 48 #endif 49 #endif 50 51 #if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */ 52 #error MSP430X44X.H file for use with ICC430/A430 only 53 #endif 54 55 56 #ifdef __IAR_SYSTEMS_ICC__ 57 #include <in430.h> 58 #pragma language=extended 59 60 #define DEFC(name, address) __no_init volatile unsigned char name @ address; 61 #define DEFW(name, address) __no_init volatile unsigned short name @ address; 62 63 #endif /* __IAR_SYSTEMS_ICC__ */ 64 65 66 #ifdef __IAR_SYSTEMS_ASM__ 67 #define DEFC(name, address) sfrb name = address; 68 #define DEFW(name, address) sfrw name = address; 69 70 #endif /* __IAR_SYSTEMS_ASM__*/ 71 72 #ifdef __cplusplus 73 #define READ_ONLY 74 #else 75 #define READ_ONLY const 76 #endif 77 78 /************************************************************ 79 * STANDARD BITS 80 ************************************************************/ 81 82 #define BIT0 (0x0001) 83 #define BIT1 (0x0002) 84 #define BIT2 (0x0004) 85 #define BIT3 (0x0008) 86 #define BIT4 (0x0010) 87 #define BIT5 (0x0020) 88 #define BIT6 (0x0040) 89 #define BIT7 (0x0080) 90 #define BIT8 (0x0100) 91 #define BIT9 (0x0200) 92 #define BITA (0x0400) 93 #define BITB (0x0800) 94 #define BITC (0x1000) 95 #define BITD (0x2000) 96 #define BITE (0x4000) 97 #define BITF (0x8000) 98 99 /************************************************************ 100 * STATUS REGISTER BITS 101 ************************************************************/ 102 103 #define C (0x0001) 104 #define Z (0x0002) 105 #define N (0x0004) 106 #define V (0x0100) 107 #define GIE (0x0008) 108 #define CPUOFF (0x0010) 109 #define OSCOFF (0x0020) 110 #define SCG0 (0x0040) 111 #define SCG1 (0x0080) 112 113 /* Low Power Modes coded with Bits 4-7 in SR */ 114 115 #ifndef __IAR_SYSTEMS_ICC /* Begin #defines for assembler */ 116 #define LPM0 (CPUOFF) 117 #define LPM1 (SCG0+CPUOFF) 118 #define LPM2 (SCG1+CPUOFF) 119 #define LPM3 (SCG1+SCG0+CPUOFF) 120 #define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF) 121 /* End #defines for assembler */ 122 123 #else /* Begin #defines for C */ 124 #define LPM0_bits (CPUOFF) 125 #define LPM1_bits (SCG0+CPUOFF) 126 #define LPM2_bits (SCG1+CPUOFF) 127 #define LPM3_bits (SCG1+SCG0+CPUOFF) 128 #define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF) 129 130 #include <In430.h> 131 132 #define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */ 133 #define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */ 134 #define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */ 135 #define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */ 136 #define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */ 137 #define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */ 138 #define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */ 139 #define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */ 140 #define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */ 141 #define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */ 142 #endif /* End #defines for C */ 143 144 /************************************************************ 145 * PERIPHERAL FILE MAP 146 ************************************************************/ 147 148 /************************************************************ 149 * SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS 150 ************************************************************/ 151 152 #define IE1_ (0x0000) /* Interrupt Enable 1 */ 153 DEFC( IE1 , IE1_) 154 #define U0IE IE1 /* UART0 Interrupt Enable Register */ 155 #define WDTIE (0x01) 156 #define OFIE (0x02) 157 #define NMIIE (0x10) 158 #define ACCVIE (0x20) 159 #define URXIE0 (0x40) 160 #define UTXIE0 (0x80) 161 162 #define IFG1_ (0x0002) /* Interrupt Flag 1 */ 163 DEFC( IFG1 , IFG1_) 164 #define U0IFG IFG1 /* UART0 Interrupt Flag Register */ 165 #define WDTIFG (0x01) 166 #define OFIFG (0x02) 167 #define NMIIFG (0x10) 168 #define URXIFG0 (0x40) 169 #define UTXIFG0 (0x80) 170 171 #define ME1_ (0x0004) /* Module Enable 1 */ 172 DEFC( ME1 , ME1_) 173 #define U0ME ME1 /* UART0 Module Enable Register */ 174 #define URXE0 (0x40) 175 #define UTXE0 (0x80) 176 #define USPIE0 (0x40) 177 178 #define IE2_ (0x0001) /* Interrupt Enable 2 */ 179 DEFC( IE2 , IE2_) 180 #define U1IE IE2 /* UART1 Interrupt Enable Register */ 181 #define URXIE1 (0x10) 182 #define UTXIE1 (0x20) 183 184 #define IFG2_ (0x0003) /* Interrupt Flag 2 */ 185 DEFC( IFG2 , IFG2_) 186 #define U1IFG IFG2 /* UART1 Interrupt Flag Register */ 187 #define URXIFG1 (0x10) 188 #define UTXIFG1 (0x20) 189 190 #define ME2_ (0x0005) /* Module Enable 2 */ 191 DEFC( ME2 , ME2_) 192 #define U1ME ME2 /* UART1 Module Enable Register */ 193 #define URXE1 (0x10) 194 #define UTXE1 (0x20) 195 #define USPIE1 (0x10) 196 197 /************************************************************ 198 * WATCHDOG TIMER 199 ************************************************************/ 200 #define __MSP430_HAS_WDT__ /* Definition to show that Module is available */ 201 202 #define WDTCTL_ (0x0120) /* Watchdog Timer Control */ 203 DEFW( WDTCTL , WDTCTL_) 204 /* The bit names have been prefixed with "WDT" */ 205 #define WDTIS0 (0x0001) 206 #define WDTIS1 (0x0002) 207 #define WDTSSEL (0x0004) 208 #define WDTCNTCL (0x0008) 209 #define WDTTMSEL (0x0010) 210 #define WDTNMI (0x0020) 211 #define WDTNMIES (0x0040) 212 #define WDTHOLD (0x0080) 213 214 #define WDTPW (0x5A00) 215 216 /* WDT-interval times [1ms] coded with Bits 0-2 */ 217 /* WDT is clocked by fSMCLK (assumed 1MHz) */ 218 #define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */ 219 #define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */ 220 #define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */ 221 #define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ 222 /* WDT is clocked by fACLK (assumed 32KHz) */ 223 #define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */ 224 #define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ 225 #define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ 226 #define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ 227 /* Watchdog mode -> reset after expired time */ 228 /* WDT is clocked by fSMCLK (assumed 1MHz) */ 229 #define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */ 230 #define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */ 231 #define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */ 232 #define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */ 233 /* WDT is clocked by fACLK (assumed 32KHz) */ 234 #define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */ 235 #define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */ 236 #define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */ 237 #define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */ 238 239 /* INTERRUPT CONTROL */ 240 /* These two bits are defined in the Special Function Registers */ 241 /* #define WDTIE 0x01 */ 242 /* #define WDTIFG 0x01 */ 243 244 /************************************************************ 245 * HARDWARE MULTIPLIER 246 ************************************************************/ 247 #define __MSP430_HAS_MPY__ /* Definition to show that Module is available */ 248 249 #define MPY_ (0x0130) /* Multiply Unsigned/Operand 1 */ 250 DEFW( MPY , MPY_) 251 #define MPYS_ (0x0132) /* Multiply Signed/Operand 1 */ 252 DEFW( MPYS , MPYS_) 253 #define MAC_ (0x0134) /* Multiply Unsigned and Accumulate/Operand 1 */ 254 DEFW( MAC , MAC_) 255 #define MACS_ (0x0136) /* Multiply Signed and Accumulate/Operand 1 */ 256 DEFW( MACS , MACS_) 257 #define OP2_ (0x0138) /* Operand 2 */ 258 DEFW( OP2 , OP2_) 259 #define RESLO_ (0x013A) /* Result Low Word */ 260 DEFW( RESLO , RESLO_) 261 #define RESHI_ (0x013C) /* Result High Word */ 262 DEFW( RESHI , RESHI_) 263 #define SUMEXT_ (0x013E) /* Sum Extend */ 264 READ_ONLY DEFW( SUMEXT , SUMEXT_) 265 266 /************************************************************ 267 * DIGITAL I/O Port1/2 268 ************************************************************/ 269 #define __MSP430_HAS_PORT1__ /* Definition to show that Module is available */ 270 #define __MSP430_HAS_PORT2__ /* Definition to show that Module is available */ 271 272 #define P1IN_ (0x0020) /* Port 1 Input */ 273 READ_ONLY DEFC( P1IN , P1IN_) 274 #define P1OUT_ (0x0021) /* Port 1 Output */ 275 DEFC( P1OUT , P1OUT_) 276 #define P1DIR_ (0x0022) /* Port 1 Direction */ 277 DEFC( P1DIR , P1DIR_) 278 #define P1IFG_ (0x0023) /* Port 1 Interrupt Flag */ 279 DEFC( P1IFG , P1IFG_) 280 #define P1IES_ (0x0024) /* Port 1 Interrupt Edge Select */ 281 DEFC( P1IES , P1IES_) 282 #define P1IE_ (0x0025) /* Port 1 Interrupt Enable */ 283 DEFC( P1IE , P1IE_) 284 #define P1SEL_ (0x0026) /* Port 1 Selection */ 285 DEFC( P1SEL , P1SEL_) 286 287 #define P2IN_ (0x0028) /* Port 2 Input */ 288 READ_ONLY DEFC( P2IN , P2IN_) 289 #define P2OUT_ (0x0029) /* Port 2 Output */ 290 DEFC( P2OUT , P2OUT_) 291 #define P2DIR_ (0x002A) /* Port 2 Direction */ 292 DEFC( P2DIR , P2DIR_) 293 #define P2IFG_ (0x002B) /* Port 2 Interrupt Flag */ 294 DEFC( P2IFG , P2IFG_) 295 #define P2IES_ (0x002C) /* Port 2 Interrupt Edge Select */ 296 DEFC( P2IES , P2IES_) 297 #define P2IE_ (0x002D) /* Port 2 Interrupt Enable */ 298 DEFC( P2IE , P2IE_) 299 #define P2SEL_ (0x002E) /* Port 2 Selection */ 300 DEFC( P2SEL , P2SEL_) 301 302 /************************************************************ 303 * DIGITAL I/O Port3/4 304 ************************************************************/ 305 #define __MSP430_HAS_PORT3__ /* Definition to show that Module is available */ 306 #define __MSP430_HAS_PORT4__ /* Definition to show that Module is available */ 307 308 #define P3IN_ (0x0018) /* Port 3 Input */ 309 READ_ONLY DEFC( P3IN , P3IN_) 310 #define P3OUT_ (0x0019) /* Port 3 Output */ 311 DEFC( P3OUT , P3OUT_) 312 #define P3DIR_ (0x001A) /* Port 3 Direction */ 313 DEFC( P3DIR , P3DIR_) 314 #define P3SEL_ (0x001B) /* Port 3 Selection */ 315 DEFC( P3SEL , P3SEL_) 316 317 #define P4IN_ (0x001C) /* Port 4 Input */ 318 READ_ONLY DEFC( P4IN , P4IN_) 319 #define P4OUT_ (0x001D) /* Port 4 Output */ 320 DEFC( P4OUT , P4OUT_) 321 #define P4DIR_ (0x001E) /* Port 4 Direction */ 322 DEFC( P4DIR , P4DIR_) 323 #define P4SEL_ (0x001F) /* Port 4 Selection */ 324 DEFC( P4SEL , P4SEL_) 325 326 /************************************************************ 327 * DIGITAL I/O Port5/6 328 ************************************************************/ 329 #define __MSP430_HAS_PORT5__ /* Definition to show that Module is available */ 330 #define __MSP430_HAS_PORT6__ /* Definition to show that Module is available */ 331 332 #define P5IN_ (0x0030) /* Port 5 Input */ 333 READ_ONLY DEFC( P5IN , P5IN_) 334 #define P5OUT_ (0x0031) /* Port 5 Output */ 335 DEFC( P5OUT , P5OUT_) 336 #define P5DIR_ (0x0032) /* Port 5 Direction */ 337 DEFC( P5DIR , P5DIR_) 338 #define P5SEL_ (0x0033) /* Port 5 Selection */ 339 DEFC( P5SEL , P5SEL_) 340 341 #define P6IN_ (0x0034) /* Port 6 Input */ 342 READ_ONLY DEFC( P6IN , P6IN_) 343 #define P6OUT_ (0x0035) /* Port 6 Output */ 344 DEFC( P6OUT , P6OUT_) 345 #define P6DIR_ (0x0036) /* Port 6 Direction */ 346 DEFC( P6DIR , P6DIR_) 347 #define P6SEL_ (0x0037) /* Port 6 Selection */ 348 DEFC( P6SEL , P6SEL_) 349 350 /************************************************************ 351 * USART 352 ************************************************************/ 353 354 /* UxCTL */ 355 #define PENA (0x80) /* Parity enable */ 356 #define PEV (0x40) /* Parity 0:odd / 1:even */ 357 #define SPB (0x20) /* Stop Bits 0:one / 1: two */ 358 #define CHAR (0x10) /* Data 0:7-bits / 1:8-bits */ 359 #define LISTEN (0x08) /* Listen mode */ 360 #define SYNC (0x04) /* UART / SPI mode */ 361 #define MM (0x02) /* Master Mode off/on */ 362 #define SWRST (0x01) /* USART Software Reset */ 363 364 /* UxTCTL */ 365 #define CKPH (0x80) /* SPI: Clock Phase */ 366 #define CKPL (0x40) /* Clock Polarity */ 367 #define SSEL1 (0x20) /* Clock Source Select 1 */ 368 #define SSEL0 (0x10) /* Clock Source Select 0 */ 369 #define URXSE (0x08) /* Receive Start edge select */ 370 #define TXWAKE (0x04) /* TX Wake up mode */ 371 #define STC (0x02) /* SPI: STC enable 0:on / 1:off */ 372 #define TXEPT (0x01) /* TX Buffer empty */ 373 374 /* UxRCTL */ 375 #define FE (0x80) /* Frame Error */ 376 #define PE (0x40) /* Parity Error */ 377 #define OE (0x20) /* Overrun Error */ 378 #define BRK (0x10) /* Break detected */ 379 #define URXEIE (0x08) /* RX Error interrupt enable */ 380 #define URXWIE (0x04) /* RX Wake up interrupt enable */ 381 #define RXWAKE (0x02) /* RX Wake up detect */ 382 #define RXERR (0x01) /* RX Error Error */ 383 384 /************************************************************ 385 * USART 0 386 ************************************************************/ 387 #define __MSP430_HAS_UART0__ /* Definition to show that Module is available */ 388 389 #define U0CTL_ (0x0070) /* USART 0 Control */ 390 DEFC( U0CTL , U0CTL_) 391 #define U0TCTL_ (0x0071) /* USART 0 Transmit Control */ 392 DEFC( U0TCTL , U0TCTL_) 393 #define U0RCTL_ (0x0072) /* USART 0 Receive Control */ 394 DEFC( U0RCTL , U0RCTL_) 395 #define U0MCTL_ (0x0073) /* USART 0 Modulation Control */ 396 DEFC( U0MCTL , U0MCTL_) 397 #define U0BR0_ (0x0074) /* USART 0 Baud Rate 0 */ 398 DEFC( U0BR0 , U0BR0_) 399 #define U0BR1_ (0x0075) /* USART 0 Baud Rate 1 */ 400 DEFC( U0BR1 , U0BR1_) 401 #define U0RXBUF_ (0x0076) /* USART 0 Receive Buffer */ 402 #ifndef __IAR_SYSTEMS_ICC__ 403 READ_ONLY DEFC( U0RXBUF , U0RXBUF_) 404 #endif 405 #define U0TXBUF_ (0x0077) /* USART 0 Transmit Buffer */ 406 #ifndef __IAR_SYSTEMS_ICC__ 407 DEFC( U0TXBUF , U0TXBUF_) 408 #endif 409 410 /* Alternate register names */ 411 412 #define UCTL0 U0CTL /* USART 0 Control */ 413 #define UTCTL0 U0TCTL /* USART 0 Transmit Control */ 414 #define URCTL0 U0RCTL /* USART 0 Receive Control */ 415 #define UMCTL0 U0MCTL /* USART 0 Modulation Control */ 416 #define UBR00 U0BR0 /* USART 0 Baud Rate 0 */ 417 #define UBR10 U0BR1 /* USART 0 Baud Rate 1 */ 418 #define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */ 419 #define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */ 420 #define UCTL0_ U0CTL_ /* USART 0 Control */ 421 #define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */ 422 #define URCTL0_ U0RCTL_ /* USART 0 Receive Control */ 423 #define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */ 424 #define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */ 425 #define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */ 426 #define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */ 427 #define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */ 428 #define UCTL_0 U0CTL /* USART 0 Control */ 429 #define UTCTL_0 U0TCTL /* USART 0 Transmit Control */ 430 #define URCTL_0 U0RCTL /* USART 0 Receive Control */ 431 #define UMCTL_0 U0MCTL /* USART 0 Modulation Control */ 432 #define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */ 433 #define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */ 434 #define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */ 435 #define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */ 436 #define UCTL_0_ U0CTL_ /* USART 0 Control */ 437 #define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */ 438 #define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */ 439 #define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */ 440 #define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */ 441 #define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */ 442 #define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */ 443 #define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */ 444 445 /************************************************************ 446 * USART 1 447 ************************************************************/ 448 #define __MSP430_HAS_UART1__ /* Definition to show that Module is available */ 449 450 #define U1CTL_ (0x0078) /* USART 1 Control */ 451 DEFC( U1CTL , U1CTL_) 452 #define U1TCTL_ (0x0079) /* USART 1 Transmit Control */ 453 DEFC( U1TCTL , U1TCTL_) 454 #define U1RCTL_ (0x007A) /* USART 1 Receive Control */ 455 DEFC( U1RCTL , U1RCTL_) 456 #define U1MCTL_ (0x007B) /* USART 1 Modulation Control */ 457 DEFC( U1MCTL , U1MCTL_) 458 #define U1BR0_ (0x007C) /* USART 1 Baud Rate 0 */ 459 DEFC( U1BR0 , U1BR0_) 460 #define U1BR1_ (0x007D) /* USART 1 Baud Rate 1 */ 461 DEFC( U1BR1 , U1BR1_) 462 #define U1RXBUF_ (0x007E) /* USART 1 Receive Buffer */ 463 READ_ONLY DEFC( U1RXBUF , U1RXBUF_) 464 #define U1TXBUF_ (0x007F) /* USART 1 Transmit Buffer */ 465 DEFC( U1TXBUF , U1TXBUF_) 466 467 /* Alternate register names */ 468 469 #define UCTL1 U1CTL /* USART 1 Control */ 470 #define UTCTL1 U1TCTL /* USART 1 Transmit Control */ 471 #define URCTL1 U1RCTL /* USART 1 Receive Control */ 472 #define UMCTL1 U1MCTL /* USART 1 Modulation Control */ 473 #define UBR01 U1BR0 /* USART 1 Baud Rate 0 */ 474 #define UBR11 U1BR1 /* USART 1 Baud Rate 1 */ 475 #define RXBUF1 U1RXBUF /* USART 1 Receive Buffer */ 476 #define TXBUF1 U1TXBUF /* USART 1 Transmit Buffer */ 477 #define UCTL1_ U1CTL_ /* USART 1 Control */ 478 #define UTCTL1_ U1TCTL_ /* USART 1 Transmit Control */ 479 #define URCTL1_ U1RCTL_ /* USART 1 Receive Control */ 480 #define UMCTL1_ U1MCTL_ /* USART 1 Modulation Control */ 481 #define UBR01_ U1BR0_ /* USART 1 Baud Rate 0 */ 482 #define UBR11_ U1BR1_ /* USART 1 Baud Rate 1 */ 483 #define RXBUF1_ U1RXBUF_ /* USART 1 Receive Buffer */ 484 #define TXBUF1_ U1TXBUF_ /* USART 1 Transmit Buffer */ 485 #define UCTL_1 U1CTL /* USART 1 Control */ 486 #define UTCTL_1 U1TCTL /* USART 1 Transmit Control */ 487 #define URCTL_1 U1RCTL /* USART 1 Receive Control */ 488 #define UMCTL_1 U1MCTL /* USART 1 Modulation Control */ 489 #define UBR0_1 U1BR0 /* USART 1 Baud Rate 0 */ 490 #define UBR1_1 U1BR1 /* USART 1 Baud Rate 1 */ 491 #define RXBUF_1 U1RXBUF /* USART 1 Receive Buffer */ 492 #define TXBUF_1 U1TXBUF /* USART 1 Transmit Buffer */ 493 #define UCTL_1_ U1CTL_ /* USART 1 Control */ 494 #define UTCTL_1_ U1TCTL_ /* USART 1 Transmit Control */ 495 #define URCTL_1_ U1RCTL_ /* USART 1 Receive Control */ 496 #define UMCTL_1_ U1MCTL_ /* USART 1 Modulation Control */ 497 #define UBR0_1_ U1BR0_ /* USART 1 Baud Rate 0 */ 498 #define UBR1_1_ U1BR1_ /* USART 1 Baud Rate 1 */ 499 #define RXBUF_1_ U1RXBUF_ /* USART 1 Receive Buffer */ 500 #define TXBUF_1_ U1TXBUF_ /* USART 1 Transmit Buffer */ 501 502 /************************************************************ 503 * USART0 I2C 504 ************************************************************/ 505 #define __MSP430_HAS_I2C__ /* Definition to show that Module is available */ 506 507 #define I2CIE_ (0x0050) /* I2C Interrupt Enable */ 508 DEFC( I2CIE , I2CIE_) 509 #define ALIE (0x01) /* Arbitration lost */ 510 #define NACKIE (0x02) /* No acknowledge */ 511 #define OAIE (0x04) /* Own address */ 512 #define ARDYIE (0x08) /* Access ready (opeation complete) */ 513 #define RXRDYIE (0x10) /* Receive ready (data received) */ 514 #define TXRDYIE (0x20) /* Transmit ready (transmit register empty) */ 515 #define GCIE (0x40) /* General call */ 516 #define STTIE (0x80) /* Start condition */ 517 518 #define I2CIFG_ (0x0051) /* I2C Interrupt Flag */ 519 DEFC( I2CIFG , I2CIFG_) 520 #define ALIFG (0x01) /* Arbitration lost */ 521 #define NACKIFG (0x02) /* No acknowledge */ 522 #define OAIFG (0x04) /* Own address */ 523 #define ARDYIFG (0x08) /* Access ready (opeation complete) */ 524 #define RXRDYIFG (0x10) /* Receive ready (data received) */ 525 #define TXRDYIFG (0x20) /* Transmit ready (transmit register empty) */ 526 #define GCIFG (0x40) /* General call */ 527 #define STTIFG (0x80) /* Start condition */ 528 529 #define I2CNDAT_ (0x0052) /* I2C Data Count */ 530 DEFC( I2CNDAT , I2CNDAT_) 531 532 /* USART 0 Control */ 533 #define I2CEN (0x01) /* I2C enable */ 534 #define MST (0x02) /* I2C master */ 535 #define XA (0x10) /* I2C extended addressing */ 536 #define I2C (0x20) /* USART I2C */ 537 #define TXDMAEN (0x40) /* Transmit DMA enable */ 538 #define RXDMAEN (0x80) /* Receive DMA enable */ 539 540 #define I2CTCTL U0TCTL /* I2C Transfer Control */ 541 #define I2CTCTL_ U0TCTL /* I2C Transfer Control */ 542 #define I2CSTT (0x01) /* Start bit */ 543 #define I2CSTP (0x02) /* Stop bit */ 544 #define I2CSTB (0x04) /* Start byte mode */ 545 #define I2CTRX (0x08) /* Transmit */ 546 #define I2CSSEL0 (0x10) /* Clock select bit 0 */ 547 #define I2CSSEL1 (0x20) /* Clock select bit 1 */ 548 #define I2CRM (0x40) /* Repeat mode */ 549 #define I2CWORD (0x80) /* Word data mode */ 550 551 #define I2CSSEL_0 (0*0x10u) /* I2C clock select 0: UCLK */ 552 #define I2CSSEL_1 (1*0x10u) /* I2C clock select 1: ACLK */ 553 #define I2CSSEL_2 (2*0x10u) /* I2C clock select 2: SMCLK */ 554 #define I2CSSEL_3 (3*0x10u) /* I2C clock select 3: SMCLK */ 555 556 #define I2CMM_0 (0x00) /* Master mode 0 */ 557 #define I2CMM_1 (I2CSTT) /* Master mode 1 */ 558 #define I2CMM_2 (I2CSTP+I2CSTT) /* Master mode 2 */ 559 #define I2CMM_3 (I2CRM+I2CSTT) /* Master mode 3 */ 560 #define I2CMM_4 (I2CSTP) /* Master mode 4 */ 561 562 #define I2CDCTL U0RCTL /* I2C Data Control */ 563 #define I2CDCTL_ U0RCTL /* I2C Data Control */ 564 #define I2CBB (0x01) /* Bus busy */ 565 #define I2CRXOVR (0x02) /* Receiver overrun */ 566 #define I2CTXUDF (0x04) /* Transmit underflow */ 567 #define I2CSBD (0x08) /* Received byte */ 568 #define I2CSCLLOW (0x10) /* SCL being held low */ 569 #define I2CBUSY (0x20) /* I2C Busy Flag */ 570 571 #define I2CPSC U0MCTL /* I2C Pre-scaler */ 572 #define I2CPSC_ U0MCTL /* I2C Pre-scaler */ 573 #define I2CSCLH U0BR0 /* I2C SCL High */ 574 #define I2CSCLH_ U0BR0 /* I2C SCL High */ 575 #define I2CSCLL U0BR1 /* I2C SCL Low */ 576 #define I2CSCLL_ U0BR1 /* I2C SCL Low */ 577 #define I2CDRB_ (0x0076) /* I2C Data for Byte access */ 578 #ifndef __IAR_SYSTEMS_ICC__ 579 DEFC( I2CDRB , I2CDRB_) 580 #endif 581 #define I2CDRW_ (0x0076) /* I2C Data for Word access */ 582 #ifndef __IAR_SYSTEMS_ICC__ 583 DEFW( I2CDRW , I2CDRW_) 584 #endif 585 586 #ifdef __IAR_SYSTEMS_ICC__ 587 __no_init union 588 { 589 struct 590 { 591 volatile READ_ONLY unsigned char U0RXBUF; 592 volatile unsigned char U0TXBUF; 593 }; 594 volatile unsigned short I2CDRW; 595 volatile unsigned char I2CDRB; 596 } @ 0x0076; 597 #endif 598 599 #define I2COA_ (0x0118) /* I2C Own Address */ 600 DEFW( I2COA , I2COA_) 601 #define I2CSA_ (0x011A) /* I2C Slave Address */ 602 DEFW( I2CSA , I2CSA_) 603 604 #define I2CIV_ (0x011C) /* I2C Interrupt Vector */ 605 READ_ONLY DEFW( I2CIV , I2CIV_) 606 #define I2CIV_NONE (0x0000) /* I2C interrupt vector: No interrupt pending */ 607 #define I2CIV_AL (0x0002) /* I2C interrupt vector: Arbitration lost (ALIFG) */ 608 #define I2CIV_NACK (0x0004) /* I2C interrupt vector: No acknowledge (NACKIFG) */ 609 #define I2CIV_OA (0x0006) /* I2C interrupt vector: Own address (OAIFG) */ 610 #define I2CIV_ARDY (0x0008) /* I2C interrupt vector: Access ready (ARDYIFG) */ 611 #define I2CIV_RXRDY (0x000A) /* I2C interrupt vector: Receive ready (RXRDYIFG) */ 612 #define I2CIV_TXRDY (0x000C) /* I2C interrupt vector: Transmit ready (TXRDYIFG) */ 613 #define I2CIV_GC (0x000E) /* I2C interrupt vector: General call (GCIFG) */ 614 #define I2CIV_STT (0x0010) /* I2C interrupt vector: Start condition (STTIFG) */ 615 616 /************************************************************ 617 * Timer A3 618 ************************************************************/ 619 #define __MSP430_HAS_TA3__ /* Definition to show that Module is available */ 620 621 #define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */ 622 READ_ONLY DEFW( TAIV , TAIV_) 623 #define TACTL_ (0x0160) /* Timer A Control */ 624 DEFW( TACTL , TACTL_) 625 #define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */ 626 DEFW( TACCTL0 , TACCTL0_) 627 #define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */ 628 DEFW( TACCTL1 , TACCTL1_) 629 #define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */ 630 DEFW( TACCTL2 , TACCTL2_) 631 #define TAR_ (0x0170) /* Timer A */ 632 DEFW( TAR , TAR_) 633 #define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */ 634 DEFW( TACCR0 , TACCR0_) 635 #define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */ 636 DEFW( TACCR1 , TACCR1_) 637 #define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */ 638 DEFW( TACCR2 , TACCR2_) 639 640 /* Alternate register names */ 641 #define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */ 642 #define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */ 643 #define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */ 644 #define CCR0 TACCR0 /* Timer A Capture/Compare 0 */ 645 #define CCR1 TACCR1 /* Timer A Capture/Compare 1 */ 646 #define CCR2 TACCR2 /* Timer A Capture/Compare 2 */ 647 #define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */ 648 #define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */ 649 #define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */ 650 #define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */ 651 #define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */ 652 #define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */ 653 654 #define TASSEL1 (0x0200) /* Timer A clock source select 0 */ 655 #define TASSEL0 (0x0100) /* Timer A clock source select 1 */ 656 #define ID1 (0x0080) /* Timer A clock input divider 1 */ 657 #define ID0 (0x0040) /* Timer A clock input divider 0 */ 658 #define MC1 (0x0020) /* Timer A mode control 1 */ 659 #define MC0 (0x0010) /* Timer A mode control 0 */ 660 #define TACLR (0x0004) /* Timer A counter clear */ 661 #define TAIE (0x0002) /* Timer A counter interrupt enable */ 662 #define TAIFG (0x0001) /* Timer A counter interrupt flag */ 663 664 #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ 665 #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */ 666 #define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */ 667 #define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */ 668 #define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ 669 #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ 670 #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ 671 #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ 672 #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */ 673 #define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */ 674 #define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */ 675 #define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */ 676 677 #define CM1 (0x8000) /* Capture mode 1 */ 678 #define CM0 (0x4000) /* Capture mode 0 */ 679 #define CCIS1 (0x2000) /* Capture input select 1 */ 680 #define CCIS0 (0x1000) /* Capture input select 0 */ 681 #define SCS (0x0800) /* Capture sychronize */ 682 #define SCCI (0x0400) /* Latched capture signal (read) */ 683 #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */ 684 #define OUTMOD2 (0x0080) /* Output mode 2 */ 685 #define OUTMOD1 (0x0040) /* Output mode 1 */ 686 #define OUTMOD0 (0x0020) /* Output mode 0 */ 687 #define CCIE (0x0010) /* Capture/compare interrupt enable */ 688 #define CCI (0x0008) /* Capture input signal (read) */ 689 #define OUT (0x0004) /* PWM Output signal if output mode 0 */ 690 #define COV (0x0002) /* Capture/compare overflow flag */ 691 #define CCIFG (0x0001) /* Capture/compare interrupt flag */ 692 693 #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */ 694 #define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */ 695 #define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */ 696 #define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */ 697 #define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */ 698 #define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */ 699 #define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */ 700 #define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */ 701 #define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ 702 #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ 703 #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ 704 #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ 705 #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */ 706 #define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */ 707 #define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */ 708 #define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ 709 710 /************************************************************ 711 * Timer B7 712 ************************************************************/ 713 #define __MSP430_HAS_TB7__ /* Definition to show that Module is available */ 714 715 #define TBIV_ (0x011E) /* Timer B Interrupt Vector Word */ 716 READ_ONLY DEFW( TBIV , TBIV_) 717 #define TBCTL_ (0x0180) /* Timer B Control */ 718 DEFW( TBCTL , TBCTL_) 719 #define TBCCTL0_ (0x0182) /* Timer B Capture/Compare Control 0 */ 720 DEFW( TBCCTL0 , TBCCTL0_) 721 #define TBCCTL1_ (0x0184) /* Timer B Capture/Compare Control 1 */ 722 DEFW( TBCCTL1 , TBCCTL1_) 723 #define TBCCTL2_ (0x0186) /* Timer B Capture/Compare Control 2 */ 724 DEFW( TBCCTL2 , TBCCTL2_) 725 #define TBCCTL3_ (0x0188) /* Timer B Capture/Compare Control 3 */ 726 DEFW( TBCCTL3 , TBCCTL3_) 727 #define TBCCTL4_ (0x018A) /* Timer B Capture/Compare Control 4 */ 728 DEFW( TBCCTL4 , TBCCTL4_) 729 #define TBCCTL5_ (0x018C) /* Timer B Capture/Compare Control 5 */ 730 DEFW( TBCCTL5 , TBCCTL5_) 731 #define TBCCTL6_ (0x018E) /* Timer B Capture/Compare Control 6 */ 732 DEFW( TBCCTL6 , TBCCTL6_) 733 #define TBR_ (0x0190) /* Timer B */ 734 DEFW( TBR , TBR_) 735 #define TBCCR0_ (0x0192) /* Timer B Capture/Compare 0 */ 736 DEFW( TBCCR0 , TBCCR0_) 737 #define TBCCR1_ (0x0194) /* Timer B Capture/Compare 1 */ 738 DEFW( TBCCR1 , TBCCR1_) 739 #define TBCCR2_ (0x0196) /* Timer B Capture/Compare 2 */ 740 DEFW( TBCCR2 , TBCCR2_) 741 #define TBCCR3_ (0x0198) /* Timer B Capture/Compare 3 */ 742 DEFW( TBCCR3 , TBCCR3_) 743 #define TBCCR4_ (0x019A) /* Timer B Capture/Compare 4 */ 744 DEFW( TBCCR4 , TBCCR4_) 745 #define TBCCR5_ (0x019C) /* Timer B Capture/Compare 5 */ 746 DEFW( TBCCR5 , TBCCR5_) 747 #define TBCCR6_ (0x019E) /* Timer B Capture/Compare 6 */ 748 DEFW( TBCCR6 , TBCCR6_) 749 750 #define TBCLGRP1 (0x4000) /* Timer B Compare latch load group 1 */ 751 #define TBCLGRP0 (0x2000) /* Timer B Compare latch load group 0 */ 752 #define CNTL1 (0x1000) /* Counter lenght 1 */ 753 #define CNTL0 (0x0800) /* Counter lenght 0 */ 754 #define TBSSEL1 (0x0200) /* Clock source 1 */ 755 #define TBSSEL0 (0x0100) /* Clock source 0 */ 756 #define TBCLR (0x0004) /* Timer B counter clear */ 757 #define TBIE (0x0002) /* Timer B interrupt enable */ 758 #define TBIFG (0x0001) /* Timer B interrupt flag */ 759 760 #define SHR1 (0x4000) /* Timer B Compare latch load group 1 */ 761 #define SHR0 (0x2000) /* Timer B Compare latch load group 0 */ 762 763 #define TBSSEL_0 (0*0x0100u) /* Clock Source: TBCLK */ 764 #define TBSSEL_1 (1*0x0100u) /* Clock Source: ACLK */ 765 #define TBSSEL_2 (2*0x0100u) /* Clock Source: SMCLK */ 766 #define TBSSEL_3 (3*0x0100u) /* Clock Source: INCLK */ 767 #define CNTL_0 (0*0x0800u) /* Counter lenght: 16 bit */ 768 #define CNTL_1 (1*0x0800u) /* Counter lenght: 12 bit */ 769 #define CNTL_2 (2*0x0800u) /* Counter lenght: 10 bit */ 770 #define CNTL_3 (3*0x0800u) /* Counter lenght: 8 bit */ 771 #define SHR_0 (0*0x2000u) /* Timer B Group: 0 - individually */ 772 #define SHR_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ 773 #define SHR_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ 774 #define SHR_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */ 775 #define TBCLGRP_0 (0*0x2000u) /* Timer B Group: 0 - individually */ 776 #define TBCLGRP_1 (1*0x2000u) /* Timer B Group: 1 - 3 groups (1-2, 3-4, 5-6) */ 777 #define TBCLGRP_2 (2*0x2000u) /* Timer B Group: 2 - 2 groups (1-3, 4-6)*/ 778 #define TBCLGRP_3 (3*0x2000u) /* Timer B Group: 3 - 1 group (all) */ 779 780 /* Additional Timer B Control Register bits are defined in Timer A */ 781 #define CLLD1 (0x0400) /* Compare latch load source 1 */ 782 #define CLLD0 (0x0200) /* Compare latch load source 0 */ 783 784 #define SLSHR1 (0x0400) /* Compare latch load source 1 */ 785 #define SLSHR0 (0x0200) /* Compare latch load source 0 */ 786 787 #define SLSHR_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ 788 #define SLSHR_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ 789 #define SLSHR_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ 790 #define SLSHR_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ 791 792 #define CLLD_0 (0*0x0200u) /* Compare latch load sourec : 0 - immediate */ 793 #define CLLD_1 (1*0x0200u) /* Compare latch load sourec : 1 - TBR counts to 0 */ 794 #define CLLD_2 (2*0x0200u) /* Compare latch load sourec : 2 - up/down */ 795 #define CLLD_3 (3*0x0200u) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */ 796 797 /************************************************************ 798 * Basic Clock Module 799 ************************************************************/ 800 #define __MSP430_HAS_BASIC_CLOCK__ /* Definition to show that Module is available */ 801 802 #define DCOCTL_ (0x0056) /* DCO Clock Frequency Control */ 803 DEFC( DCOCTL , DCOCTL_) 804 #define BCSCTL1_ (0x0057) /* Basic Clock System Control 1 */ 805 DEFC( BCSCTL1 , BCSCTL1_) 806 #define BCSCTL2_ (0x0058) /* Basic Clock System Control 2 */ 807 DEFC( BCSCTL2 , BCSCTL2_) 808 809 #define MOD0 (0x01) /* Modulation Bit 0 */ 810 #define MOD1 (0x02) /* Modulation Bit 1 */ 811 #define MOD2 (0x04) /* Modulation Bit 2 */ 812 #define MOD3 (0x08) /* Modulation Bit 3 */ 813 #define MOD4 (0x10) /* Modulation Bit 4 */ 814 #define DCO0 (0x20) /* DCO Select Bit 0 */ 815 #define DCO1 (0x40) /* DCO Select Bit 1 */ 816 #define DCO2 (0x80) /* DCO Select Bit 2 */ 817 818 #define RSEL0 (0x01) /* Range Select Bit 0 */ 819 #define RSEL1 (0x02) /* Range Select Bit 1 */ 820 #define RSEL2 (0x04) /* Range Select Bit 2 */ 821 #define XT5V (0x08) /* XT5V should always be reset */ 822 #define DIVA0 (0x10) /* ACLK Divider 0 */ 823 #define DIVA1 (0x20) /* ACLK Divider 1 */ 824 #define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */ 825 #define XT2OFF (0x80) /* Enable XT2CLK */ 826 827 #define DIVA_0 (0x00) /* ACLK Divider 0: /1 */ 828 #define DIVA_1 (0x10) /* ACLK Divider 1: /2 */ 829 #define DIVA_2 (0x20) /* ACLK Divider 2: /4 */ 830 #define DIVA_3 (0x30) /* ACLK Divider 3: /8 */ 831 832 #define DCOR (0x01) /* Enable External Resistor : 1 */ 833 #define DIVS0 (0x02) /* SMCLK Divider 0 */ 834 #define DIVS1 (0x04) /* SMCLK Divider 1 */ 835 #define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */ 836 #define DIVM0 (0x10) /* MCLK Divider 0 */ 837 #define DIVM1 (0x20) /* MCLK Divider 1 */ 838 #define SELM0 (0x40) /* MCLK Source Select 0 */ 839 #define SELM1 (0x80) /* MCLK Source Select 1 */ 840 841 #define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */ 842 #define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */ 843 #define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */ 844 #define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */ 845 846 #define DIVM_0 (0x00) /* MCLK Divider 0: /1 */ 847 #define DIVM_1 (0x10) /* MCLK Divider 1: /2 */ 848 #define DIVM_2 (0x20) /* MCLK Divider 2: /4 */ 849 #define DIVM_3 (0x30) /* MCLK Divider 3: /8 */ 850 851 #define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ 852 #define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ 853 #define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */ 854 #define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ 855 856 /************************************************************ 857 * Brown-Out, Supply Voltage Supervision (SVS) 858 ************************************************************/ 859 #define __MSP430_HAS_SVS__ /* Definition to show that Module is available */ 860 861 #define SVSCTL_ (0x0055) /* SVS Control */ 862 DEFC( SVSCTL , SVSCTL_) 863 #define SVSFG (0x01) /* SVS Flag */ 864 #define SVSOP (0x02) /* SVS output (read only) */ 865 #define SVSON (0x04) /* Switches the SVS on/off */ 866 #define PORON (0x08) /* Enable POR Generation if Low Voltage */ 867 #define VLD0 (0x10) 868 #define VLD1 (0x20) 869 #define VLD2 (0x40) 870 #define VLD3 (0x80) 871 872 #define VLDON (0x10) 873 #define VLDOFF (0x00) 874 #define VLD_1_8V (0x10) 875 876 /************************************************************* 877 * Flash Memory 878 *************************************************************/ 879 #define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */ 880 881 #define FCTL1_ (0x0128) /* FLASH Control 1 */ 882 DEFW( FCTL1 , FCTL1_) 883 #define FCTL2_ (0x012A) /* FLASH Control 2 */ 884 DEFW( FCTL2 , FCTL2_) 885 #define FCTL3_ (0x012C) /* FLASH Control 3 */ 886 DEFW( FCTL3 , FCTL3_) 887 888 #define FRKEY (0x9600) /* Flash key returned by read */ 889 #define FWKEY (0xA500) /* Flash key for write */ 890 #define FXKEY (0x3300) /* for use with XOR instruction */ 891 892 #define ERASE (0x0002) /* Enable bit for Flash segment erase */ 893 #define MERAS (0x0004) /* Enable bit for Flash mass erase */ 894 #define WRT (0x0040) /* Enable bit for Flash write */ 895 #define BLKWRT (0x0080) /* Enable bit for Flash segment write */ 896 #define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */ 897 898 #define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */ 899 #define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */ 900 #ifndef FN2 901 #define FN2 (0x0004) 902 #endif 903 #ifndef FN3 904 #define FN3 (0x0008) 905 #endif 906 #ifndef FN4 907 #define FN4 (0x0010) 908 #endif 909 #define FN5 (0x0020) 910 #define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */ 911 #define FSSEL1 (0x0080) /* Flash clock select 1 */ 912 913 #define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ 914 #define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ 915 #define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ 916 #define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ 917 918 #define BUSY (0x0001) /* Flash busy: 1 */ 919 #define KEYV (0x0002) /* Flash Key violation flag */ 920 #define ACCVIFG (0x0004) /* Flash Access violation flag */ 921 #define WAIT (0x0008) /* Wait flag for segment write */ 922 #define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */ 923 #define EMEX (0x0020) /* Flash Emergency Exit */ 924 925 /************************************************************ 926 * Comparator A 927 ************************************************************/ 928 #define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */ 929 930 #define CACTL1_ (0x0059) /* Comparator A Control 1 */ 931 DEFC( CACTL1 , CACTL1_) 932 #define CACTL2_ (0x005A) /* Comparator A Control 2 */ 933 DEFC( CACTL2 , CACTL2_) 934 #define CAPD_ (0x005B) /* Comparator A Port Disable */ 935 DEFC( CAPD , CAPD_) 936 937 #define CAIFG (0x01) /* Comp. A Interrupt Flag */ 938 #define CAIE (0x02) /* Comp. A Interrupt Enable */ 939 #define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */ 940 #define CAON (0x08) /* Comp. A enable */ 941 #define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */ 942 #define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */ 943 #define CARSEL (0x40) /* Comp. A Internal Reference Enable */ 944 #define CAEX (0x80) /* Comp. A Exchange Inputs */ 945 946 #define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */ 947 #define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */ 948 #define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */ 949 #define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ 950 951 #define CAOUT (0x01) /* Comp. A Output */ 952 #define CAF (0x02) /* Comp. A Enable Output Filter */ 953 #define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */ 954 #define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */ 955 #define CACTL24 (0x10) 956 #define CACTL25 (0x20) 957 #define CACTL26 (0x40) 958 #define CACTL27 (0x80) 959 960 #define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */ 961 #define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */ 962 #define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */ 963 #define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */ 964 #define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */ 965 #define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */ 966 #define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */ 967 #define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */ 968 969 /************************************************************ 970 * ADC12 971 ************************************************************/ 972 #define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */ 973 974 #define ADC12CTL0_ (0x01A0) /* ADC12 Control 0 */ 975 DEFW( ADC12CTL0 , ADC12CTL0_) 976 #define ADC12CTL1_ (0x01A2) /* ADC12 Control 1 */ 977 DEFW( ADC12CTL1 , ADC12CTL1_) 978 #define ADC12IFG_ (0x01A4) /* ADC12 Interrupt Flag */ 979 DEFW( ADC12IFG , ADC12IFG_) 980 #define ADC12IE_ (0x01A6) /* ADC12 Interrupt Enable */ 981 DEFW( ADC12IE , ADC12IE_) 982 #define ADC12IV_ (0x01A8) /* ADC12 Interrupt Vector Word */ 983 DEFW( ADC12IV , ADC12IV_) 984 985 #define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */ 986 #ifndef __IAR_SYSTEMS_ICC 987 #define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */ 988 #else 989 #define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ 990 #endif 991 #define ADC12MEM0_ (0x0140) /* ADC12 Conversion Memory 0 */ 992 DEFW( ADC12MEM0 , ADC12MEM0_) 993 #define ADC12MEM1_ (0x0142) /* ADC12 Conversion Memory 1 */ 994 DEFW( ADC12MEM1 , ADC12MEM1_) 995 #define ADC12MEM2_ (0x0144) /* ADC12 Conversion Memory 2 */ 996 DEFW( ADC12MEM2 , ADC12MEM2_) 997 #define ADC12MEM3_ (0x0146) /* ADC12 Conversion Memory 3 */ 998 DEFW( ADC12MEM3 , ADC12MEM3_) 999 #define ADC12MEM4_ (0x0148) /* ADC12 Conversion Memory 4 */ 1000 DEFW( ADC12MEM4 , ADC12MEM4_) 1001 #define ADC12MEM5_ (0x014A) /* ADC12 Conversion Memory 5 */ 1002 DEFW( ADC12MEM5 , ADC12MEM5_) 1003 #define ADC12MEM6_ (0x014C) /* ADC12 Conversion Memory 6 */ 1004 DEFW( ADC12MEM6 , ADC12MEM6_) 1005 #define ADC12MEM7_ (0x014E) /* ADC12 Conversion Memory 7 */ 1006 DEFW( ADC12MEM7 , ADC12MEM7_) 1007 #define ADC12MEM8_ (0x0150) /* ADC12 Conversion Memory 8 */ 1008 DEFW( ADC12MEM8 , ADC12MEM8_) 1009 #define ADC12MEM9_ (0x0152) /* ADC12 Conversion Memory 9 */ 1010 DEFW( ADC12MEM9 , ADC12MEM9_) 1011 #define ADC12MEM10_ (0x0154) /* ADC12 Conversion Memory 10 */ 1012 DEFW( ADC12MEM10 , ADC12MEM10_) 1013 #define ADC12MEM11_ (0x0156) /* ADC12 Conversion Memory 11 */ 1014 DEFW( ADC12MEM11 , ADC12MEM11_) 1015 #define ADC12MEM12_ (0x0158) /* ADC12 Conversion Memory 12 */ 1016 DEFW( ADC12MEM12 , ADC12MEM12_) 1017 #define ADC12MEM13_ (0x015A) /* ADC12 Conversion Memory 13 */ 1018 DEFW( ADC12MEM13 , ADC12MEM13_) 1019 #define ADC12MEM14_ (0x015C) /* ADC12 Conversion Memory 14 */ 1020 DEFW( ADC12MEM14 , ADC12MEM14_) 1021 #define ADC12MEM15_ (0x015E) /* ADC12 Conversion Memory 15 */ 1022 DEFW( ADC12MEM15 , ADC12MEM15_) 1023 1024 #define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */ 1025 #ifndef __IAR_SYSTEMS_ICC 1026 #define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */ 1027 #else 1028 #define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ 1029 #endif 1030 #define ADC12MCTL0_ (0x0080) /* ADC12 Memory Control 0 */ 1031 DEFC( ADC12MCTL0 , ADC12MCTL0_) 1032 #define ADC12MCTL1_ (0x0081) /* ADC12 Memory Control 1 */ 1033 DEFC( ADC12MCTL1 , ADC12MCTL1_) 1034 #define ADC12MCTL2_ (0x0082) /* ADC12 Memory Control 2 */ 1035 DEFC( ADC12MCTL2 , ADC12MCTL2_) 1036 #define ADC12MCTL3_ (0x0083) /* ADC12 Memory Control 3 */ 1037 DEFC( ADC12MCTL3 , ADC12MCTL3_) 1038 #define ADC12MCTL4_ (0x0084) /* ADC12 Memory Control 4 */ 1039 DEFC( ADC12MCTL4 , ADC12MCTL4_) 1040 #define ADC12MCTL5_ (0x0085) /* ADC12 Memory Control 5 */ 1041 DEFC( ADC12MCTL5 , ADC12MCTL5_) 1042 #define ADC12MCTL6_ (0x0086) /* ADC12 Memory Control 6 */ 1043 DEFC( ADC12MCTL6 , ADC12MCTL6_) 1044 #define ADC12MCTL7_ (0x0087) /* ADC12 Memory Control 7 */ 1045 DEFC( ADC12MCTL7 , ADC12MCTL7_) 1046 #define ADC12MCTL8_ (0x0088) /* ADC12 Memory Control 8 */ 1047 DEFC( ADC12MCTL8 , ADC12MCTL8_) 1048 #define ADC12MCTL9_ (0x0089) /* ADC12 Memory Control 9 */ 1049 DEFC( ADC12MCTL9 , ADC12MCTL9_) 1050 #define ADC12MCTL10_ (0x008A) /* ADC12 Memory Control 10 */ 1051 DEFC( ADC12MCTL10 , ADC12MCTL10_) 1052 #define ADC12MCTL11_ (0x008B) /* ADC12 Memory Control 11 */ 1053 DEFC( ADC12MCTL11 , ADC12MCTL11_) 1054 #define ADC12MCTL12_ (0x008C) /* ADC12 Memory Control 12 */ 1055 DEFC( ADC12MCTL12 , ADC12MCTL12_) 1056 #define ADC12MCTL13_ (0x008D) /* ADC12 Memory Control 13 */ 1057 DEFC( ADC12MCTL13 , ADC12MCTL13_) 1058 #define ADC12MCTL14_ (0x008E) /* ADC12 Memory Control 14 */ 1059 DEFC( ADC12MCTL14 , ADC12MCTL14_) 1060 #define ADC12MCTL15_ (0x008F) /* ADC12 Memory Control 15 */ 1061 DEFC( ADC12MCTL15 , ADC12MCTL15_) 1062 1063 /* ADC12CTL0 */ 1064 #define ADC12SC (0x001) /* ADC12 Start Conversion */ 1065 #define ENC (0x002) /* ADC12 Enable Conversion */ 1066 #define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */ 1067 #define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */ 1068 #define ADC12ON (0x010) /* ADC12 On/enable */ 1069 #define REFON (0x020) /* ADC12 Reference on */ 1070 #define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */ 1071 #define MSC (0x080) /* ADC12 Multiple SampleConversion */ 1072 #define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */ 1073 #define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */ 1074 #define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */ 1075 #define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */ 1076 #define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */ 1077 #define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */ 1078 #define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */ 1079 #define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */ 1080 #define MSH (0x080) 1081 1082 #define SHT0_0 (0*0x100u) 1083 #define SHT0_1 (1*0x100u) 1084 #define SHT0_2 (2*0x100u) 1085 #define SHT0_3 (3*0x100u) 1086 #define SHT0_4 (4*0x100u) 1087 #define SHT0_5 (5*0x100u) 1088 #define SHT0_6 (6*0x100u) 1089 #define SHT0_7 (7*0x100u) 1090 #define SHT0_8 (8*0x100u) 1091 #define SHT0_9 (9*0x100u) 1092 #define SHT0_10 (10*0x100u) 1093 #define SHT0_11 (11*0x100u) 1094 #define SHT0_12 (12*0x100u) 1095 #define SHT0_13 (13*0x100u) 1096 #define SHT0_14 (14*0x100u) 1097 #define SHT0_15 (15*0x100u) 1098 1099 #define SHT1_0 (0*0x1000u) 1100 #define SHT1_1 (1*0x1000u) 1101 #define SHT1_2 (2*0x1000u) 1102 #define SHT1_3 (3*0x1000u) 1103 #define SHT1_4 (4*0x1000u) 1104 #define SHT1_5 (5*0x1000u) 1105 #define SHT1_6 (6*0x1000u) 1106 #define SHT1_7 (7*0x1000u) 1107 #define SHT1_8 (8*0x1000u) 1108 #define SHT1_9 (9*0x1000u) 1109 #define SHT1_10 (10*0x1000u) 1110 #define SHT1_11 (11*0x1000u) 1111 #define SHT1_12 (12*0x1000u) 1112 #define SHT1_13 (13*0x1000u) 1113 #define SHT1_14 (14*0x1000u) 1114 #define SHT1_15 (15*0x1000u) 1115 1116 /* ADC12CTL1 */ 1117 #define ADC12BUSY (0x0001) /* ADC12 Busy */ 1118 #define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */ 1119 #define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */ 1120 #define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */ 1121 #define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */ 1122 #define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */ 1123 #define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */ 1124 #define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */ 1125 #define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */ 1126 #define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */ 1127 #define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */ 1128 #define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */ 1129 #define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */ 1130 #define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */ 1131 #define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */ 1132 #define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */ 1133 1134 #define CONSEQ_0 (0*2u) 1135 #define CONSEQ_1 (1*2u) 1136 #define CONSEQ_2 (2*2u) 1137 #define CONSEQ_3 (3*2u) 1138 #define ADC12SSEL_0 (0*8u) 1139 #define ADC12SSEL_1 (1*8u) 1140 #define ADC12SSEL_2 (2*8u) 1141 #define ADC12SSEL_3 (3*8u) 1142 #define ADC12DIV_0 (0*0x20u) 1143 #define ADC12DIV_1 (1*0x20u) 1144 #define ADC12DIV_2 (2*0x20u) 1145 #define ADC12DIV_3 (3*0x20u) 1146 #define ADC12DIV_4 (4*0x20u) 1147 #define ADC12DIV_5 (5*0x20u) 1148 #define ADC12DIV_6 (6*0x20u) 1149 #define ADC12DIV_7 (7*0x20u) 1150 #define SHS_0 (0*0x400u) 1151 #define SHS_1 (1*0x400u) 1152 #define SHS_2 (2*0x400u) 1153 #define SHS_3 (3*0x400u) 1154 #define CSTARTADD_0 (0*0x1000u) 1155 #define CSTARTADD_1 (1*0x1000u) 1156 #define CSTARTADD_2 (2*0x1000u) 1157 #define CSTARTADD_3 (3*0x1000u) 1158 #define CSTARTADD_4 (4*0x1000u) 1159 #define CSTARTADD_5 (5*0x1000u) 1160 #define CSTARTADD_6 (6*0x1000u) 1161 #define CSTARTADD_7 (7*0x1000u) 1162 #define CSTARTADD_8 (8*0x1000u) 1163 #define CSTARTADD_9 (9*0x1000u) 1164 #define CSTARTADD_10 (10*0x1000u) 1165 #define CSTARTADD_11 (11*0x1000u) 1166 #define CSTARTADD_12 (12*0x1000u) 1167 #define CSTARTADD_13 (13*0x1000u) 1168 #define CSTARTADD_14 (14*0x1000u) 1169 #define CSTARTADD_15 (15*0x1000u) 1170 1171 /* ADC12MCTLx */ 1172 #define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */ 1173 #define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */ 1174 #define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */ 1175 #define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */ 1176 #define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */ 1177 #define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */ 1178 #define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */ 1179 #define EOS (0x0080) /* ADC12 End of Sequence */ 1180 1181 #define INCH_0 (0) 1182 #define INCH_1 (1) 1183 #define INCH_2 (2) 1184 #define INCH_3 (3) 1185 #define INCH_4 (4) 1186 #define INCH_5 (5) 1187 #define INCH_6 (6) 1188 #define INCH_7 (7) 1189 #define INCH_8 (8) 1190 #define INCH_9 (9) 1191 #define INCH_10 (10) 1192 #define INCH_11 (11) 1193 #define INCH_12 (12) 1194 #define INCH_13 (13) 1195 #define INCH_14 (14) 1196 #define INCH_15 (15) 1197 1198 #define SREF_0 (0*0x10u) 1199 #define SREF_1 (1*0x10u) 1200 #define SREF_2 (2*0x10u) 1201 #define SREF_3 (3*0x10u) 1202 #define SREF_4 (4*0x10u) 1203 #define SREF_5 (5*0x10u) 1204 #define SREF_6 (6*0x10u) 1205 #define SREF_7 (7*0x10u) 1206 1207 /************************************************************ 1208 * DAC12 1209 ************************************************************/ 1210 #define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */ 1211 1212 #define DAC12_0CTL_ (0x01c0) /* DAC12_0 Control */ 1213 DEFW( DAC12_0CTL , DAC12_0CTL_) 1214 #define DAC12_1CTL_ (0x01c2) /* DAC12_1 Control */ 1215 DEFW( DAC12_1CTL , DAC12_1CTL_) 1216 1217 #define DAC12GRP (0x0001) /* DAC12 group */ 1218 #define DAC12ENC (0x0002) /* DAC12 enable conversion */ 1219 #define DAC12IFG (0x0004) /* DAC12 interrupt flag */ 1220 #define DAC12IE (0x0008) /* DAC12 interrupt enable */ 1221 #define DAC12DF (0x0010) /* DAC12 data format */ 1222 #define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */ 1223 #define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */ 1224 #define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */ 1225 #define DAC12IR (0x0100) /* DAC12 input reference and output range */ 1226 #define DAC12CALON (0x0200) /* DAC12 calibration */ 1227 #define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */ 1228 #define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */ 1229 #define DAC12RES (0x1000) /* DAC12 resolution */ 1230 #define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */ 1231 #define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */ 1232 1233 #define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */ 1234 #define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */ 1235 #define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */ 1236 #define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */ 1237 #define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */ 1238 #define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */ 1239 #define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */ 1240 #define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */ 1241 1242 #define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */ 1243 #define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */ 1244 #define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */ 1245 #define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */ 1246 1247 #define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */ 1248 #define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */ 1249 #define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */ 1250 #define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */ 1251 1252 #define DAC12_0DAT_ (0x01c8) /* DAC12_0 Data */ 1253 DEFW( DAC12_0DAT , DAC12_0DAT_) 1254 #define DAC12_1DAT_ (0x01ca) /* DAC12_1 Data */ 1255 DEFW( DAC12_1DAT , DAC12_1DAT_) 1256 /************************************************************ 1257 * DMA 1258 ************************************************************/ 1259 #define __MSP430_HAS_DMA_3__ /* Definition to show that Module is available */ 1260 1261 #define DMACTL0_ (0x0122) /* DMA Module Control 0 */ 1262 DEFW( DMACTL0 , DMACTL0_) 1263 #define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */ 1264 #define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */ 1265 #define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */ 1266 #define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */ 1267 #define DMA1TSEL0 (0x0010) /* DMA channel 1 transfer select bit 0 */ 1268 #define DMA1TSEL1 (0x0020) /* DMA channel 1 transfer select bit 1 */ 1269 #define DMA1TSEL2 (0x0040) /* DMA channel 1 transfer select bit 2 */ 1270 #define DMA1TSEL3 (0x0080) /* DMA channel 1 transfer select bit 3 */ 1271 #define DMA2TSEL0 (0x0100) /* DMA channel 2 transfer select bit 0 */ 1272 #define DMA2TSEL1 (0x0200) /* DMA channel 2 transfer select bit 1 */ 1273 #define DMA2TSEL2 (0x0400) /* DMA channel 2 transfer select bit 2 */ 1274 #define DMA2TSEL3 (0x0800) /* DMA channel 2 transfer select bit 3 */ 1275 1276 #define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw)*/ 1277 #define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */ 1278 #define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */ 1279 #define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3: UART0/I2C receive */ 1280 #define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4: UART0/I2C transmit */ 1281 #define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG */ 1282 #define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */ 1283 #define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */ 1284 #define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */ 1285 #define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9: UART1 receive */ 1286 #define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10: UART1 transmit */ 1287 #define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11: Multiplier ready */ 1288 #define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */ 1289 #define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */ 1290 1291 #define DMA1TSEL_0 (0*0x0010u) /* DMA channel 1 transfer select 0: DMA_REQ */ 1292 #define DMA1TSEL_1 (1*0x0010u) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */ 1293 #define DMA1TSEL_2 (2*0x0010u) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */ 1294 #define DMA1TSEL_3 (3*0x0010u) /* DMA channel 1 transfer select 3: UART0/I2C receive */ 1295 #define DMA1TSEL_4 (4*0x0010u) /* DMA channel 1 transfer select 4: UART0/I2C transmit */ 1296 #define DMA1TSEL_5 (5*0x0010u) /* DMA channel 1 transfer select 5: DAC12.0IFG */ 1297 #define DMA1TSEL_6 (6*0x0010u) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */ 1298 #define DMA1TSEL_7 (7*0x0010u) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */ 1299 #define DMA1TSEL_8 (8*0x0010u) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */ 1300 #define DMA1TSEL_9 (9*0x0010u) /* DMA channel 1 transfer select 9: UART1 receive */ 1301 #define DMA1TSEL_10 (10*0x0010u) /* DMA channel 1 transfer select 10: UART1 transmit */ 1302 #define DMA1TSEL_11 (11*0x0010u) /* DMA channel 1 transfer select 11: Multiplier ready */ 1303 #define DMA1TSEL_14 (14*0x0010u) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */ 1304 #define DMA1TSEL_15 (15*0x0010u) /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */ 1305 1306 #define DMA2TSEL_0 (0*0x0100u) /* DMA channel 2 transfer select 0: DMA_REQ */ 1307 #define DMA2TSEL_1 (1*0x0100u) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */ 1308 #define DMA2TSEL_2 (2*0x0100u) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */ 1309 #define DMA2TSEL_3 (3*0x0100u) /* DMA channel 2 transfer select 3: UART0/I2C receive */ 1310 #define DMA2TSEL_4 (4*0x0100u) /* DMA channel 2 transfer select 4: UART0/I2C transmit */ 1311 #define DMA2TSEL_5 (5*0x0100u) /* DMA channel 2 transfer select 5: DAC12.0IFG */ 1312 #define DMA2TSEL_6 (6*0x0100u) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */ 1313 #define DMA2TSEL_7 (7*0x0100u) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */ 1314 #define DMA2TSEL_8 (8*0x0100u) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */ 1315 #define DMA2TSEL_9 (9*0x0100u) /* DMA channel 2 transfer select 9: UART1 receive */ 1316 #define DMA2TSEL_10 (10*0x0100u) /* DMA channel 2 transfer select 10: UART1 transmit */ 1317 #define DMA2TSEL_11 (11*0x0100u) /* DMA channel 2 transfer select 11: Multiplier ready */ 1318 #define DMA2TSEL_14 (14*0x0100u) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */ 1319 #define DMA2TSEL_15 (15*0x0100u) /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */ 1320 1321 #define DMACTL1_ (0x0124) /* DMA Module Control 1 */ 1322 DEFW( DMACTL1 , DMACTL1_) 1323 #define ENNMI (0x0001) /* Enable NMI interruption of DMA */ 1324 #define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */ 1325 #define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */ 1326 1327 #define DMA0CTL_ (0x01e0) /* DMA Channel 0 Control */ 1328 DEFW( DMA0CTL , DMA0CTL_) 1329 #define DMA1CTL_ (0x01e8) /* DMA Channel 1 Control */ 1330 DEFW( DMA1CTL , DMA1CTL_) 1331 #define DMA2CTL_ (0x01f0) /* DMA Channel 2 Control */ 1332 DEFW( DMA2CTL , DMA2CTL_) 1333 1334 #define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */ 1335 #define DMAABORT (0x0002) /* DMA transfer aborted by NMI */ 1336 #define DMAIE (0x0004) /* DMA interrupt enable */ 1337 #define DMAIFG (0x0008) /* DMA interrupt flag */ 1338 #define DMAEN (0x0010) /* DMA enable */ 1339 #define DMALEVEL (0x0020) /* DMA level sensitive trigger select */ 1340 #define DMASRCBYTE (0x0040) /* DMA source byte */ 1341 #define DMADSTBYTE (0x0080) /* DMA destination byte */ 1342 #define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */ 1343 #define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */ 1344 #define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */ 1345 #define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */ 1346 #define DMADT0 (0x1000) /* DMA transfer mode bit 0 */ 1347 #define DMADT1 (0x2000) /* DMA transfer mode bit 1 */ 1348 #define DMADT2 (0x4000) /* DMA transfer mode bit 2 */ 1349 1350 #define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */ 1351 #define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */ 1352 #define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */ 1353 #define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */ 1354 1355 #define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */ 1356 #define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */ 1357 #define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */ 1358 #define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */ 1359 1360 #define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */ 1361 #define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */ 1362 #define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */ 1363 #define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */ 1364 1365 #define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: single */ 1366 #define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: block */ 1367 #define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: interleaved */ 1368 #define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: interleaved */ 1369 #define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: single, repeat */ 1370 #define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: block, repeat */ 1371 #define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: interleaved, repeat */ 1372 #define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: interleaved, repeat */ 1373 1374 #define DMA0SA_ (0x01e2) /* DMA Channel 0 Source Address */ 1375 DEFW( DMA0SA , DMA0SA_) 1376 #define DMA0DA_ (0x01e4) /* DMA Channel 0 Destination Address */ 1377 DEFW( DMA0DA , DMA0DA_) 1378 #define DMA0SZ_ (0x01e6) /* DMA Channel 0 Transfer Size */ 1379 DEFW( DMA0SZ , DMA0SZ_) 1380 #define DMA1SA_ (0x01ea) /* DMA Channel 1 Source Address */ 1381 DEFW( DMA1SA , DMA1SA_) 1382 #define DMA1DA_ (0x01ec) /* DMA Channel 1 Destination Address */ 1383 DEFW( DMA1DA , DMA1DA_) 1384 #define DMA1SZ_ (0x01ee) /* DMA Channel 1 Transfer Size */ 1385 DEFW( DMA1SZ , DMA1SZ_) 1386 #define DMA2SA_ (0x01f2) /* DMA Channel 2 Source Address */ 1387 DEFW( DMA2SA , DMA2SA_) 1388 #define DMA2DA_ (0x01f4) /* DMA Channel 2 Destination Address */ 1389 DEFW( DMA2DA , DMA2DA_) 1390 #define DMA2SZ_ (0x01f6) /* DMA Channel 2 Transfer Size */ 1391 DEFW( DMA2SZ , DMA2SZ_) 1392 1393 /************************************************************ 1394 * Interrupt Vectors (offset from 0xFFE0) 1395 ************************************************************/ 1396 1397 #define DACDMA_VECTOR (0 * 2u) /* 0xFFE0 DAC/DMA */ 1398 #define PORT2_VECTOR (1 * 2u) /* 0xFFE2 Port 2 */ 1399 #define USART1TX_VECTOR (2 * 2u) /* 0xFFE4 USART 1 Transmit */ 1400 #define USART1RX_VECTOR (3 * 2u) /* 0xFFE6 USART 1 Receive */ 1401 #define PORT1_VECTOR (4 * 2u) /* 0xFFE8 Port 1 */ 1402 #define TIMERA1_VECTOR (5 * 2u) /* 0xFFEA Timer A CC1-2, TA */ 1403 #define TIMERA0_VECTOR (6 * 2u) /* 0xFFEC Timer A CC0 */ 1404 #define ADC12_VECTOR (7 * 2u) /* 0xFFEE ADC */ 1405 #define USART0TX_VECTOR (8 * 2u) /* 0xFFF0 USART 0 Transmit */ 1406 #define USART0RX_VECTOR (9 * 2u) /* 0xFFF2 USART 0 Receive */ 1407 #define WDT_VECTOR (10 * 2u) /* 0xFFF4 Watchdog Timer */ 1408 #define COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6 Comparator A */ 1409 #define TIMERB1_VECTOR (12 * 2u) /* 0xFFF8 Timer B CC1-6, TB */ 1410 #define TIMERB0_VECTOR (13 * 2u) /* 0xFFFA Timer B CC0 */ 1411 #define NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maskable */ 1412 #define RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [Highest Priority] */ 1413 1414 #define UART1TX_VECTOR USART1TX_VECTOR 1415 #define UART1RX_VECTOR USART1RX_VECTOR 1416 #define UART0TX_VECTOR USART0TX_VECTOR 1417 #define UART0RX_VECTOR USART0RX_VECTOR 1418 #define ADC_VECTOR ADC12_VECTOR 1419 1420 /************************************************************ 1421 * End of Modules 1422 ************************************************************/ 1423 #pragma language=default 1424 1425 #endif /* #ifndef __msp430x16x */ 1426 1427