1 /**
2 * Copyright (C) Mellanox Technologies Ltd. 2001-2018. ALL RIGHTS RESERVED.
3 *
4 * See file LICENSE for terms.
5 */
6
7 #ifndef UCT_IB_MLX5_IFC_H_
8 #define UCT_IB_MLX5_IFC_H_
9
10 #include <ucs/sys/compiler_def.h>
11
12 #include <stdint.h>
13 #include <endian.h>
14 #include <linux/types.h>
15
16 #define __uct_nullp(_typ) ((struct uct_ib_mlx5_##_typ##_bits *)0)
17 #define __uct_bit_sz(_typ, _fld) sizeof(__uct_nullp(_typ)->_fld)
18 #define __uct_bit_off(_typ, _fld) (offsetof(struct uct_ib_mlx5_##_typ##_bits, _fld))
19 #define __uct_dw_off(_typ, _fld) (__uct_bit_off(_typ, _fld) / 32)
20 #define __uct_64_off(_typ, _fld) (__uct_bit_off(_typ, _fld) / 64)
21 #define __uct_dw_bit_off(_typ, _fld) (32 - __uct_bit_sz(_typ, _fld) - (__uct_bit_off(_typ, _fld) & 0x1f))
22 #define __uct_mask(_typ, _fld) ((uint32_t)((1ull << __uct_bit_sz(_typ, _fld)) - 1))
23 #define __uct_dw_mask(_typ, _fld) (__uct_mask(_typ, _fld) << __uct_dw_bit_off(_typ, _fld))
24 #define __uct_st_sz_bits(_typ) sizeof(struct uct_ib_mlx5_##_typ##_bits)
25
26 #define UCT_IB_MLX5DV_FLD_SZ_BYTES(_typ, _fld) (__uct_bit_sz(_typ, _fld) / 8)
27 #define UCT_IB_MLX5DV_ST_SZ_BYTES(_typ) (sizeof(struct uct_ib_mlx5_##_typ##_bits) / 8)
28 #define UCT_IB_MLX5DV_ST_SZ_DW(_typ) (sizeof(struct uct_ib_mlx5_##_typ##_bits) / 32)
29 #define UCT_IB_MLX5DV_ST_SZ_QW(_typ) (sizeof(struct uct_ib_mlx5_##_typ##_bits) / 64)
30 #define UCT_IB_MLX5DV_UN_SZ_BYTES(_typ) (sizeof(union uct_ib_mlx5_##_typ##_bits) / 8)
31 #define UCT_IB_MLX5DV_UN_SZ_DW(_typ) (sizeof(union uct_ib_mlx5_##_typ##_bits) / 32)
32 #define UCT_IB_MLX5DV_BYTE_OFF(_typ, _fld) (__uct_bit_off(_typ, _fld) / 8)
33 #define UCT_IB_MLX5DV_ADDR_OF(_typ, _p, _fld) ((char *)(_p) + UCT_IB_MLX5DV_BYTE_OFF(_typ, _fld))
34
35 /* insert a value to a struct */
36 #define UCT_IB_MLX5DV_SET(_typ, _p, _fld, _v) \
37 do { \
38 char *___p = _p; \
39 uint32_t ___v = _v; \
40 uint32_t ___h; \
41 UCS_STATIC_ASSERT(__uct_st_sz_bits(_typ) % 32 == 0); \
42 ___h = (be32toh(*((__be32 *)(___p) + __uct_dw_off(_typ, _fld))) & \
43 (~__uct_dw_mask(_typ, _fld))) | \
44 (((___v) & __uct_mask(_typ, _fld)) << \
45 __uct_dw_bit_off(_typ, _fld)); \
46 *((__be32 *)(___p) + __uct_dw_off(_typ, _fld)) = htobe32(___h); \
47 } while (0)
48
49 #define UCT_IB_MLX5DV_GET(_typ, _p, _fld) \
50 ((be32toh(*((__be32 *)(_p) + \
51 __uct_dw_off(_typ, _fld))) >> __uct_dw_bit_off(_typ, _fld)) & \
52 __uct_mask(_typ, _fld))
53
54 #define UCT_IB_MLX5DV_SET64(_typ, _p, _fld, _v) \
55 do { \
56 UCS_STATIC_ASSERT(__uct_st_sz_bits(_typ) % 64 == 0); \
57 UCS_STATIC_ASSERT(__uct_bit_sz(_typ, _fld) == 64); \
58 *((__be64 *)(_p) + __uct_64_off(_typ, _fld)) = htobe64(_v); \
59 } while (0)
60
61 #define UCT_IB_MLX5DV_GET64(_typ, _p, _fld) \
62 be64toh(*((__be64 *)(_p) + __uct_64_off(_typ, _fld)))
63
64 enum {
65 UCT_IB_MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
66 UCT_IB_MLX5_CMD_OP_CREATE_MKEY = 0x200,
67 UCT_IB_MLX5_CMD_OP_CREATE_QP = 0x500,
68 UCT_IB_MLX5_CMD_OP_RST2INIT_QP = 0x502,
69 UCT_IB_MLX5_CMD_OP_INIT2RTR_QP = 0x503,
70 UCT_IB_MLX5_CMD_OP_RTR2RTS_QP = 0x504,
71 UCT_IB_MLX5_CMD_OP_2ERR_QP = 0x507,
72 UCT_IB_MLX5_CMD_OP_2RST_QP = 0x50a,
73 UCT_IB_MLX5_CMD_OP_CREATE_RMP = 0x90c,
74 UCT_IB_MLX5_CMD_OP_CREATE_DCT = 0x710,
75 UCT_IB_MLX5_CMD_OP_DRAIN_DCT = 0x712,
76 UCT_IB_MLX5_CMD_OP_CREATE_XRQ = 0x717,
77 UCT_IB_MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726
78 };
79
80 enum {
81 UCT_IB_MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
82 UCT_IB_MLX5_HCA_CAP_OPMOD_GET_CUR = 1
83 };
84
85 enum {
86 UCT_IB_MLX5_CAP_GENERAL = 0,
87 UCT_IB_MLX5_CAP_ODP = 2,
88 UCT_IB_MLX5_CAP_ATOMIC = 3,
89 };
90
91 struct uct_ib_mlx5_cmd_hca_cap_bits {
92 uint8_t reserved_at_0[0x30];
93 uint8_t vhca_id[0x10];
94
95 uint8_t reserved_at_40[0x40];
96
97 uint8_t log_max_srq_sz[0x8];
98 uint8_t log_max_qp_sz[0x8];
99 uint8_t reserved_at_90[0xb];
100 uint8_t log_max_qp[0x5];
101
102 uint8_t reserved_at_a0[0xb];
103 uint8_t log_max_srq[0x5];
104 uint8_t reserved_at_b0[0x10];
105
106 uint8_t reserved_at_c0[0x8];
107 uint8_t log_max_cq_sz[0x8];
108 uint8_t reserved_at_d0[0xb];
109 uint8_t log_max_cq[0x5];
110
111 uint8_t log_max_eq_sz[0x8];
112 uint8_t reserved_at_e8[0x2];
113 uint8_t log_max_mkey[0x6];
114 uint8_t reserved_at_f0[0x4];
115 uint8_t cmd_on_behalf[0x1];
116 uint8_t device_emulation_manager[0x1];
117 uint8_t reserved_at_f6[0x6];
118 uint8_t log_max_eq[0x4];
119
120 uint8_t max_indirection[0x8];
121 uint8_t fixed_buffer_size[0x1];
122 uint8_t log_max_mrw_sz[0x7];
123 uint8_t force_teardown[0x1];
124 uint8_t reserved_at_111[0x1];
125 uint8_t log_max_bsf_list_size[0x6];
126 uint8_t umr_extended_translation_offset[0x1];
127 uint8_t null_mkey[0x1];
128 uint8_t log_max_klm_list_size[0x6];
129
130 uint8_t reserved_at_120[0xa];
131 uint8_t log_max_ra_req_dc[0x6];
132 uint8_t reserved_at_130[0xa];
133 uint8_t log_max_ra_res_dc[0x6];
134
135 uint8_t reserved_at_140[0xa];
136 uint8_t log_max_ra_req_qp[0x6];
137 uint8_t reserved_at_150[0xa];
138 uint8_t log_max_ra_res_qp[0x6];
139
140 uint8_t end_pad[0x1];
141 uint8_t cc_query_allowed[0x1];
142 uint8_t cc_modify_allowed[0x1];
143 uint8_t start_pad[0x1];
144 uint8_t cache_line_128byte[0x1];
145 uint8_t reserved_at_165[0xa];
146 uint8_t qcam_reg[0x1];
147 uint8_t gid_table_size[0x10];
148
149 uint8_t out_of_seq_cnt[0x1];
150 uint8_t vport_counters[0x1];
151 uint8_t retransmission_q_counters[0x1];
152 uint8_t debug[0x1];
153 uint8_t modify_rq_counter_set_id[0x1];
154 uint8_t rq_delay_drop[0x1];
155 uint8_t max_qp_cnt[0xa];
156 uint8_t pkey_table_size[0x10];
157
158 uint8_t vport_group_manager[0x1];
159 uint8_t vhca_group_manager[0x1];
160 uint8_t ib_virt[0x1];
161 uint8_t eth_virt[0x1];
162 uint8_t vnic_env_queue_counters[0x1];
163 uint8_t ets[0x1];
164 uint8_t nic_flow_table[0x1];
165 uint8_t eswitch_flow_table[0x1];
166 uint8_t device_memory[0x1];
167 uint8_t mcam_reg[0x1];
168 uint8_t pcam_reg[0x1];
169 uint8_t local_ca_ack_delay[0x5];
170 uint8_t port_module_event[0x1];
171 uint8_t enhanced_error_q_counters[0x1];
172 uint8_t ports_check[0x1];
173 uint8_t reserved_at_1b3[0x1];
174 uint8_t disable_link_up[0x1];
175 uint8_t beacon_led[0x1];
176 uint8_t port_type[0x2];
177 uint8_t num_ports[0x8];
178
179 uint8_t reserved_at_1c0[0x1];
180 uint8_t pps[0x1];
181 uint8_t pps_modify[0x1];
182 uint8_t log_max_msg[0x5];
183 uint8_t reserved_at_1c8[0x4];
184 uint8_t max_tc[0x4];
185 uint8_t reserved_at_1d0[0x1];
186 uint8_t dcbx[0x1];
187 uint8_t general_notification_event[0x1];
188 uint8_t reserved_at_1d3[0x2];
189 uint8_t fpga[0x1];
190 uint8_t rol_s[0x1];
191 uint8_t rol_g[0x1];
192 uint8_t reserved_at_1d8[0x1];
193 uint8_t wol_s[0x1];
194 uint8_t wol_g[0x1];
195 uint8_t wol_a[0x1];
196 uint8_t wol_b[0x1];
197 uint8_t wol_m[0x1];
198 uint8_t wol_u[0x1];
199 uint8_t wol_p[0x1];
200
201 uint8_t stat_rate_support[0x10];
202 uint8_t reserved_at_1f0[0xc];
203 uint8_t cqe_version[0x4];
204
205 uint8_t compact_address_vector[0x1];
206 uint8_t striding_rq[0x1];
207 uint8_t reserved_at_202[0x1];
208 uint8_t ipoib_enhanced_offloads[0x1];
209 uint8_t ipoib_basic_offloads[0x1];
210 uint8_t reserved_at_205[0x1];
211 uint8_t repeated_block_disabled[0x1];
212 uint8_t umr_modify_entity_size_disabled[0x1];
213 uint8_t umr_modify_atomic_disabled[0x1];
214 uint8_t umr_indirect_mkey_disabled[0x1];
215 uint8_t umr_fence[0x2];
216 uint8_t reserved_at_20c[0x3];
217 uint8_t drain_sigerr[0x1];
218 uint8_t cmdif_checksum[0x2];
219 uint8_t sigerr_cqe[0x1];
220 uint8_t reserved_at_213[0x1];
221 uint8_t wq_signature[0x1];
222 uint8_t sctr_data_cqe[0x1];
223 uint8_t reserved_at_216[0x1];
224 uint8_t sho[0x1];
225 uint8_t tph[0x1];
226 uint8_t rf[0x1];
227 uint8_t dct[0x1];
228 uint8_t qos[0x1];
229 uint8_t eth_net_offloads[0x1];
230 uint8_t roce[0x1];
231 uint8_t atomic[0x1];
232 uint8_t reserved_at_21f[0x1];
233
234 uint8_t cq_oi[0x1];
235 uint8_t cq_resize[0x1];
236 uint8_t cq_moderation[0x1];
237 uint8_t reserved_at_223[0x3];
238 uint8_t cq_eq_remap[0x1];
239 uint8_t pg[0x1];
240 uint8_t block_lb_mc[0x1];
241 uint8_t reserved_at_229[0x1];
242 uint8_t scqe_break_moderation[0x1];
243 uint8_t cq_period_start_from_cqe[0x1];
244 uint8_t cd[0x1];
245 uint8_t reserved_at_22d[0x1];
246 uint8_t apm[0x1];
247 uint8_t vector_calc[0x1];
248 uint8_t umr_ptr_rlky[0x1];
249 uint8_t imaicl[0x1];
250 uint8_t reserved_at_232[0x4];
251 uint8_t qkv[0x1];
252 uint8_t pkv[0x1];
253 uint8_t set_deth_sqpn[0x1];
254 uint8_t reserved_at_239[0x3];
255 uint8_t xrc[0x1];
256 uint8_t ud[0x1];
257 uint8_t uc[0x1];
258 uint8_t rc[0x1];
259
260 uint8_t uar_4k[0x1];
261 uint8_t reserved_at_241[0x9];
262 uint8_t uar_sz[0x6];
263 uint8_t reserved_at_250[0x8];
264 uint8_t log_pg_sz[0x8];
265
266 uint8_t bf[0x1];
267 uint8_t driver_version[0x1];
268 uint8_t pad_tx_eth_packet[0x1];
269 uint8_t reserved_at_263[0x8];
270 uint8_t log_bf_reg_size[0x5];
271
272 uint8_t reserved_at_270[0xb];
273 uint8_t lag_master[0x1];
274 uint8_t num_lag_ports[0x4];
275
276 uint8_t reserved_at_280[0x10];
277 uint8_t max_wqe_sz_sq[0x10];
278
279 uint8_t reserved_at_2a0[0x10];
280 uint8_t max_wqe_sz_rq[0x10];
281
282 uint8_t max_flow_counter_31_16[0x10];
283 uint8_t max_wqe_sz_sq_dc[0x10];
284
285 uint8_t reserved_at_2e0[0x7];
286 uint8_t max_qp_mcg[0x19];
287
288 uint8_t reserved_at_300[0x18];
289 uint8_t log_max_mcg[0x8];
290
291 uint8_t reserved_at_320[0x3];
292 uint8_t log_max_transport_domain[0x5];
293 uint8_t reserved_at_328[0x3];
294 uint8_t log_max_pd[0x5];
295 uint8_t reserved_at_330[0xb];
296 uint8_t log_max_xrcd[0x5];
297
298 uint8_t nic_receive_steering_discard[0x1];
299 uint8_t receive_discard_vport_down[0x1];
300 uint8_t transmit_discard_vport_down[0x1];
301 uint8_t reserved_at_343[0x5];
302 uint8_t log_max_flow_counter_bulk[0x8];
303 uint8_t max_flow_counter_15_0[0x10];
304
305
306 uint8_t reserved_at_360[0x3];
307 uint8_t log_max_rq[0x5];
308 uint8_t reserved_at_368[0x3];
309 uint8_t log_max_sq[0x5];
310 uint8_t reserved_at_370[0x3];
311 uint8_t log_max_tir[0x5];
312 uint8_t reserved_at_378[0x3];
313 uint8_t log_max_tis[0x5];
314
315 uint8_t basic_cyclic_rcv_wqe[0x1];
316 uint8_t reserved_at_381[0x2];
317 uint8_t log_max_rmp[0x5];
318 uint8_t reserved_at_388[0x3];
319 uint8_t log_max_rqt[0x5];
320 uint8_t reserved_at_390[0x3];
321 uint8_t log_max_rqt_size[0x5];
322 uint8_t reserved_at_398[0x3];
323 uint8_t log_max_tis_per_sq[0x5];
324
325 uint8_t ext_stride_num_range[0x1];
326 uint8_t reserved_at_3a1[0x2];
327 uint8_t log_max_stride_sz_rq[0x5];
328 uint8_t reserved_at_3a8[0x3];
329 uint8_t log_min_stride_sz_rq[0x5];
330 uint8_t reserved_at_3b0[0x3];
331 uint8_t log_max_stride_sz_sq[0x5];
332 uint8_t reserved_at_3b8[0x3];
333 uint8_t log_min_stride_sz_sq[0x5];
334
335 uint8_t hairpin[0x1];
336 uint8_t reserved_at_3c1[0x2];
337 uint8_t log_max_hairpin_queues[0x5];
338 uint8_t reserved_at_3c8[0x3];
339 uint8_t log_max_hairpin_wq_data_sz[0x5];
340 uint8_t reserved_at_3d0[0x3];
341 uint8_t log_max_hairpin_num_packets[0x5];
342 uint8_t reserved_at_3d8[0x3];
343 uint8_t log_max_wq_sz[0x5];
344
345 uint8_t nic_vport_change_event[0x1];
346 uint8_t disable_local_lb_uc[0x1];
347 uint8_t disable_local_lb_mc[0x1];
348 uint8_t log_min_hairpin_wq_data_sz[0x5];
349 uint8_t reserved_at_3e8[0x3];
350 uint8_t log_max_vlan_list[0x5];
351 uint8_t reserved_at_3f0[0x3];
352 uint8_t log_max_current_mc_list[0x5];
353 uint8_t reserved_at_3f8[0x3];
354 uint8_t log_max_current_uc_list[0x5];
355
356 uint8_t general_obj_types[0x40];
357
358 uint8_t reserved_at_440[0x40];
359
360 uint8_t reserved_at_480[0x3];
361 uint8_t log_max_l2_table[0x5];
362 uint8_t reserved_at_488[0x8];
363 uint8_t log_uar_page_sz[0x10];
364
365 uint8_t reserved_at_4a0[0x20];
366 uint8_t device_frequency_mhz[0x20];
367 uint8_t device_frequency_khz[0x20];
368
369 uint8_t reserved_at_500[0x20];
370 uint8_t num_of_uars_per_page[0x20];
371 uint8_t reserved_at_540[0x40];
372
373 uint8_t reserved_at_580[0x3d];
374 uint8_t cqe_128_always[0x1];
375 uint8_t cqe_compression_128[0x1];
376 uint8_t cqe_compression[0x1];
377
378 uint8_t cqe_compression_timeout[0x10];
379 uint8_t cqe_compression_max_num[0x10];
380
381 uint8_t reserved_at_5e0[0x10];
382 uint8_t tag_matching[0x1];
383 uint8_t rndv_offload_rc[0x1];
384 uint8_t rndv_offload_dc[0x1];
385 uint8_t log_tag_matching_list_sz[0x5];
386 uint8_t reserved_at_5f8[0x3];
387 uint8_t log_max_xrq[0x5];
388
389 uint8_t affiliate_nic_vport_criteria[0x8];
390 uint8_t native_port_num[0x8];
391 uint8_t num_vhca_ports[0x8];
392 uint8_t reserved_at_618[0x6];
393 uint8_t sw_owner_id[0x1];
394 uint8_t reserved_at_61f[0x1e1];
395 };
396
397 enum {
398 UCT_IB_MLX5_ATOMIC_OPS_CMP_SWAP = UCS_BIT(0),
399 UCT_IB_MLX5_ATOMIC_OPS_FETCH_ADD = UCS_BIT(1),
400 UCT_IB_MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = UCS_BIT(2),
401 UCT_IB_MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = UCS_BIT(3)
402 };
403
404 struct uct_ib_mlx5_atomic_caps_bits {
405 uint8_t reserved_at_0[0x40];
406
407 uint8_t atomic_req_8B_endianness_mode[0x2];
408 uint8_t reserved_at_42[0x4];
409 uint8_t supported_atomic_req_8B_endianness_mode_1[0x1];
410
411 uint8_t reserved_at_47[0x19];
412
413 uint8_t reserved_at_60[0x20];
414
415 uint8_t reserved_at_80[0x10];
416 uint8_t atomic_operations[0x10];
417
418 uint8_t reserved_at_a0[0x10];
419 uint8_t atomic_size_qp[0x10];
420
421 uint8_t reserved_at_c0[0x10];
422 uint8_t atomic_size_dc[0x10];
423
424 uint8_t reserved_at_e0[0x1a0];
425
426 uint8_t fetch_add_pci_atomic[0x10];
427 uint8_t swap_pci_atomic[0x10];
428 uint8_t compare_swap_pci_atomic[0x10];
429 uint8_t reserved_at_2b0[0x10];
430
431 uint8_t reserved_at_2c0[0x540];
432 };
433
434 struct uct_ib_mlx5_odp_per_transport_service_cap_bits {
435 uint8_t send[0x1];
436 uint8_t receive[0x1];
437 uint8_t write[0x1];
438 uint8_t read[0x1];
439 uint8_t atomic[0x1];
440 uint8_t srq_receive[0x1];
441 uint8_t reserved_at_6[0x1a];
442 };
443
444 struct uct_ib_mlx5_odp_cap_bits {
445 uint8_t reserved_at_0[0x40];
446
447 uint8_t sig[0x1];
448 uint8_t reserved_at_41[0x1f];
449
450 uint8_t reserved_at_60[0x20];
451
452 struct uct_ib_mlx5_odp_per_transport_service_cap_bits rc_odp_caps;
453
454 struct uct_ib_mlx5_odp_per_transport_service_cap_bits uc_odp_caps;
455
456 struct uct_ib_mlx5_odp_per_transport_service_cap_bits ud_odp_caps;
457
458 struct uct_ib_mlx5_odp_per_transport_service_cap_bits xrc_odp_caps;
459
460 struct uct_ib_mlx5_odp_per_transport_service_cap_bits dc_odp_caps;
461
462 uint8_t reserved_at_100[0x700];
463 };
464
465 union uct_ib_mlx5_hca_cap_union_bits {
466 struct uct_ib_mlx5_cmd_hca_cap_bits cmd_hca_cap;
467 struct uct_ib_mlx5_odp_cap_bits odp_cap;
468 struct uct_ib_mlx5_atomic_caps_bits atomic_caps;
469 uint8_t reserved_at_0[0x8000];
470 };
471
472 struct uct_ib_mlx5_query_hca_cap_out_bits {
473 uint8_t status[0x8];
474 uint8_t reserved_at_8[0x18];
475
476 uint8_t syndrome[0x20];
477
478 uint8_t reserved_at_40[0x40];
479
480 union uct_ib_mlx5_hca_cap_union_bits capability;
481 };
482
483 struct uct_ib_mlx5_query_hca_cap_in_bits {
484 uint8_t opcode[0x10];
485 uint8_t uid[0x10];
486
487 uint8_t reserved_at_20[0x10];
488 uint8_t op_mod[0x10];
489
490 uint8_t reserved_at_40[0x40];
491 };
492
493 enum {
494 UCT_IB_MLX5_MKC_ACCESS_MODE_PA = 0x0,
495 UCT_IB_MLX5_MKC_ACCESS_MODE_MTT = 0x1,
496 UCT_IB_MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
497 UCT_IB_MLX5_MKC_ACCESS_MODE_KSM = 0x3,
498 UCT_IB_MLX5_MKC_ACCESS_MODE_MEMIC = 0x5
499 };
500
501 struct uct_ib_mlx5_mkc_bits {
502 uint8_t reserved_at_0[0x1];
503 uint8_t free[0x1];
504 uint8_t reserved_at_2[0x1];
505 uint8_t access_mode_4_2[0x3];
506 uint8_t reserved_at_6[0x7];
507 uint8_t relaxed_ordering_write[0x1];
508 uint8_t reserved_at_e[0x1];
509 uint8_t small_fence_on_rdma_read_response[0x1];
510 uint8_t umr_en[0x1];
511 uint8_t a[0x1];
512 uint8_t rw[0x1];
513 uint8_t rr[0x1];
514 uint8_t lw[0x1];
515 uint8_t lr[0x1];
516 uint8_t access_mode_1_0[0x2];
517 uint8_t reserved_at_18[0x8];
518
519 uint8_t qpn[0x18];
520 uint8_t mkey_7_0[0x8];
521
522 uint8_t reserved_at_40[0x20];
523
524 uint8_t length64[0x1];
525 uint8_t bsf_en[0x1];
526 uint8_t sync_umr[0x1];
527 uint8_t reserved_at_63[0x2];
528 uint8_t expected_sigerr_count[0x1];
529 uint8_t reserved_at_66[0x1];
530 uint8_t en_rinval[0x1];
531 uint8_t pd[0x18];
532
533 uint8_t start_addr[0x40];
534
535 uint8_t len[0x40];
536
537 uint8_t bsf_octword_size[0x20];
538
539 uint8_t reserved_at_120[0x80];
540
541 uint8_t translations_octword_size[0x20];
542
543 uint8_t reserved_at_1c0[0x1b];
544 uint8_t log_entity_size[0x5];
545
546 uint8_t reserved_at_1e0[0x20];
547 };
548
549 struct uct_ib_mlx5_create_mkey_in_bits {
550 uint8_t opcode[0x10];
551 uint8_t uid[0x10];
552
553 uint8_t reserved_at_20[0x10];
554 uint8_t op_mod[0x10];
555
556 uint8_t reserved_at_40[0x20];
557
558 uint8_t pg_access[0x1];
559 uint8_t mkey_umem_valid[0x1];
560 uint8_t cmd_on_behalf[0x1];
561 uint8_t reserved_at_63[0xd];
562 uint8_t function_id[0x10];
563
564 struct uct_ib_mlx5_mkc_bits memory_key_mkey_entry;
565
566 uint8_t reserved_at_280[0x80];
567
568 uint8_t translations_octword_actual_size[0x20];
569
570 uint8_t mkey_umem_id[0x20];
571
572 uint8_t mkey_umem_offset[0x40];
573
574 uint8_t reserved_at_380[0x500];
575
576 uint8_t klm_pas_mtt[0][0x20];
577 };
578
579 struct uct_ib_mlx5_klm_bits {
580 uint8_t byte_count[0x20];
581
582 uint8_t mkey[0x20];
583
584 uint8_t address[0x40];
585 };
586
587 struct uct_ib_mlx5_create_mkey_out_bits {
588 uint8_t status[0x8];
589 uint8_t reserved_at_8[0x18];
590
591 uint8_t syndrome[0x20];
592
593 uint8_t reserved_at_40[0x8];
594 uint8_t mkey_index[0x18];
595
596 uint8_t reserved_at_60[0x20];
597 };
598
599 struct uct_ib_mlx5_set_xrq_dc_params_entry_out_bits {
600 uint8_t status[0x8];
601 uint8_t reserved_at_8[0x18];
602
603 uint8_t syndrome[0x20];
604
605 uint8_t reserved_at_40[0x40];
606 };
607
608 struct uct_ib_mlx5_set_xrq_dc_params_entry_in_bits {
609 uint8_t opcode[0x10];
610 uint8_t reserved_at_10[0x10];
611
612 uint8_t reserved_at_20[0x10];
613 uint8_t op_mod[0x10];
614
615 uint8_t reserved_at_40[0x8];
616 uint8_t xrqn[0x18];
617
618 uint8_t reserved_at_60[0x20];
619
620 uint8_t reserved_at_80[0x3];
621 uint8_t ack_timeout[0x5];
622 uint8_t reserved_at_88[0x4];
623 uint8_t multi_path[0x1];
624 uint8_t mtu[0x3];
625 uint8_t pkey_table_index[0x10];
626
627 uint8_t reserved_at_a0[0xc];
628 uint8_t cnak_reverse_sl[0x4];
629 uint8_t reserved_at_b0[0x4];
630 uint8_t reverse_sl[0x4];
631 uint8_t reserved_at_b8[0x4];
632 uint8_t sl[0x4];
633
634 uint8_t dc_access_key[0x40];
635
636 uint8_t reserved_at_100[0x80];
637 };
638
639 enum {
640 UCT_IB_MLX5_DCTC_STATE_ACTIVE = 0x0,
641 UCT_IB_MLX5_DCTC_STATE_DRAINING = 0x1,
642 UCT_IB_MLX5_DCTC_STATE_DRAINED = 0x2
643 };
644
645 enum {
646 UCT_IB_MLX5_DCTC_CS_RES_DISABLE = 0x0,
647 UCT_IB_MLX5_DCTC_CS_RES_NA = 0x1,
648 UCT_IB_MLX5_DCTC_CS_RES_UP_TO_64B = 0x2
649 };
650
651 enum {
652 UCT_IB_MLX5_DCTC_MTU_256_BYTES = 0x1,
653 UCT_IB_MLX5_DCTC_MTU_512_BYTES = 0x2,
654 UCT_IB_MLX5_DCTC_MTU_1K_BYTES = 0x3,
655 UCT_IB_MLX5_DCTC_MTU_2K_BYTES = 0x4,
656 UCT_IB_MLX5_DCTC_MTU_4K_BYTES = 0x5
657 };
658
659 struct uct_ib_mlx5_dctc_bits {
660 uint8_t reserved_at_0[0x4];
661 uint8_t state[0x4];
662 uint8_t reserved_at_8[0x10];
663 uint8_t offload_type[0x4];
664 uint8_t reserved_at_1c[0x4];
665
666 uint8_t reserved_at_20[0x8];
667 uint8_t user_index[0x18];
668
669 uint8_t reserved_at_40[0x8];
670 uint8_t cqn[0x18];
671
672 uint8_t counter_set_id[0x8];
673 uint8_t atomic_mode[0x4];
674 uint8_t rre[0x1];
675 uint8_t rwe[0x1];
676 uint8_t rae[0x1];
677 uint8_t atomic_like_write_en[0x1];
678 uint8_t latency_sensitive[0x1];
679 uint8_t rlky[0x1];
680 uint8_t free_ar[0x1];
681 uint8_t reserved_at_73[0xd];
682
683 uint8_t reserved_at_80[0x8];
684 uint8_t cs_res[0x8];
685 uint8_t reserved_at_90[0x3];
686 uint8_t min_rnr_nak[0x5];
687 uint8_t reserved_at_98[0x8];
688
689 uint8_t reserved_at_a0[0x8];
690 uint8_t srqn_xrqn[0x18];
691
692 uint8_t reserved_at_c0[0x8];
693 uint8_t pd[0x18];
694
695 uint8_t tclass[0x8];
696 uint8_t reserved_at_e8[0x4];
697 uint8_t flow_label[0x14];
698
699 uint8_t dc_access_key[0x40];
700
701 uint8_t reserved_at_140[0x5];
702 uint8_t mtu[0x3];
703 uint8_t port[0x8];
704 uint8_t pkey_index[0x10];
705
706 uint8_t reserved_at_160[0x8];
707 uint8_t my_addr_index[0x8];
708 uint8_t reserved_at_170[0x8];
709 uint8_t hop_limit[0x8];
710
711 uint8_t dc_access_key_violation_count[0x20];
712
713 uint8_t reserved_at_1a0[0x14];
714 uint8_t dei_cfi[0x1];
715 uint8_t eth_prio[0x3];
716 uint8_t ecn[0x2];
717 uint8_t dscp[0x6];
718
719 uint8_t reserved_at_1c0[0x40];
720 };
721
722 struct uct_ib_mlx5_create_dct_out_bits {
723 uint8_t status[0x8];
724 uint8_t reserved_at_8[0x18];
725
726 uint8_t syndrome[0x20];
727
728 uint8_t reserved_at_40[0x8];
729 uint8_t dctn[0x18];
730
731 uint8_t reserved_at_60[0x20];
732 };
733
734 struct uct_ib_mlx5_create_dct_in_bits {
735 uint8_t opcode[0x10];
736 uint8_t uid[0x10];
737
738 uint8_t reserved_at_20[0x10];
739 uint8_t op_mod[0x10];
740
741 uint8_t reserved_at_40[0x40];
742
743 struct uct_ib_mlx5_dctc_bits dct_context_entry;
744
745 uint8_t reserved_at_280[0x180];
746 };
747
748 struct uct_ib_mlx5_drain_dct_out_bits {
749 uint8_t status[0x8];
750 uint8_t reserved_at_8[0x18];
751
752 uint8_t syndrome[0x20];
753
754 uint8_t reserved_at_40[0x40];
755 };
756
757 struct uct_ib_mlx5_drain_dct_in_bits {
758 uint8_t opcode[0x10];
759 uint8_t uid[0x10];
760
761 uint8_t reserved_at_20[0x10];
762 uint8_t op_mod[0x10];
763
764 uint8_t reserved_at_40[0x8];
765 uint8_t dctn[0x18];
766
767 uint8_t reserved_at_60[0x20];
768 };
769
770 struct uct_ib_mlx5_cmd_pas_bits {
771 uint8_t pa_h[0x20];
772
773 uint8_t pa_l[0x14];
774 uint8_t reserved_at_34[0xc];
775 };
776
777 enum {
778 UCT_IB_MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
779 UCT_IB_MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1
780 };
781
782 enum {
783 UCT_IB_MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
784 UCT_IB_MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1
785 };
786
787 struct uct_ib_mlx5_wq_bits {
788 uint8_t wq_type[0x4];
789 uint8_t wq_signature[0x1];
790 uint8_t end_padding_mode[0x2];
791 uint8_t cd_slave[0x1];
792 uint8_t reserved_at_8[0x18];
793
794 uint8_t hds_skip_first_sge[0x1];
795 uint8_t log2_hds_buf_size[0x3];
796 uint8_t reserved_at_24[0x7];
797 uint8_t page_offset[0x5];
798 uint8_t lwm[0x10];
799
800 uint8_t reserved_at_40[0x8];
801 uint8_t pd[0x18];
802
803 uint8_t reserved_at_60[0x8];
804 uint8_t uar_page[0x18];
805
806 uint8_t dbr_addr[0x40];
807
808 uint8_t hw_counter[0x20];
809
810 uint8_t sw_counter[0x20];
811
812 uint8_t reserved_at_100[0xc];
813 uint8_t log_wq_stride[0x4];
814 uint8_t reserved_at_110[0x3];
815 uint8_t log_wq_pg_sz[0x5];
816 uint8_t reserved_at_118[0x3];
817 uint8_t log_wq_sz[0x5];
818
819 uint8_t dbr_umem_valid[0x1];
820 uint8_t wq_umem_valid[0x1];
821 uint8_t reserved_at_122[0x1];
822 uint8_t log_hairpin_num_packets[0x5];
823 uint8_t reserved_at_128[0x3];
824 uint8_t log_hairpin_data_sz[0x5];
825 uint8_t reserved_at_130[0x4];
826 uint8_t log_wqe_num_of_strides[0x4];
827 uint8_t two_byte_shift_en[0x1];
828 uint8_t reserved_at_139[0x4];
829 uint8_t log_wqe_stride_size[0x3];
830
831 uint8_t dbr_umem_id[0x20];
832
833 uint8_t wq_umem_id[0x20];
834
835 uint8_t reserved_at_180[0x480];
836
837 struct uct_ib_mlx5_cmd_pas_bits pas[0];
838 };
839
840 enum {
841 UCT_IB_MLX5_XRQC_STATE_GOOD = 0x0,
842 UCT_IB_MLX5_XRQC_STATE_ERROR = 0x1
843 };
844
845 enum {
846 UCT_IB_MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
847 UCT_IB_MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1
848 };
849
850 enum {
851 UCT_IB_MLX5_XRQC_OFFLOAD_RNDV = 0x1
852 };
853
854 struct uct_ib_mlx5_tag_matching_topology_context_bits {
855 uint8_t log_matching_list_sz[0x4];
856 uint8_t reserved_at_4[0xc];
857 uint8_t append_next_index[0x10];
858
859 uint8_t sw_phase_cnt[0x10];
860 uint8_t hw_phase_cnt[0x10];
861
862 uint8_t reserved_at_40[0x40];
863 };
864
865 struct uct_ib_mlx5_xrqc_bits {
866 uint8_t state[0x4];
867 uint8_t rlkey[0x1];
868 uint8_t reserved_at_5[0xf];
869 uint8_t topology[0x4];
870 uint8_t reserved_at_18[0x4];
871 uint8_t offload[0x4];
872
873 uint8_t reserved_at_20[0x8];
874 uint8_t user_index[0x18];
875
876 uint8_t reserved_at_40[0x8];
877 uint8_t cqn[0x18];
878
879 uint8_t reserved_at_60[0x1f];
880 uint8_t dc[0x1];
881
882 uint8_t reserved_at_80[0x80];
883
884 struct uct_ib_mlx5_tag_matching_topology_context_bits tag_matching_topology_context;
885
886 uint8_t reserved_at_180[0x280];
887
888 struct uct_ib_mlx5_wq_bits wq;
889 };
890
891 struct uct_ib_mlx5_create_xrq_out_bits {
892 uint8_t status[0x8];
893 uint8_t reserved_at_8[0x18];
894
895 uint8_t syndrome[0x20];
896
897 uint8_t reserved_at_40[0x8];
898 uint8_t xrqn[0x18];
899
900 uint8_t reserved_at_60[0x20];
901 };
902
903 struct uct_ib_mlx5_create_xrq_in_bits {
904 uint8_t opcode[0x10];
905 uint8_t uid[0x10];
906
907 uint8_t reserved_at_20[0x10];
908 uint8_t op_mod[0x10];
909
910 uint8_t reserved_at_40[0x40];
911
912 struct uct_ib_mlx5_xrqc_bits xrq_context;
913 };
914
915 enum {
916 UCT_IB_MLX5_RMPC_STATE_RDY = 0x1,
917 UCT_IB_MLX5_RMPC_STATE_ERR = 0x3
918 };
919
920 struct uct_ib_mlx5_rmpc_bits {
921 uint8_t reserved_at_0[0x8];
922 uint8_t state[0x4];
923 uint8_t reserved_at_c[0x14];
924
925 uint8_t basic_cyclic_rcv_wqe[0x1];
926 uint8_t reserved_at_21[0x1f];
927
928 uint8_t reserved_at_40[0x140];
929
930 struct uct_ib_mlx5_wq_bits wq;
931 };
932
933 struct uct_ib_mlx5_create_rmp_out_bits {
934 uint8_t status[0x8];
935 uint8_t reserved_at_8[0x18];
936
937 uint8_t syndrome[0x20];
938
939 uint8_t reserved_at_40[0x8];
940 uint8_t rmpn[0x18];
941
942 uint8_t reserved_at_60[0x20];
943 };
944
945 struct uct_ib_mlx5_create_rmp_in_bits {
946 uint8_t opcode[0x10];
947 uint8_t uid[0x10];
948
949 uint8_t reserved_at_20[0x10];
950 uint8_t op_mod[0x10];
951
952 uint8_t reserved_at_40[0xc0];
953
954 struct uct_ib_mlx5_rmpc_bits rmp_context;
955 };
956
957 enum {
958 UCT_IB_MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
959 UCT_IB_MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
960 UCT_IB_MLX5_ADS_STAT_RATE_10GBPS = 0x8,
961 UCT_IB_MLX5_ADS_STAT_RATE_30GBPS = 0x9,
962 UCT_IB_MLX5_ADS_STAT_RATE_5GBPS = 0xa,
963 UCT_IB_MLX5_ADS_STAT_RATE_20GBPS = 0xb,
964 UCT_IB_MLX5_ADS_STAT_RATE_40GBPS = 0xc,
965 UCT_IB_MLX5_ADS_STAT_RATE_60GBPS = 0xd,
966 UCT_IB_MLX5_ADS_STAT_RATE_80GBPS = 0xe,
967 UCT_IB_MLX5_ADS_STAT_RATE_120GBPS = 0xf
968 };
969
970 struct uct_ib_mlx5_ads_bits {
971 uint8_t fl[0x1];
972 uint8_t free_ar[0x1];
973 uint8_t reserved_at_2[0xe];
974 uint8_t pkey_index[0x10];
975
976 uint8_t reserved_at_20[0x8];
977 uint8_t grh[0x1];
978 uint8_t mlid[0x7];
979 uint8_t rlid[0x10];
980
981 uint8_t ack_timeout[0x5];
982 uint8_t reserved_at_45[0x3];
983 uint8_t src_addr_index[0x8];
984 uint8_t log_rtm[0x4];
985 uint8_t stat_rate[0x4];
986 uint8_t hop_limit[0x8];
987
988 uint8_t reserved_at_60[0x4];
989 uint8_t tclass[0x8];
990 uint8_t flow_label[0x14];
991
992 uint8_t rgid_rip[16][0x8];
993
994 uint8_t reserved_at_100[0x4];
995 uint8_t f_dscp[0x1];
996 uint8_t f_ecn[0x1];
997 uint8_t reserved_at_106[0x1];
998 uint8_t f_eth_prio[0x1];
999 uint8_t ecn[0x2];
1000 uint8_t dscp[0x6];
1001 uint8_t udp_sport[0x10];
1002
1003 uint8_t dei_cfi[0x1];
1004 uint8_t eth_prio[0x3];
1005 uint8_t sl[0x4];
1006 uint8_t vhca_port_num[0x8];
1007 uint8_t rmac_47_32[0x10];
1008
1009 uint8_t rmac_31_0[0x20];
1010 };
1011
1012 enum {
1013 UCT_IB_MLX5_QPC_STATE_RST = 0x0,
1014 UCT_IB_MLX5_QPC_STATE_INIT = 0x1,
1015 UCT_IB_MLX5_QPC_STATE_RTR = 0x2,
1016 UCT_IB_MLX5_QPC_STATE_RTS = 0x3,
1017 UCT_IB_MLX5_QPC_STATE_SQER = 0x4,
1018 UCT_IB_MLX5_QPC_STATE_ERR = 0x6,
1019 UCT_IB_MLX5_QPC_STATE_SQD = 0x7,
1020 UCT_IB_MLX5_QPC_STATE_SUSPENDED = 0x9
1021 };
1022
1023 enum {
1024 UCT_IB_MLX5_QPC_ST_RC = 0x0,
1025 UCT_IB_MLX5_QPC_ST_UC = 0x1,
1026 UCT_IB_MLX5_QPC_ST_UD = 0x2,
1027 UCT_IB_MLX5_QPC_ST_XRC = 0x3,
1028 UCT_IB_MLX5_QPC_ST_DCI = 0x5,
1029 UCT_IB_MLX5_QPC_ST_QP0 = 0x7,
1030 UCT_IB_MLX5_QPC_ST_QP1 = 0x8,
1031 UCT_IB_MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1032 UCT_IB_MLX5_QPC_ST_REG_UMR = 0xc
1033 };
1034
1035 enum {
1036 UCT_IB_MLX5_QPC_PM_STATE_ARMED = 0x0,
1037 UCT_IB_MLX5_QPC_PM_STATE_REARM = 0x1,
1038 UCT_IB_MLX5_QPC_PM_STATE_RESERVED = 0x2,
1039 UCT_IB_MLX5_QPC_PM_STATE_MIGRATED = 0x3
1040 };
1041
1042 enum {
1043 UCT_IB_MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1
1044 };
1045
1046 enum {
1047 UCT_IB_MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1048 UCT_IB_MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1
1049 };
1050
1051 enum {
1052 UCT_IB_MLX5_QPC_MTU_256_BYTES = 0x1,
1053 UCT_IB_MLX5_QPC_MTU_512_BYTES = 0x2,
1054 UCT_IB_MLX5_QPC_MTU_1K_BYTES = 0x3,
1055 UCT_IB_MLX5_QPC_MTU_2K_BYTES = 0x4,
1056 UCT_IB_MLX5_QPC_MTU_4K_BYTES = 0x5,
1057 UCT_IB_MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7
1058 };
1059
1060 enum {
1061 UCT_IB_MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1062 UCT_IB_MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1063 UCT_IB_MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1064 UCT_IB_MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1065 UCT_IB_MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1066 UCT_IB_MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1067 UCT_IB_MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1068 UCT_IB_MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8
1069 };
1070
1071 enum {
1072 UCT_IB_MLX5_QPC_CS_REQ_DISABLE = 0x0,
1073 UCT_IB_MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1074 UCT_IB_MLX5_QPC_CS_REQ_UP_TO_64B = 0x22
1075 };
1076
uct_ib_mlx5_qpc_cs_req(unsigned size)1077 static inline unsigned uct_ib_mlx5_qpc_cs_req(unsigned size)
1078 {
1079 return (size > 32) ? UCT_IB_MLX5_QPC_CS_REQ_UP_TO_64B :
1080 size ? UCT_IB_MLX5_QPC_CS_REQ_UP_TO_32B :
1081 UCT_IB_MLX5_QPC_CS_REQ_DISABLE;
1082 }
1083
1084 enum {
1085 UCT_IB_MLX5_QPC_CS_RES_DISABLE = 0x0,
1086 UCT_IB_MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1087 UCT_IB_MLX5_QPC_CS_RES_UP_TO_64B = 0x2
1088 };
1089
uct_ib_mlx5_qpc_cs_res(unsigned size,int dc)1090 static inline unsigned uct_ib_mlx5_qpc_cs_res(unsigned size, int dc)
1091 {
1092 return (size > 32) ? UCT_IB_MLX5_QPC_CS_RES_UP_TO_64B :
1093 (size && !dc) ? UCT_IB_MLX5_QPC_CS_RES_UP_TO_32B :
1094 UCT_IB_MLX5_QPC_CS_RES_DISABLE;
1095 }
1096
1097 struct uct_ib_mlx5_qpc_bits {
1098 uint8_t state[0x4];
1099 uint8_t lag_tx_port_affinity[0x4];
1100 uint8_t st[0x8];
1101 uint8_t reserved_at_10[0x3];
1102 uint8_t pm_state[0x2];
1103 uint8_t reserved_at_15[0x1];
1104 uint8_t req_e2e_credit_mode[0x2];
1105 uint8_t offload_type[0x4];
1106 uint8_t end_padding_mode[0x2];
1107 uint8_t reserved_at_1e[0x2];
1108
1109 uint8_t wq_signature[0x1];
1110 uint8_t block_lb_mc[0x1];
1111 uint8_t atomic_like_write_en[0x1];
1112 uint8_t latency_sensitive[0x1];
1113 uint8_t reserved_at_24[0x1];
1114 uint8_t drain_sigerr[0x1];
1115 uint8_t reserved_at_26[0x2];
1116 uint8_t pd[0x18];
1117
1118 uint8_t mtu[0x3];
1119 uint8_t log_msg_max[0x5];
1120 uint8_t reserved_at_48[0x1];
1121 uint8_t log_rq_size[0x4];
1122 uint8_t log_rq_stride[0x3];
1123 uint8_t no_sq[0x1];
1124 uint8_t log_sq_size[0x4];
1125 uint8_t reserved_at_55[0x6];
1126 uint8_t rlky[0x1];
1127 uint8_t ulp_stateless_offload_mode[0x4];
1128
1129 uint8_t counter_set_id[0x8];
1130 uint8_t uar_page[0x18];
1131
1132 uint8_t reserved_at_80[0x8];
1133 uint8_t user_index[0x18];
1134
1135 uint8_t reserved_at_a0[0x3];
1136 uint8_t log_page_size[0x5];
1137 uint8_t remote_qpn[0x18];
1138
1139 struct uct_ib_mlx5_ads_bits primary_address_path;
1140
1141 struct uct_ib_mlx5_ads_bits secondary_address_path;
1142
1143 uint8_t log_ack_req_freq[0x4];
1144 uint8_t reserved_at_384[0x4];
1145 uint8_t log_sra_max[0x3];
1146 uint8_t reserved_at_38b[0x2];
1147 uint8_t retry_count[0x3];
1148 uint8_t rnr_retry[0x3];
1149 uint8_t reserved_at_393[0x1];
1150 uint8_t fre[0x1];
1151 uint8_t cur_rnr_retry[0x3];
1152 uint8_t cur_retry_count[0x3];
1153 uint8_t reserved_at_39b[0x5];
1154
1155 uint8_t reserved_at_3a0[0x20];
1156
1157 uint8_t reserved_at_3c0[0x8];
1158 uint8_t next_send_psn[0x18];
1159
1160 uint8_t reserved_at_3e0[0x8];
1161 uint8_t cqn_snd[0x18];
1162
1163 uint8_t reserved_at_400[0x8];
1164 uint8_t deth_sqpn[0x18];
1165
1166 uint8_t reserved_at_420[0x20];
1167
1168 uint8_t reserved_at_440[0x8];
1169 uint8_t last_acked_psn[0x18];
1170
1171 uint8_t reserved_at_460[0x8];
1172 uint8_t ssn[0x18];
1173
1174 uint8_t reserved_at_480[0x8];
1175 uint8_t log_rra_max[0x3];
1176 uint8_t reserved_at_48b[0x1];
1177 uint8_t atomic_mode[0x4];
1178 uint8_t rre[0x1];
1179 uint8_t rwe[0x1];
1180 uint8_t rae[0x1];
1181 uint8_t reserved_at_493[0x1];
1182 uint8_t page_offset[0x6];
1183 uint8_t reserved_at_49a[0x3];
1184 uint8_t cd_slave_receive[0x1];
1185 uint8_t cd_slave_send[0x1];
1186 uint8_t cd_master[0x1];
1187
1188 uint8_t reserved_at_4a0[0x3];
1189 uint8_t min_rnr_nak[0x5];
1190 uint8_t next_rcv_psn[0x18];
1191
1192 uint8_t reserved_at_4c0[0x8];
1193 uint8_t xrcd[0x18];
1194
1195 uint8_t reserved_at_4e0[0x8];
1196 uint8_t cqn_rcv[0x18];
1197
1198 uint8_t dbr_addr[0x40];
1199
1200 uint8_t q_key[0x20];
1201
1202 uint8_t reserved_at_560[0x5];
1203 uint8_t rq_type[0x3];
1204 uint8_t srqn_rmpn_xrqn[0x18];
1205
1206 uint8_t reserved_at_580[0x8];
1207 uint8_t rmsn[0x18];
1208
1209 uint8_t hw_sq_wqebb_counter[0x10];
1210 uint8_t sw_sq_wqebb_counter[0x10];
1211
1212 uint8_t hw_rq_counter[0x20];
1213
1214 uint8_t sw_rq_counter[0x20];
1215
1216 uint8_t reserved_at_600[0x20];
1217
1218 uint8_t reserved_at_620[0xf];
1219 uint8_t cgs[0x1];
1220 uint8_t cs_req[0x8];
1221 uint8_t cs_res[0x8];
1222
1223 uint8_t dc_access_key[0x40];
1224
1225 uint8_t reserved_at_680[0x3];
1226 uint8_t dbr_umem_valid[0x1];
1227 uint8_t reserved_at_684[0x1c];
1228
1229 uint8_t reserved_at_6a0[0x80];
1230
1231 uint8_t dbr_umem_id[0x20];
1232 };
1233
1234 struct uct_ib_mlx5_create_qp_out_bits {
1235 uint8_t status[0x8];
1236 uint8_t reserved_at_8[0x18];
1237
1238 uint8_t syndrome[0x20];
1239
1240 uint8_t reserved_at_40[0x8];
1241 uint8_t qpn[0x18];
1242
1243 uint8_t reserved_at_60[0x20];
1244 };
1245
1246 struct uct_ib_mlx5_create_qp_in_bits {
1247 uint8_t opcode[0x10];
1248 uint8_t uid[0x10];
1249
1250 uint8_t reserved_at_20[0x10];
1251 uint8_t op_mod[0x10];
1252
1253 uint8_t reserved_at_40[0x40];
1254
1255 uint8_t opt_param_mask[0x20];
1256
1257 uint8_t reserved_at_a0[0x20];
1258
1259 struct uct_ib_mlx5_qpc_bits qpc;
1260
1261 uint8_t reserved_at_800[0x40];
1262
1263 uint8_t wq_umem_id[0x20];
1264
1265 uint8_t wq_umem_valid[0x1];
1266 uint8_t reserved_at_861[0x1f];
1267
1268 uint8_t pas[0][0x40];
1269 };
1270
1271 struct uct_ib_mlx5_init2rtr_qp_out_bits {
1272 uint8_t status[0x8];
1273 uint8_t reserved_at_8[0x18];
1274
1275 uint8_t syndrome[0x20];
1276
1277 uint8_t reserved_at_40[0x40];
1278 };
1279
1280 struct uct_ib_mlx5_init2rtr_qp_in_bits {
1281 uint8_t opcode[0x10];
1282 uint8_t uid[0x10];
1283
1284 uint8_t reserved_at_20[0x10];
1285 uint8_t op_mod[0x10];
1286
1287 uint8_t reserved_at_40[0x8];
1288 uint8_t qpn[0x18];
1289
1290 uint8_t reserved_at_60[0x20];
1291
1292 uint8_t opt_param_mask[0x20];
1293
1294 uint8_t reserved_at_a0[0x20];
1295
1296 struct uct_ib_mlx5_qpc_bits qpc;
1297
1298 uint8_t reserved_at_800[0x80];
1299 };
1300
1301 struct uct_ib_mlx5_rtr2rts_qp_out_bits {
1302 uint8_t status[0x8];
1303 uint8_t reserved_at_8[0x18];
1304
1305 uint8_t syndrome[0x20];
1306
1307 uint8_t reserved_at_40[0x40];
1308 };
1309
1310 struct uct_ib_mlx5_rtr2rts_qp_in_bits {
1311 uint8_t opcode[0x10];
1312 uint8_t uid[0x10];
1313
1314 uint8_t reserved_at_20[0x10];
1315 uint8_t op_mod[0x10];
1316
1317 uint8_t reserved_at_40[0x8];
1318 uint8_t qpn[0x18];
1319
1320 uint8_t reserved_at_60[0x20];
1321
1322 uint8_t opt_param_mask[0x20];
1323
1324 uint8_t reserved_at_a0[0x20];
1325
1326 struct uct_ib_mlx5_qpc_bits qpc;
1327
1328 uint8_t reserved_at_800[0x80];
1329 };
1330
1331 struct uct_ib_mlx5_rst2init_qp_out_bits {
1332 uint8_t status[0x8];
1333 uint8_t reserved_at_8[0x18];
1334
1335 uint8_t syndrome[0x20];
1336
1337 uint8_t reserved_at_40[0x40];
1338 };
1339
1340 struct uct_ib_mlx5_rst2init_qp_in_bits {
1341 uint8_t opcode[0x10];
1342 uint8_t uid[0x10];
1343
1344 uint8_t reserved_at_20[0x10];
1345 uint8_t op_mod[0x10];
1346
1347 uint8_t reserved_at_40[0x8];
1348 uint8_t qpn[0x18];
1349
1350 uint8_t reserved_at_60[0x20];
1351
1352 uint8_t opt_param_mask[0x20];
1353
1354 uint8_t reserved_at_a0[0x20];
1355
1356 struct uct_ib_mlx5_qpc_bits qpc;
1357
1358 uint8_t reserved_at_800[0x80];
1359 };
1360
1361 struct uct_ib_mlx5_modify_qp_out_bits {
1362 uint8_t status[0x8];
1363 uint8_t reserved_at_8[0x18];
1364
1365 uint8_t syndrome[0x20];
1366
1367 uint8_t reserved_at_40[0x40];
1368 };
1369
1370 struct uct_ib_mlx5_modify_qp_in_bits {
1371 uint8_t opcode[0x10];
1372 uint8_t uid[0x10];
1373
1374 uint8_t reserved_at_20[0x10];
1375 uint8_t op_mod[0x10];
1376
1377 uint8_t reserved_at_40[0x8];
1378 uint8_t qpn[0x18];
1379
1380 uint8_t reserved_at_60[0x20];
1381 };
1382
1383 enum {
1384 UCT_IB_MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13
1385 };
1386
1387 #endif
1388