1 /* pdp11_uqssp.h: Unibus/Qbus storage systems port definitions file 2 3 Copyright (c) 2001-2008, Robert M Supnik 4 Derived from work by Stephen F. Shirron 5 6 Permission is hereby granted, free of charge, to any person obtaining a 7 copy of this software and associated documentation files (the "Software"), 8 to deal in the Software without restriction, including without limitation 9 the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 and/or sell copies of the Software, and to permit persons to whom the 11 Software is furnished to do so, subject to the following conditions: 12 13 The above copyright notice and this permission notice shall be included in 14 all copies or substantial portions of the Software. 15 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 20 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 23 Except as contained in this notice, the name of Robert M Supnik shall not be 24 used in advertising or otherwise to promote the sale, use or other dealings 25 in this Software without prior written authorization from Robert M Supnik. 26 27 30-Aug-02 RMS Added TMSCP support 28 */ 29 30 #ifndef _PDP11_UQSSP_H_ 31 #define _PDP11_UQSSP_H_ 0 32 33 /* IP register - initialization and polling 34 35 read - controller polls command queue 36 write - controller re-initializes 37 */ 38 39 /* SA register - status, address, and purge 40 41 read - data and error information 42 write - host startup information, purge complete 43 */ 44 45 #define SA_ER 0x8000 /* error */ 46 #define SA_S4 0x4000 /* init step 4 */ 47 #define SA_S3 0x2000 /* init step 3 */ 48 #define SA_S2 0x1000 /* init step 2 */ 49 #define SA_S1 0x0800 /* init step 1 */ 50 51 /* Init step 1, controller to host */ 52 53 #define SA_S1C_NV 0x0400 /* fixed vec NI */ 54 #define SA_S1C_Q22 0x0200 /* Q22 device */ 55 #define SA_S1C_DI 0x0100 /* ext diags */ 56 #define SA_S1C_OD 0x0080 /* odd addrs NI */ 57 #define SA_S1C_MP 0x0040 /* mapping */ 58 #define SA_S1C_SM 0x0020 /* spec fncs NI */ 59 #define SA_S1C_CN 0x0010 /* node name NI */ 60 61 /* Init step 1, host to controller */ 62 63 #define SA_S1H_VL 0x8000 /* valid */ 64 #define SA_S1H_WR 0x4000 /* wrap mode */ 65 #define SA_S1H_V_CQ 11 /* cmd q len */ 66 #define SA_S1H_M_CQ 0x7 67 #define SA_S1H_V_RQ 8 /* resp q len */ 68 #define SA_S1H_M_RQ 0x7 69 #define SA_S1H_IE 0x0080 /* int enb */ 70 #define SA_S1H_VEC 0x007F /* vector */ 71 #define SA_S1H_CQ(x) (1 << (((x) >> SA_S1H_V_CQ) & SA_S1H_M_CQ)) 72 #define SA_S1H_RQ(x) (1 << (((x) >> SA_S1H_V_RQ) & SA_S1H_M_RQ)) 73 74 /* Init step 2, controller to host */ 75 76 #define SA_S2C_PT 0x0000 /* port type */ 77 #define SA_S2C_V_EC 8 /* info to echo */ 78 #define SA_S2C_M_EC 0xFF 79 #define SA_S2C_EC(x) (((x) >> SA_S2C_V_EC) & SA_S2C_M_EC) 80 81 /* Init step 2, host to controller */ 82 83 #define SA_S2H_CLO 0xFFFE /* comm addr lo */ 84 #define SA_S2H_PI 0x0001 /* adp prg int */ 85 86 /* Init step 3, controller to host */ 87 88 #define SA_S3C_V_EC 0 /* info to echo */ 89 #define SA_S3C_M_EC 0xFF 90 #define SA_S3C_EC(x) (((x) >> SA_S3C_V_EC) & SA_S3C_M_EC) 91 92 /* Init step 3, host to controller */ 93 94 #define SA_S3H_PP 0x8000 /* purge, poll test */ 95 #define SA_S3H_CHI 0x7FFF /* comm addr hi */ 96 97 /* Init step 4, controller to host */ 98 99 #define SA_S4C_V_MOD 4 /* adapter # */ 100 #define SA_S4C_V_VER 0 /* version # */ 101 102 /* Init step 4, host to controller */ 103 104 #define SA_S4H_CS 0x0400 /* host scrpad NI */ 105 #define SA_S4H_NN 0x0200 /* snd node name NI */ 106 #define SA_S4H_SF 0x0100 /* spec fnc NI */ 107 #define SA_S4H_LF 0x0002 /* send last fail */ 108 #define SA_S4H_GO 0x0001 /* go */ 109 110 /* Fatal error codes (generic through 32) */ 111 112 #define PE_PRE 1 /* packet read err */ 113 #define PE_PWE 2 /* packet write err */ 114 #define PE_QRE 6 /* queue read err */ 115 #define PE_QWE 7 /* queue write err */ 116 #define PE_HAT 9 /* host access tmo */ 117 #define PE_ICI 14 /* inv conn ident */ 118 #define PE_PIE 20 /* prot incompat */ 119 #define PE_PPF 21 /* prg/poll err */ 120 #define PE_MRE 22 /* map reg rd err */ 121 #define PE_T11 475 /* T11 err NI */ 122 #define PE_SND 476 /* SND err NI */ 123 #define PE_RCV 477 /* RCV err NI */ 124 #define PE_NSR 478 /* no such rsrc */ 125 126 /* Comm region offsets */ 127 128 #define SA_COMM_QQ -8 /* unused */ 129 #define SA_COMM_PI -6 /* purge int */ 130 #define SA_COMM_CI -4 /* cmd int */ 131 #define SA_COMM_RI -2 /* resp int */ 132 #define SA_COMM_MAX ((4 << SA_S1H_M_CQ) + (4 << SA_S1H_M_RQ) - SA_COMM_QQ) 133 134 /* Command/response rings */ 135 136 struct uq_ring { 137 int32 ioff; /* intr offset */ 138 uint32 ba; /* base addr */ 139 uint32 lnt; /* size in bytes */ 140 uint32 idx; /* current index */ 141 }; 142 143 /* Ring descriptor entry */ 144 145 #define UQ_DESC_OWN 0x80000000 /* ownership */ 146 #define UQ_DESC_F 0x40000000 /* flag */ 147 #define UQ_ADDR 0x003FFFFE /* addr, word aligned */ 148 149 /* Packet header */ 150 151 #define UQ_HDR_OFF -4 /* offset */ 152 153 #define UQ_HLNT 0 /* length */ 154 #define UQ_HCTC 1 /* credits, type, CID */ 155 156 #define UQ_HCTC_V_CR 0 /* credits */ 157 #define UQ_HCTC_M_CR 0xF 158 #define UQ_HCTC_V_TYP 4 /* type */ 159 #define UQ_HCTC_M_TYP 0xF 160 #define UQ_TYP_SEQ 0 /* sequential */ 161 #define UQ_TYP_DAT 1 /* datagram */ 162 #define UQ_HCTC_V_CID 8 /* conn ID */ 163 #define UQ_HCTC_M_CID 0xFF 164 #define UQ_CID_MSCP 0 /* MSCP */ 165 #define UQ_CID_TMSCP 1 /* TMSCP */ 166 #define UQ_CID_DUP 2 /* DUP */ 167 #define UQ_CID_DIAG 0xFF /* diagnostic */ 168 169 #endif 170