1// DESCRIPTION: Verilator: Verilog Test module
2//
3// This file ONLY is placed into the Public Domain, for any use,
4// without warranty, 2021 by Krzysztof Bieganski.
5// SPDX-License-Identifier: CC0-1.0
6
7`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
8
9package config_pkg;
10   typedef struct packed {
11      int UPPER0;
12      int UPPER2;
13      int USE_QUAD0;
14      int USE_QUAD1;
15      int USE_QUAD2;
16   } config_struct;
17
18endpackage : config_pkg
19
20module t;
21    import config_pkg::*;
22
23    struct_submodule #(.MY_CONFIG('{
24                                       UPPER0: 10,
25                                       UPPER2: 20,
26                                       USE_QUAD0: 4,
27                                       USE_QUAD1: 5,
28                                       USE_QUAD2: 6
29                                    })) a_submodule_I ();
30endmodule : t
31
32module struct_submodule
33  import config_pkg::*;
34   #(parameter config_struct MY_CONFIG = '0);
35
36   initial begin
37      `checkd(MY_CONFIG.UPPER0, 10);
38      `checkd(MY_CONFIG.USE_QUAD0, 4);
39      `checkd(MY_CONFIG.USE_QUAD1, 5);
40      `checkd(MY_CONFIG.USE_QUAD2, 6);
41      `checkd(MY_CONFIG.UPPER2, 20);
42      $write("*-* All Finished *-*\n");
43      $finish;
44   end
45endmodule : struct_submodule
46