1 #ifndef R2_V810_DISASM_H 2 #define R2_V810_DISASM_H 3 4 #define V810_INSTR_MAXLEN 24 5 6 #define OPCODE(instr) (((instr) >> 10) & 0x3F) 7 #define REG1(instr) ((instr) & 0x1F) 8 #define REG2(instr) (((instr) >> 5) & 0x1F) 9 #define IMM5(instr) REG1((instr)) 10 #define COND(instr) (((instr) >> 9) & 0xF) 11 12 #define SEXT5(imm) (((imm) & 0x10) ? (imm) | 0xE0 : (imm)) 13 #define SEXT9(imm) (((imm) & 0x100) ? (imm) | 0xFFFFFE00 : (imm)) 14 #define SEXT26(imm) (((imm) & 0x2000000) ? (imm) | 0xFC000000 : (imm)) 15 16 #define DISP9(word1) SEXT9((word1) & 0x1FE) 17 #define DISP26(word1, word2) SEXT26((((word1) & 0x3FF) << 16) | (word2)) 18 19 enum v810_cmd_opcodes { 20 V810_MOV = 0x0, 21 V810_ADD = 0x1, 22 V810_SUB = 0x2, 23 V810_CMP = 0x3, 24 V810_SHL = 0x4, 25 V810_SHR = 0x5, 26 V810_JMP = 0x6, 27 V810_SAR = 0x7, 28 V810_MUL = 0x8, 29 V810_DIV = 0x9, 30 V810_MULU = 0xA, 31 V810_DIVU = 0xB, 32 V810_OR = 0xC, 33 V810_AND = 0xD, 34 V810_XOR = 0xE, 35 V810_NOT = 0xF, 36 V810_MOV_IMM5 = 0x10, 37 V810_ADD_IMM5 = 0x11, 38 V810_SETF = 0x12, 39 V810_CMP_IMM5 = 0x13, 40 V810_SHL_IMM5 = 0x14, 41 V810_SHR_IMM5 = 0x15, 42 V810_CLI = 0x16, 43 V810_SAR_IMM5 = 0x17, 44 V810_TRAP = 0x18, 45 V810_RETI = 0x19, 46 V810_HALT = 0x1A, 47 V810_LDSR = 0x1C, 48 V810_STSR = 0x1D, 49 V810_SEI = 0x1E, 50 V810_BSTR = 0x1F, 51 V810_BCOND = 0x20, 52 V810_MOVEA = 0x28, 53 V810_ADDI = 0x29, 54 V810_JR = 0x2A, 55 V810_JAL = 0x2B, 56 V810_ORI = 0x2C, 57 V810_ANDI = 0x2D, 58 V810_XORI = 0x2E, 59 V810_MOVHI = 0x2F, 60 V810_LDB = 0x30, 61 V810_LDH = 0x31, 62 V810_LDW = 0x33, 63 V810_STB = 0x34, 64 V810_STH = 0x35, 65 V810_STW = 0x37, 66 V810_INB = 0x38, 67 V810_INH = 0x39, 68 V810_CAXI = 0x3A, 69 V810_INW = 0x3B, 70 V810_OUTB = 0x3C, 71 V810_OUTH = 0x3D, 72 V810_EXT = 0x3E, 73 V810_OUTW = 0x3F, 74 }; 75 76 enum v810_bit_ops { 77 V810_BIT_SCH0U = 0x0, 78 V810_BIT_SCH0D = 0x1, 79 V810_BIT_SCH1U = 0x2, 80 V810_BIT_SCH1D = 0x3, 81 V810_BIT_ORU = 0x8, 82 V810_BIT_ANDU = 0x9, 83 V810_BIT_XORU = 0xA, 84 V810_BIT_MOVU = 0xB, 85 V810_BIT_ORNU = 0xC, 86 V810_BIT_ANDNU = 0xD, 87 V810_BIT_XORNU = 0xE, 88 V810_BIT_NOTU = 0xF, 89 }; 90 91 enum v810_ext_ops { 92 V810_EXT_CMPF_S = 0x0, 93 V810_EXT_CVT_WS = 0x2, 94 V810_EXT_CVT_SW = 0x3, 95 V810_EXT_ADDF_S = 0x4, 96 V810_EXT_SUBF_S = 0x5, 97 V810_EXT_MULF_S = 0x6, 98 V810_EXT_DIVF_S = 0x7, 99 V810_EXT_XB = 0x8, 100 V810_EXT_XH = 0x9, 101 V810_EXT_REV = 0xA, 102 V810_EXT_TRNC_SW = 0xB, 103 V810_EXT_MPYHW = 0xC, 104 }; 105 106 enum v810_conds { 107 V810_COND_V = 0x0, 108 V810_COND_L = 0x1, 109 V810_COND_E = 0x2, 110 V810_COND_NH = 0x3, 111 V810_COND_N = 0x4, 112 V810_COND_NONE = 0x5, 113 V810_COND_LT = 0x6, 114 V810_COND_LE = 0x7, 115 V810_COND_NV = 0x8, 116 V810_COND_NL = 0x9, 117 V810_COND_NE = 0xA, 118 V810_COND_H = 0xB, 119 V810_COND_P = 0xC, 120 V810_COND_NOP = 0xD, 121 V810_COND_GE = 0xE, 122 V810_COND_GT = 0xF, 123 }; 124 125 enum v810_sysregs { 126 V810_SREG_EIPC = 0x0, 127 V810_SREG_EIPSW = 0x1, 128 V810_SREG_FEPC = 0x2, 129 V810_SREG_FEPSW = 0x3, 130 V810_SREG_ECR = 0x4, 131 V810_SREG_PSW = 0x5, 132 V810_SREG_PIR = 0x6, 133 V810_SREG_TKCW = 0x7, 134 V810_SREG_CHCW = 0x18, 135 V810_SREG_ADTRE = 0x19, 136 }; 137 138 struct v810_cmd { 139 unsigned type; 140 char instr[V810_INSTR_MAXLEN]; 141 char operands[V810_INSTR_MAXLEN]; 142 }; 143 144 int v810_decode_command(const ut8 *instr, int len, struct v810_cmd *cmd); 145 146 #endif /* R2_V810_DISASM_H */ 147