xref: /openbsd/sys/arch/amd64/include/specialreg.h (revision 6635b7e6)
1 /*	$OpenBSD: specialreg.h,v 1.116 2024/08/04 11:05:18 kettenis Exp $	*/
2 /*	$NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $	*/
3 /*	$NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $	*/
4 
5 /*-
6  * Copyright (c) 1991 The Regents of the University of California.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. Neither the name of the University nor the names of its contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31  * SUCH DAMAGE.
32  *
33  *	@(#)specialreg.h	7.1 (Berkeley) 5/9/91
34  */
35 
36 /*
37  * Bits in 386 special registers:
38  */
39 #define	CR0_PE	0x00000001	/* Protected mode Enable */
40 #define	CR0_MP	0x00000002	/* "Math" Present (NPX or NPX emulator) */
41 #define	CR0_EM	0x00000004	/* EMulate non-NPX coproc. (trap ESC only) */
42 #define	CR0_TS	0x00000008	/* Task Switched (if MP, trap ESC and WAIT) */
43 #define	CR0_ET	0x00000010	/* Extension Type (387 (if set) vs 287) */
44 #define	CR0_PG	0x80000000	/* PaGing enable */
45 
46 /*
47  * Bits in 486 special registers:
48  */
49 #define CR0_NE	0x00000020	/* Numeric Error enable (EX16 vs IRQ13) */
50 #define CR0_WP	0x00010000	/* Write Protect (honor PG_RW in all modes) */
51 #define CR0_AM	0x00040000	/* Alignment Mask (set to enable AC flag) */
52 #define	CR0_NW	0x20000000	/* Not Write-through */
53 #define	CR0_CD	0x40000000	/* Cache Disable */
54 
55 /*
56  * bits in CR3
57  */
58 #define CR3_PCID	0xfffULL
59 #define CR3_PWT		(1ULL << 3)
60 #define CR3_PCD		(1ULL << 4)
61 #define CR3_REUSE_PCID	(1ULL << 63)
62 #define CR3_PADDR	0x7ffffffffffff000ULL
63 
64 /*
65  * bits in the pentiums %cr4 register:
66  */
67 
68 #define	CR4_VME	0x00000001	/* virtual 8086 mode extension enable */
69 #define	CR4_PVI 0x00000002	/* protected mode virtual interrupt enable */
70 #define	CR4_TSD 0x00000004	/* restrict RDTSC instruction to cpl 0 only */
71 #define	CR4_DE	0x00000008	/* debugging extension */
72 #define	CR4_PSE	0x00000010	/* large (4MB) page size enable */
73 #define	CR4_PAE 0x00000020	/* physical address extension enable */
74 #define	CR4_MCE	0x00000040	/* machine check enable */
75 #define	CR4_PGE	0x00000080	/* page global enable */
76 #define	CR4_PCE	0x00000100	/* enable RDPMC instruction for all cpls */
77 #define	CR4_OSFXSR	0x00000200	/* enable fxsave/fxrestor and SSE */
78 #define	CR4_OSXMMEXCPT	0x00000400	/* enable unmasked SSE exceptions */
79 #define	CR4_UMIP	0x00000800	/* user mode instruction prevention */
80 #define	CR4_VMXE	0x00002000	/* enable virtual machine operation */
81 #define	CR4_SMXE	0x00004000	/* enable safe mode operation */
82 #define	CR4_FSGSBASE	0x00010000	/* enable {RD,WR}{FS,GS}BASE ops */
83 #define	CR4_PCIDE	0x00020000	/* enable process-context IDs */
84 #define	CR4_OSXSAVE	0x00040000	/* enable XSAVE and extended states */
85 #define	CR4_KL		0x00080000	/* enable AES Key Locker */
86 #define	CR4_SMEP	0x00100000	/* supervisor mode exec protection */
87 #define	CR4_SMAP	0x00200000	/* supervisor mode access prevention */
88 #define	CR4_PKE		0x00400000	/* user-mode protection keys */
89 #define	CR4_CET		0x00800000	/* control-flow enforcement tech */
90 #define	CR4_PKS		0x01000000	/* supervisor-mode protection keys */
91 #define	CR4_UINTR	0x02000000	/* user interrupts enable bit */
92 
93 /*
94  * Extended state components, for xsave/xrstor family of instructions.
95  */
96 #define	XFEATURE_X87		0x00000001	/* x87 FPU/MMX state */
97 #define	XFEATURE_SSE		0x00000002	/* SSE state */
98 #define	XFEATURE_AVX		0x00000004	/* AVX state */
99 #define	XFEATURE_BNDREG		0x00000008	/* MPX state */
100 #define	XFEATURE_BNDCSR		0x00000010	/* MPX state */
101 #define	XFEATURE_MPX		(XFEATURE_BNDREG | XFEATURE_BNDCSR)
102 #define	XFEATURE_OPMASK		0x00000020	/* AVX-512 opmask */
103 #define	XFEATURE_ZMM_HI256	0x00000040	/* AVX-512 ZMM0-7 */
104 #define	XFEATURE_HI16_ZMM	0x00000080	/* AVX-512 ZMM16-31 */
105 #define	XFEATURE_AVX512		(XFEATURE_OPMASK | XFEATURE_ZMM_HI256 | \
106 				 XFEATURE_HI16_ZMM)
107 #define	XFEATURE_PT		0x00000100	/* processor trace */
108 #define	XFEATURE_PKRU		0x00000200	/* user page key */
109 #define	XFEATURE_PASID		0x00000400	/* Process ASIDs */
110 #define	XFEATURE_CET_U		0x00000800	/* ctrl-flow enforce user */
111 #define	XFEATURE_CET_S		0x00001000	/* ctrl-flow enforce system */
112 #define	XFEATURE_CET		(XFEATURE_CET_U | XFEATURE_CET_S)
113 #define	XFEATURE_HDC		0x00002000	/* HW duty cycling */
114 #define	XFEATURE_UINTR		0x00004000	/* user interrupts */
115 #define	XFEATURE_LBR		0x00008000	/* last-branch record */
116 #define	XFEATURE_HWP		0x00010000	/* HW P-states */
117 #define	XFEATURE_TILECFG	0x00020000	/* AMX state */
118 #define	XFEATURE_TILEDATA	0x00040000	/* AMX state */
119 #define	XFEATURE_AMX		(XFEATURE_TILECFG | XFEATURE_TILEDATA)
120 
121 /* valid only in xcomp_bv field: */
122 #define XFEATURE_COMPRESSED	(1ULL << 63)	/* compressed format */
123 
124 /* which bits are for XCR0 and which for the XSS MSR? */
125 #define XFEATURE_XCR0_MASK \
126 	(XFEATURE_X87 | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
127 	 XFEATURE_AVX512 | XFEATURE_PKRU | XFEATURE_AMX)
128 #define	XFEATURE_XSS_MASK \
129 	(XFEATURE_PT | XFEATURE_PASID | XFEATURE_CET | XFEATURE_HDC | \
130 	 XFEATURE_UINTR | XFEATURE_LBR | XFEATURE_HWP)
131 
132 /*
133  * CPUID "features" bits (CPUID function 0x1):
134  * EDX bits, then ECX bits
135  */
136 
137 #define	CPUID_FPU	0x00000001	/* processor has an FPU? */
138 #define	CPUID_VME	0x00000002	/* has virtual mode (%cr4's VME/PVI) */
139 #define	CPUID_DE	0x00000004	/* has debugging extension */
140 #define	CPUID_PSE	0x00000008	/* has 4MB page size extension */
141 #define	CPUID_TSC	0x00000010	/* has time stamp counter */
142 #define	CPUID_MSR	0x00000020	/* has model specific registers */
143 #define	CPUID_PAE	0x00000040	/* has phys address extension */
144 #define	CPUID_MCE	0x00000080	/* has machine check exception */
145 #define	CPUID_CX8	0x00000100	/* has CMPXCHG8B instruction */
146 #define	CPUID_APIC	0x00000200	/* has enabled APIC */
147 #define	CPUID_SYS1	0x00000400	/* has SYSCALL/SYSRET inst. (Cyrix) */
148 #define	CPUID_SEP	0x00000800	/* has SYSCALL/SYSRET inst. (AMD/Intel) */
149 #define	CPUID_MTRR	0x00001000	/* has memory type range register */
150 #define	CPUID_PGE	0x00002000	/* has page global extension */
151 #define	CPUID_MCA	0x00004000	/* has machine check architecture */
152 #define	CPUID_CMOV	0x00008000	/* has CMOVcc instruction */
153 #define	CPUID_PAT	0x00010000	/* has page attribute table */
154 #define	CPUID_PSE36	0x00020000	/* has 36bit page size extension */
155 #define	CPUID_PSN	0x00040000	/* has processor serial number */
156 #define	CPUID_CFLUSH	0x00080000	/* CFLUSH insn supported */
157 #define	CPUID_B20	0x00100000	/* reserved */
158 #define	CPUID_DS	0x00200000	/* Debug Store */
159 #define	CPUID_ACPI	0x00400000	/* ACPI performance modulation regs */
160 #define	CPUID_MMX	0x00800000	/* has MMX instructions */
161 #define	CPUID_FXSR	0x01000000	/* has FXRSTOR instruction */
162 #define	CPUID_SSE	0x02000000	/* has streaming SIMD extensions */
163 #define	CPUID_SSE2	0x04000000	/* has streaming SIMD extensions #2 */
164 #define	CPUID_SS	0x08000000	/* self-snoop */
165 #define	CPUID_HTT	0x10000000	/* Hyper-Threading Technology */
166 #define	CPUID_TM	0x20000000	/* thermal monitor (TCC) */
167 #define	CPUID_B30	0x40000000	/* reserved */
168 #define	CPUID_PBE	0x80000000	/* Pending Break Enabled restarts clock */
169 #define CPUID_EDX_BITS \
170     ("\20" "\01FPU" "\02VME" "\03DE" "\04PSE" "\05TSC" "\06MSR" "\07PAE" \
171      "\010MCE" "\011CX8" "\012APIC" "\014SEP" "\015MTRR" "\016PGE" "\017MCA" \
172      "\020CMOV" "\021PAT" "\022PSE36" "\023PSN" "\024CFLUSH" "\026DS" \
173      "\027ACPI" "\030MMX" "\031FXSR" "\032SSE" "\033SSE2" "\034SS" "\035HTT" \
174      "\036TM" "\040PBE" )
175 
176 #define	CPUIDECX_SSE3	0x00000001	/* streaming SIMD extensions #3 */
177 #define	CPUIDECX_PCLMUL	0x00000002	/* Carryless Multiplication */
178 #define	CPUIDECX_DTES64	0x00000004	/* 64bit debug store */
179 #define	CPUIDECX_MWAIT	0x00000008	/* Monitor/Mwait */
180 #define	CPUIDECX_DSCPL	0x00000010	/* CPL Qualified Debug Store */
181 #define	CPUIDECX_VMX	0x00000020	/* Virtual Machine Extensions */
182 #define	CPUIDECX_SMX	0x00000040	/* Safer Mode Extensions */
183 #define	CPUIDECX_EST	0x00000080	/* enhanced SpeedStep */
184 #define	CPUIDECX_TM2	0x00000100	/* thermal monitor 2 */
185 #define	CPUIDECX_SSSE3	0x00000200	/* Supplemental Streaming SIMD Ext. 3 */
186 #define	CPUIDECX_CNXTID	0x00000400	/* Context ID */
187 #define CPUIDECX_SDBG	0x00000800	/* Silicon debug capability */
188 #define	CPUIDECX_FMA3	0x00001000	/* Fused Multiply Add */
189 #define	CPUIDECX_CX16	0x00002000	/* has CMPXCHG16B instruction */
190 #define	CPUIDECX_XTPR	0x00004000	/* xTPR Update Control */
191 #define	CPUIDECX_PDCM	0x00008000	/* Perfmon and Debug Capability */
192 #define	CPUIDECX_PCID	0x00020000	/* Process-context ID Capability */
193 #define	CPUIDECX_DCA	0x00040000	/* Direct Cache Access */
194 #define	CPUIDECX_SSE41	0x00080000	/* Streaming SIMD Extensions 4.1 */
195 #define	CPUIDECX_SSE42	0x00100000	/* Streaming SIMD Extensions 4.2 */
196 #define	CPUIDECX_X2APIC	0x00200000	/* Extended xAPIC Support */
197 #define	CPUIDECX_MOVBE	0x00400000	/* MOVBE Instruction */
198 #define	CPUIDECX_POPCNT	0x00800000	/* POPCNT Instruction */
199 #define	CPUIDECX_DEADLINE	0x01000000	/* APIC one-shot via deadline */
200 #define	CPUIDECX_AES	0x02000000	/* AES Instruction */
201 #define	CPUIDECX_XSAVE	0x04000000	/* XSAVE/XSTOR States */
202 #define	CPUIDECX_OSXSAVE	0x08000000	/* OSXSAVE */
203 #define	CPUIDECX_AVX	0x10000000	/* Advanced Vector Extensions */
204 #define	CPUIDECX_F16C	0x20000000	/* 16bit fp conversion  */
205 #define	CPUIDECX_RDRAND	0x40000000	/* RDRAND instruction  */
206 #define	CPUIDECX_HV	0x80000000	/* Running on hypervisor */
207 #define CPUID_ECX_BITS \
208     ("\20" "\01SSE3" "\02PCLMUL" "\03DTES64" "\04MWAIT" "\05DS-CPL" "\06VMX" \
209      "\07SMX" "\010EST" "\011TM2" "\012SSSE3" "\013CNXT-ID" "\014SDBG" \
210      "\015FMA3" "\016CX16" "\017xTPR" "\020PDCM" "\022PCID" "\023DCA" \
211      "\024SSE4.1" "\025SSE4.2" "\026x2APIC" "\027MOVBE" "\030POPCNT" \
212      "\031DEADLINE" "\032AES" "\033XSAVE" "\034OSXSAVE" "\035AVX" "\036F16C" \
213      "\037RDRAND" "\040HV" )
214 
215 /*
216  * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0)
217  * EBX bits
218  */
219 #define	SEFF0EBX_FSGSBASE	0x00000001 /* {RD,WR}[FG]SBASE instructions */
220 #define	SEFF0EBX_TSC_ADJUST	0x00000002 /* Has IA32_TSC_ADJUST MSR */
221 #define	SEFF0EBX_SGX		0x00000004 /* Software Guard Extensions */
222 #define	SEFF0EBX_BMI1		0x00000008 /* advanced bit manipulation */
223 #define	SEFF0EBX_HLE		0x00000010 /* Hardware Lock Elision */
224 #define	SEFF0EBX_AVX2		0x00000020 /* Advanced Vector Extensions 2 */
225 #define	SEFF0EBX_SMEP		0x00000080 /* Supervisor mode exec protection */
226 #define	SEFF0EBX_BMI2		0x00000100 /* advanced bit manipulation */
227 #define	SEFF0EBX_ERMS		0x00000200 /* Enhanced REP MOVSB/STOSB */
228 #define	SEFF0EBX_INVPCID	0x00000400 /* INVPCID instruction */
229 #define	SEFF0EBX_RTM		0x00000800 /* Restricted Transactional Memory */
230 #define	SEFF0EBX_PQM		0x00001000 /* Quality of Service Monitoring */
231 #define	SEFF0EBX_MPX		0x00004000 /* Memory Protection Extensions */
232 #define	SEFF0EBX_AVX512F	0x00010000 /* AVX-512 foundation inst */
233 #define	SEFF0EBX_AVX512DQ	0x00020000 /* AVX-512 double/quadword */
234 #define	SEFF0EBX_RDSEED		0x00040000 /* RDSEED instruction */
235 #define	SEFF0EBX_ADX		0x00080000 /* ADCX/ADOX instructions */
236 #define	SEFF0EBX_SMAP		0x00100000 /* Supervisor mode access prevent */
237 #define	SEFF0EBX_AVX512IFMA	0x00200000 /* AVX-512 integer mult-add */
238 #define	SEFF0EBX_PCOMMIT	0x00400000 /* Persistent commit inst */
239 #define	SEFF0EBX_CLFLUSHOPT	0x00800000 /* cache line flush */
240 #define	SEFF0EBX_CLWB		0x01000000 /* cache line write back */
241 #define	SEFF0EBX_PT		0x02000000 /* Processor Trace */
242 #define	SEFF0EBX_AVX512PF	0x04000000 /* AVX-512 prefetch */
243 #define	SEFF0EBX_AVX512ER	0x08000000 /* AVX-512 exp/reciprocal */
244 #define	SEFF0EBX_AVX512CD	0x10000000 /* AVX-512 conflict detection */
245 #define	SEFF0EBX_SHA		0x20000000 /* SHA Extensions */
246 #define	SEFF0EBX_AVX512BW	0x40000000 /* AVX-512 byte/word inst */
247 #define	SEFF0EBX_AVX512VL	0x80000000 /* AVX-512 vector len inst */
248 #define SEFF0_EBX_BITS \
249     ("\20" "\01FSGSBASE" "\02TSC_ADJUST" "\03SGX" "\04BMI1" "\05HLE" \
250      "\06AVX2" "\010SMEP" "\011BMI2" "\012ERMS" "\013INVPCID" "\014RTM" \
251      "\015PQM" "\017MPX" "\021AVX512F" "\022AVX512DQ" "\023RDSEED" "\024ADX" \
252      "\025SMAP" "\026AVX512IFMA" "\027PCOMMIT" "\030CLFLUSHOPT" "\031CLWB" \
253      "\032PT" "\033AVX512PF" "\034AVX512ER" "\035AVX512CD" "\036SHA" \
254      "\037AVX512BW" "\040AVX512VL" )
255 
256 /* SEFF ECX bits */
257 #define SEFF0ECX_PREFETCHWT1	0x00000001 /* PREFETCHWT1 instruction */
258 #define SEFF0ECX_AVX512VBMI	0x00000002 /* AVX-512 vector bit inst */
259 #define SEFF0ECX_UMIP		0x00000004 /* UMIP support */
260 #define SEFF0ECX_PKU		0x00000008 /* Page prot keys for user mode */
261 #define SEFF0ECX_OSPKE		0x00000010 /* OS enabled RD/WRPKRU */
262 #define SEFF0ECX_WAITPKG	0x00000020 /* UMONITOR/UMWAIT/TPAUSE insns */
263 #define SEFF0ECX_PKS		0x80000000 /* Page prot keys for sup mode */
264 #define SEFF0_ECX_BITS \
265     ("\20" "\01PREFETCHWT1" "\02AVX512VBMI" "\03UMIP" "\04PKU" "\06WAITPKG" \
266      "\040PKS" )
267 
268 /* SEFF EDX bits */
269 #define SEFF0EDX_AVX512_4FNNIW	0x00000004 /* AVX-512 neural network insns */
270 #define SEFF0EDX_AVX512_4FMAPS	0x00000008 /* AVX-512 mult accum single prec */
271 #define SEFF0EDX_SRBDS_CTRL	0x00000200 /* MCU_OPT_CTRL MSR */
272 #define SEFF0EDX_MD_CLEAR	0x00000400 /* Microarch Data Clear */
273 #define SEFF0EDX_TSXFA		0x00002000 /* TSX Forced Abort */
274 #define SEFF0EDX_IBT		0x00100000 /* Indirect Branch Tracking */
275 #define SEFF0EDX_IBRS		0x04000000 /* IBRS / IBPB Speculation Control */
276 #define SEFF0EDX_STIBP		0x08000000 /* STIBP Speculation Control */
277 #define SEFF0EDX_L1DF		0x10000000 /* L1D_FLUSH */
278 #define SEFF0EDX_ARCH_CAP	0x20000000 /* Has IA32_ARCH_CAPABILITIES MSR */
279 #define SEFF0EDX_SSBD		0x80000000 /* Spec Store Bypass Disable */
280 #define SEFF0_EDX_BITS \
281     ("\20" "\03AVX512FNNIW" "\04AVX512FMAPS" "\012SRBDS_CTRL" "\013MD_CLEAR" \
282      "\016TSXFA" "\025IBT" "\033IBRS,IBPB" "\034STIBP" "\035L1DF" "\040SSBD" )
283 
284 /*
285  * Thermal and Power Management (CPUID function 0x6) EAX bits
286  */
287 #define	TPM_SENSOR	0x00000001	 /* Digital temp sensor */
288 #define	TPM_ARAT	0x00000004	 /* APIC Timer Always Running */
289 #define TPM_EAX_BITS \
290     ("\20" "\01SENSOR" "\03ARAT" )
291 /* Thermal and Power Management (CPUID function 0x6) ECX bits */
292 #define	TPM_EFFFREQ	0x00000001	 /* APERF & MPERF MSR present */
293 #define TPM_ECX_BITS \
294     ("\20" "\01EFFFREQ" )
295 
296  /*
297   * "Architectural Performance Monitoring" bits (CPUID function 0x0a):
298   * EAX bits, EBX bits, EDX bits.
299   */
300 
301 #define CPUIDEAX_VERID			0x000000ff /* Version ID */
302 #define CPUIDEAX_NUM_GC(cpuid)		(((cpuid) >>  8) & 0x000000ff)
303 #define CPUIDEAX_BIT_GC(cpuid)		(((cpuid) >> 16) & 0x000000ff)
304 #define CPUIDEAX_LEN_EBX(cpuid)		(((cpuid) >> 24) & 0x000000ff)
305 
306 #define CPUIDEBX_EVT_CORE		(1 << 0) /* Core cycle */
307 #define CPUIDEBX_EVT_INST		(1 << 1) /* Instruction retired */
308 #define CPUIDEBX_EVT_REFR		(1 << 2) /* Reference cycles */
309 #define CPUIDEBX_EVT_CACHE_REF		(1 << 3) /* Last-level cache ref. */
310 #define CPUIDEBX_EVT_CACHE_MIS		(1 << 4) /* Last-level cache miss. */
311 #define CPUIDEBX_EVT_BRANCH_INST	(1 << 5) /* Branch instruction ret. */
312 #define CPUIDEBX_EVT_BRANCH_MISP	(1 << 6) /* Branch mispredict ret. */
313 
314 #define CPUIDEDX_NUM_FC(cpuid)		(((cpuid) >> 0) & 0x0000001f)
315 #define CPUIDEDX_BIT_FC(cpuid)		(((cpuid) >> 5) & 0x000000ff)
316 
317 /*
318  * CPUID "extended features" bits (CPUID function 0x80000001):
319  * EDX bits, then ECX bits
320  */
321 
322 #define	CPUID_MPC	0x00080000	/* Multiprocessing Capable */
323 #define	CPUID_NXE	0x00100000	/* No-Execute Extension */
324 #define	CPUID_MMXX	0x00400000	/* AMD MMX Extensions */
325 #define	CPUID_FFXSR	0x02000000	/* fast FP/MMX save/restore */
326 #define	CPUID_PAGE1GB	0x04000000	/* 1-GByte pages */
327 #define CPUID_RDTSCP	0x08000000	/* RDTSCP / IA32_TSC_AUX available */
328 #define	CPUID_LONG	0x20000000	/* long mode */
329 #define	CPUID_3DNOW2	0x40000000	/* 3DNow! Instruction Extension */
330 #define	CPUID_3DNOW	0x80000000	/* 3DNow! Instructions */
331 #define CPUIDE_EDX_BITS \
332     ("\20" "\024MPC" "\025NXE" "\027MMXX" "\032FFXSR" "\033PAGE1GB" \
333      "\034RDTSCP" "\036LONG" "\0373DNOW2" "\0403DNOW" )
334 
335 #define	CPUIDECX_LAHF		0x00000001 /* LAHF and SAHF instructions */
336 #define	CPUIDECX_CMPLEG		0x00000002 /* Core MP legacy mode */
337 #define	CPUIDECX_SVM		0x00000004 /* Secure Virtual Machine */
338 #define	CPUIDECX_EAPICSP	0x00000008 /* Extended APIC space */
339 #define	CPUIDECX_AMCR8		0x00000010 /* LOCK MOV CR0 means MOV CR8 */
340 #define	CPUIDECX_ABM		0x00000020 /* LZCNT instruction */
341 #define	CPUIDECX_SSE4A		0x00000040 /* SSE4-A instruction set */
342 #define	CPUIDECX_MASSE		0x00000080 /* Misaligned SSE mode */
343 #define	CPUIDECX_3DNOWP		0x00000100 /* 3DNowPrefetch */
344 #define	CPUIDECX_OSVW		0x00000200 /* OS visible workaround */
345 #define	CPUIDECX_IBS		0x00000400 /* Instruction based sampling */
346 #define	CPUIDECX_XOP		0x00000800 /* Extended operating support */
347 #define	CPUIDECX_SKINIT		0x00001000 /* SKINIT and STGI are supported */
348 #define	CPUIDECX_WDT		0x00002000 /* Watchdog timer */
349 /* Reserved			0x00004000 */
350 #define	CPUIDECX_LWP		0x00008000 /* Lightweight profiling support */
351 #define	CPUIDECX_FMA4		0x00010000 /* 4-operand FMA instructions */
352 #define	CPUIDECX_TCE		0x00020000 /* Translation Cache Extension */
353 /* Reserved			0x00040000 */
354 #define	CPUIDECX_NODEID		0x00080000 /* Support for MSRC001C */
355 /* Reserved			0x00100000 */
356 #define	CPUIDECX_TBM		0x00200000 /* Trailing bit manipulation instruction */
357 #define	CPUIDECX_TOPEXT		0x00400000 /* Topology extensions support */
358 #define	CPUIDECX_CPCTR		0x00800000 /* core performance counter ext */
359 #define	CPUIDECX_DBKP		0x04000000 /* DataBreakpointExtension */
360 #define	CPUIDECX_PERFTSC	0x08000000 /* performance time-stamp counter */
361 #define	CPUIDECX_PCTRL3		0x10000000 /* L3 performance counter ext */
362 #define	CPUIDECX_MWAITX		0x20000000 /* MWAITX/MONITORX */
363 #define CPUIDE_ECX_BITS \
364     ("\20" "\01LAHF" "\02CMPLEG" "\03SVM" "\04EAPICSP" "\05AMCR8" "\06ABM" \
365      "\07SSE4A" "\010MASSE" "\0113DNOWP" "\012OSVW" "\013IBS" "\014XOP" \
366      "\015SKINIT" "\020WDT" "\021FMA4" "\022TCE" "\024NODEID" "\026TBM" \
367      "\027TOPEXT" "\030CPCTR" "\033DBKP" "\034PERFTSC" "\035PCTRL3" \
368      "\036MWAITX" )
369 
370 /*
371  * "Advanced Power Management Information" bits (CPUID function 0x80000007):
372  * EDX bits.
373  */
374 #define CPUIDEDX_HWPSTATE	(1 << 7)	/* Hardware P State Control */
375 #define CPUIDEDX_ITSC		(1 << 8)	/* Invariant TSC */
376 #define CPUID_APMI_EDX_BITS \
377     ("\20" "\010HWPSTATE" "\011ITSC" )
378 
379 /*
380  * AMD CPUID function 0x80000008 EBX bits
381  */
382 #define CPUIDEBX_INVLPGB	(1ULL <<  3)	/* INVLPG w/broadcast */
383 #define CPUIDEBX_IBPB		(1ULL << 12)	/* Speculation Control IBPB */
384 #define CPUIDEBX_IBRS		(1ULL << 14)	/* Speculation Control IBRS */
385 #define CPUIDEBX_STIBP		(1ULL << 15)	/* Speculation Control STIBP */
386 #define CPUIDEBX_IBRS_ALWAYSON	(1ULL << 16)	/* IBRS always on mode */
387 #define CPUIDEBX_STIBP_ALWAYSON	(1ULL << 17)	/* STIBP always on mode */
388 #define CPUIDEBX_IBRS_PREF	(1ULL << 18)	/* IBRS preferred */
389 #define CPUIDEBX_IBRS_SAME_MODE	(1ULL << 19)	/* IBRS not mode-specific */
390 #define CPUIDEBX_SSBD		(1ULL << 24)	/* Speculation Control SSBD */
391 #define CPUIDEBX_VIRT_SSBD	(1ULL << 25)	/* Virt Spec Control SSBD */
392 #define CPUIDEBX_SSBD_NOTREQ	(1ULL << 26)	/* SSBD not required */
393 #define CPUID_AMDSPEC_EBX_BITS \
394     ("\20" "\04INVLPGB" "\015IBPB" "\017IBRS" "\020STIBP" "\021IBRS_ALL" \
395      "\022STIBP_ALL" "\023IBRS_PREF" "\024IBRS_SM" "\031SSBD" "\032VIRTSSBD" \
396      "\033SSBDNR" )
397 
398 /*
399  * AMD CPUID function 0x8000001F EAX bits
400  */
401 #define CPUIDEAX_SME		(1ULL << 0)  /* SME */
402 #define CPUIDEAX_SEV		(1ULL << 1)  /* SEV */
403 #define CPUIDEAX_PFLUSH_MSR	(1ULL << 2)  /* Page Flush MSR */
404 #define CPUIDEAX_SEVES		(1ULL << 3)  /* SEV-ES */
405 #define CPUIDEAX_SEVSNP		(1ULL << 4)  /* SEV-SNP */
406 #define CPUIDEAX_VMPL		(1ULL << 5)  /* VM Permission Levels */
407 #define CPUIDEAX_RMPQUERY	(1ULL << 6)  /* RMPQUERY */
408 #define CPUIDEAX_VMPLSSS	(1ULL << 7)  /* VMPL Supservisor Shadow Stack */
409 #define CPUIDEAX_SECTSC		(1ULL << 8)  /* Secure TSC */
410 #define CPUIDEAX_TSCAUXVIRT	(1ULL << 9)  /* TSC Aux Virtualization */
411 #define CPUIDEAX_HWECACHECOH	(1ULL << 10) /* Coherency Across Enc. Domains */
412 #define CPUIDEAX_64BITHOST	(1ULL << 11) /* SEV guest requires 64bit host */
413 #define CPUIDEAX_RESTINJ	(1ULL << 12) /* Restricted Injection */
414 #define CPUIDEAX_ALTINJ		(1ULL << 13) /* Alternate Injection */
415 #define CPUIDEAX_DBGSTSW	(1ULL << 14) /* Full debug state swap */
416 #define CPUIDEAX_IBSDISALLOW	(1ULL << 15) /* Disallowing IBS use by host */
417 #define CPUIDEAX_VTE		(1ULL << 16) /* Virt. Transparent Encryption */
418 #define CPUIDEAX_VMGEXITPARAM	(1ULL << 17) /* VMGEXIT Parameter */
419 #define CPUIDEAX_VTOMMSR	(1ULL << 18) /* Virtual TOM MSR */
420 #define CPUIDEAX_IBSVIRT	(1ULL << 19) /* IBS Virtualization for SEV-ES */
421 #define CPUIDEAX_VMSARPROT	(1ULL << 24) /* VMSA Register Protection */
422 #define CPUIDEAX_SMTPROT	(1ULL << 25) /* SMT Protection */
423 #define CPUIDEAX_SVSMPAGEMSR	(1ULL << 28) /* SVSM Communication Page MSR */
424 #define CPUIDEAX_NVSMSR		(1ULL << 29) /* NestedVirtSnpMsr */
425 #define CPUID_AMDSEV_EAX_BITS \
426     ("\20" "\01SME" "\02SEV" "\03PFLUSH_MSR" "\04SEVES" "\05SEVSNP" "\06VMPL" \
427      "\07RMPQUERY" "\010VMPLSSS" "\011SECTSC" "\012TSCAUXVIRT" \
428      "\013HWECACHECOH" "\014REQ64BITHOST" "\015RESTINJ" "\016ALTINJ" \
429      "\017DBGSTSW" "\020IBSDISALLOW" "\021VTE" "\022VMGEXITPARAM" \
430      "\023VTOMMSR" "\024IBSVIRT" "\031VMSARPROT" "\032SMTPROT" \
431      "\035SVSMPAGEMSR" "\036NVSMSR" )
432 
433 /* Number of encrypted guests */
434 #define CPUID_AMDSEV_ECX_BITS ("\20")
435 
436 /* Minimum ASID for SEV enabled, SEV-ES disabled guest. */
437 #define CPUID_AMDSEV_EDX_BITS ("\20")
438 
439 #define	CPUID2FAMILY(cpuid)	(((cpuid) >> 8) & 15)
440 #define	CPUID2MODEL(cpuid)	(((cpuid) >> 4) & 15)
441 #define	CPUID2STEPPING(cpuid)	((cpuid) & 15)
442 
443 #define	CPUID(code, eax, ebx, ecx, edx)                         \
444 	__asm volatile("cpuid"                                  \
445 	    : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)    \
446 	    : "a" (code))
447 #define	CPUID_LEAF(code, leaf, eax, ebx, ecx, edx)		\
448 	__asm volatile("cpuid"                                  \
449 	    : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)    \
450 	    : "a" (code), "c" (leaf))
451 
452 
453 /*
454  * Model-specific registers for the i386 family
455  */
456 #define MSR_P5_MC_ADDR		0x000	/* P5 only */
457 #define MSR_P5_MC_TYPE		0x001	/* P5 only */
458 #define MSR_TSC			0x010
459 #define	MSR_CESR		0x011	/* P5 only (trap on P6) */
460 #define	MSR_CTR0		0x012	/* P5 only (trap on P6) */
461 #define	MSR_CTR1		0x013	/* P5 only (trap on P6) */
462 #define	MSR_PLATFORM_ID		0x017	/* Platform ID for microcode */
463 #define MSR_APICBASE		0x01b
464 #define APICBASE_BSP		0x100
465 #define APICBASE_ENABLE_X2APIC	0x400
466 #define APICBASE_GLOBAL_ENABLE	0x800
467 #define MSR_EBL_CR_POWERON	0x02a
468 #define MSR_EBC_FREQUENCY_ID    0x02c   /* Pentium 4 only */
469 #define	MSR_TEST_CTL		0x033
470 #define MSR_IA32_FEATURE_CONTROL 0x03a
471 #define MSR_TSC_ADJUST		0x03b
472 #define MSR_SPEC_CTRL		0x048	/* Speculation Control IBRS / STIBP */
473 #define SPEC_CTRL_IBRS		(1ULL << 0)
474 #define SPEC_CTRL_STIBP		(1ULL << 1)
475 #define SPEC_CTRL_SSBD		(1ULL << 2)
476 #define MSR_PRED_CMD		0x049	/* Speculation Control IBPB */
477 #define PRED_CMD_IBPB		(1ULL << 0)
478 #define MSR_BIOS_UPDT_TRIG	0x079
479 #define	MSR_BBL_CR_D0		0x088	/* PII+ only */
480 #define	MSR_BBL_CR_D1		0x089	/* PII+ only */
481 #define	MSR_BBL_CR_D2		0x08a	/* PII+ only */
482 #define MSR_BIOS_SIGN		0x08b
483 #define MSR_SMM_MONITOR_CTL	0x09b
484 #define MSR_SMBASE		0x09e
485 #define MSR_PERFCTR0		0x0c1
486 #define MSR_PERFCTR1		0x0c2
487 #define MSR_FSB_FREQ		0x0cd	/* Core Duo/Solo only */
488 #define MSR_MPERF		0x0e7
489 #define MSR_APERF		0x0e8
490 #define MSR_MTRRcap		0x0fe
491 #define MTRRcap_FIXED		0x100	/* bit 8 - fixed MTRRs supported */
492 #define MTRRcap_WC		0x400	/* bit 10 - WC type supported */
493 #define MTRRcap_SMRR		0x800	/* bit 11 - SMM range reg supported */
494 #define MSR_ARCH_CAPABILITIES	0x10a
495 #define ARCH_CAP_RDCL_NO		(1 <<  0) /* Meltdown safe */
496 #define ARCH_CAP_IBRS_ALL		(1 <<  1) /* enhanced IBRS */
497 #define ARCH_CAP_RSBA			(1 <<  2) /* RSB Alternate */
498 #define ARCH_CAP_SKIP_L1DFL_VMENTRY	(1 <<  3)
499 #define ARCH_CAP_SSB_NO			(1 <<  4) /* Spec St Byp safe */
500 #define ARCH_CAP_MDS_NO			(1 <<  5) /* microarch data-sampling */
501 #define ARCH_CAP_IF_PSCHANGE_MC_NO	(1 <<  6) /* PS MCE safe */
502 #define ARCH_CAP_TSX_CTRL		(1 <<  7) /* has TSX_CTRL MSR */
503 #define ARCH_CAP_TAA_NO			(1 <<  8) /* TSX AA safe */
504 #define ARCH_CAP_MCU_CONTROL		(1 <<  9) /* has MCU_CTRL MSR */
505 #define ARCH_CAP_MISC_PACKAGE_CTLS	(1 << 10) /* has MISC_PKG_CTLS MSR */
506 #define ARCH_CAP_ENERGY_FILTERING_CTL	(1 << 11) /* r/w energy fltring bit */
507 #define ARCH_CAP_DOITM			(1 << 12) /* Data oprnd indpdnt tmng */
508 #define ARCH_CAP_SBDR_SSDP_NO		(1 << 13) /* SBDR/SSDP safe */
509 #define ARCH_CAP_FBSDP_NO		(1 << 14) /* FBSDP safe */
510 #define ARCH_CAP_PSDP_NO		(1 << 15) /* PSDP safe */
511 #define ARCH_CAP_FB_CLEAR		(1 << 17) /* MD_CLEAR covers FB */
512 #define ARCH_CAP_FB_CLEAR_CTRL		(1 << 18)
513 #define ARCH_CAP_RRSBA			(1 << 19) /* has RRSBA if not dis */
514 #define ARCH_CAP_BHI_NO			(1 << 20) /* BHI safe */
515 #define ARCH_CAP_XAPIC_DISABLE_STATUS	(1 << 21) /* can disable xAPIC */
516 #define ARCH_CAP_OVERCLOCKING_STATUS	(1 << 23) /* has OVRCLCKNG_STAT MSR */
517 #define ARCH_CAP_PBRSB_NO		(1 << 24) /* PBSR safe */
518 #define ARCH_CAP_GDS_CTRL		(1 << 25) /* has GDS_MITG_DIS/LOCK */
519 #define ARCH_CAP_GDS_NO			(1 << 26) /* GDS safe */
520 #define ARCH_CAP_RFDS_NO		(1 << 27) /* RFDS safe */
521 #define ARCH_CAP_RFDS_CLEAR		(1 << 28) /* use VERW for RFDS */
522 #define ARCH_CAP_MSR_BITS \
523     ("\20" "\02IBRS_ALL" "\03RSBA" "\04SKIP_L1DFL" "\05SSB_NO" "\06MDS_NO" \
524      "\07IF_PSCHANGE" "\010TSX_CTRL" "\011TAA_NO" "\012MCU_CONTROL" \
525      "\013MISC_PKG_CT" "\014ENERGY_FILT" "\015DOITM" "\016SBDR_SSDP_N" \
526      "\017FBSDP_NO" "\020PSDP_NO" "\022FB_CLEAR" "\023FB_CLEAR_CT" \
527      "\024RRSBA" "\025BHI_NO" "\026XAPIC_DIS" "\030OVERCLOCK" "\031PBRSB_NO" \
528      "\032GDS_CTRL" "\033GDS_NO" "\034RFDS_NO" "\035RFDS_CLEAR" )
529 
530 #define MSR_FLUSH_CMD		0x10b
531 #define FLUSH_CMD_L1D_FLUSH	0x1	/* (1ULL << 0) */
532 #define	MSR_BBL_CR_ADDR		0x116	/* PII+ only */
533 #define	MSR_BBL_CR_DECC		0x118	/* PII+ only */
534 #define	MSR_BBL_CR_CTL		0x119	/* PII+ only */
535 #define	MSR_BBL_CR_TRIG		0x11a	/* PII+ only */
536 #define	MSR_BBL_CR_BUSY		0x11b	/* PII+ only */
537 #define	MSR_BBL_CR_CTR3		0x11e	/* PII+ only */
538 #define	MSR_TSX_CTRL		0x122
539 #define TSX_CTRL_RTM_DISABLE		(1ULL << 0)
540 #define TSX_CTRL_TSX_CPUID_CLEAR	(1ULL << 1)
541 #define	MSR_MCU_OPT_CTRL	0x123
542 #define RNGDS_MITG_DIS			(1ULL << 0)
543 #define	MSR_SYSENTER_CS		0x174 	/* PII+ only */
544 #define	MSR_SYSENTER_ESP	0x175 	/* PII+ only */
545 #define	MSR_SYSENTER_EIP	0x176   /* PII+ only */
546 #define MSR_MCG_CAP		0x179
547 #define MSR_MCG_STATUS		0x17a
548 #define MSR_MCG_CTL		0x17b
549 #define MSR_EVNTSEL0		0x186
550 #define MSR_EVNTSEL1		0x187
551 #define MSR_PERF_STATUS		0x198	/* Pentium M */
552 #define MSR_PERF_CTL		0x199	/* Pentium M */
553 #define PERF_CTL_TURBO		0x100000000ULL /* bit 32 - turbo mode */
554 #define MSR_THERM_CONTROL	0x19a
555 #define MSR_THERM_INTERRUPT	0x19b
556 #define MSR_THERM_STATUS	0x19c
557 #define MSR_THERM_STATUS_VALID_BIT	0x80000000
558 #define	MSR_THERM_STATUS_TEMP(msr)	((msr >> 16) & 0x7f)
559 #define MSR_THERM2_CTL		0x19d	/* Pentium M */
560 #define MSR_MISC_ENABLE		0x1a0
561 /*
562  * MSR_MISC_ENABLE (0x1a0)
563  *
564  * Enable Fast Strings: enables fast REP MOVS/REP STORS (R/W)
565  * Enable TCC: Enable automatic thermal control circuit (R/W)
566  * Performance monitoring available: 1 if enabled (R/O)
567  * Branch trace storage unavailable: 1 if unsupported (R/O)
568  * Processor event based sampling unavailable: 1 if unsupported (R/O)
569  * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W)
570  * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W)
571  * Limit CPUID maxval: 1 to limit CPUID leaf nodes to 0x2 and lower (R/W)
572  * Enable xTPR message disable: 1 to disable xTPR messages
573  * XD bit disable: 1 to disable NX capability (bit 34, or bit 2 of %edx/%rdx)
574  */
575 #define MISC_ENABLE_FAST_STRINGS		(1 << 0)
576 #define MISC_ENABLE_TCC				(1 << 3)
577 #define MISC_ENABLE_PERF_MON_AVAILABLE		(1 << 7)
578 #define MISC_ENABLE_BTS_UNAVAILABLE		(1 << 11)
579 #define MISC_ENABLE_PEBS_UNAVAILABLE		(1 << 12)
580 #define MISC_ENABLE_EIST_ENABLED		(1 << 16)
581 #define MISC_ENABLE_ENABLE_MONITOR_FSM		(1 << 18)
582 #define MISC_ENABLE_LIMIT_CPUID_MAXVAL		(1 << 22)
583 #define MISC_ENABLE_xTPR_MESSAGE_DISABLE	(1 << 23)
584 #define MISC_ENABLE_XD_BIT_DISABLE		(1 << 2)
585 
586 /*
587  * for Core i Series and newer Xeons, see
588  * http://www.intel.com/content/dam/www/public/us/en/
589  * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf
590  */
591 #define MSR_TEMPERATURE_TARGET	0x1a2	/* Core i Series, Newer Xeons */
592 #define MSR_TEMPERATURE_TARGET_TJMAX(msr) (((msr) >> 16) & 0xff)
593 /*
594  * not documented anywhere, see intelcore_update_sensor()
595  * only available Core Duo and Core Solo Processors
596  */
597 #define MSR_TEMPERATURE_TARGET_UNDOCUMENTED	0x0ee
598 #define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED	0x40000000
599 #define MSR_DEBUGCTLMSR		0x1d9
600 #define MSR_LASTBRANCHFROMIP	0x1db
601 #define MSR_LASTBRANCHTOIP	0x1dc
602 #define MSR_LASTINTFROMIP	0x1dd
603 #define MSR_LASTINTTOIP		0x1de
604 #define MSR_ROB_CR_BKUPTMPDR6	0x1e0
605 #define	MSR_MTRRvarBase		0x200
606 #define	MSR_MTRRfix64K_00000	0x250
607 #define	MSR_MTRRfix16K_80000	0x258
608 #define	MSR_MTRRfix4K_C0000	0x268
609 #define MSR_CR_PAT		0x277
610 #define MSR_MTRRdefType		0x2ff
611 #define MTRRdefType_FIXED_ENABLE	0x400 /* bit 10 - fixed MTRR enabled */
612 #define MTRRdefType_ENABLE	0x800 /* bit 11 - MTRRs enabled */
613 #define MSR_PERF_FIXED_CTR1	0x30a	/* CPU_CLK_Unhalted.Core */
614 #define MSR_PERF_FIXED_CTR2	0x30b	/* CPU_CLK.Unhalted.Ref */
615 #define MSR_PERF_FIXED_CTR_CTRL 0x38d
616 #define MSR_PERF_FIXED_CTR_FC_DIS	0x0 /* disable counter */
617 #define MSR_PERF_FIXED_CTR_FC_1	0x1 /* count ring 1 */
618 #define MSR_PERF_FIXED_CTR_FC_123	0x2 /* count rings 1,2,3 */
619 #define MSR_PERF_FIXED_CTR_FC_ANY	0x3 /* count everything */
620 #define MSR_PERF_FIXED_CTR_FC_MASK	0x3
621 #define MSR_PERF_FIXED_CTR_FC(_i, _v)	((_v) << (4 * (_i)))
622 #define MSR_PERF_FIXED_CTR_ANYTHR(_i)	(0x4 << (4 * (_i)))
623 #define MSR_PERF_FIXED_CTR_INT(_i)	(0x8 << (4 * (_i)))
624 #define MSR_PERF_GLOBAL_CTRL	0x38f
625 #define MSR_PERF_GLOBAL_CTR1_EN	(1ULL << 33)
626 #define MSR_PERF_GLOBAL_CTR2_EN	(1ULL << 34)
627 #define MSR_PKG_C3_RESIDENCY	0x3f8
628 #define MSR_PKG_C6_RESIDENCY	0x3f9
629 #define MSR_PKG_C7_RESIDENCY	0x3fa
630 #define MSR_CORE_C3_RESIDENCY	0x3fc
631 #define MSR_CORE_C6_RESIDENCY	0x3fd
632 #define MSR_CORE_C7_RESIDENCY	0x3fe
633 #define MSR_MC0_CTL		0x400
634 #define MSR_MC0_STATUS		0x401
635 #define MSR_MC0_ADDR		0x402
636 #define MSR_MC0_MISC		0x403
637 #define MSR_MC1_CTL		0x404
638 #define MSR_MC1_STATUS		0x405
639 #define MSR_MC1_ADDR		0x406
640 #define MSR_MC1_MISC		0x407
641 #define MSR_MC2_CTL		0x408
642 #define MSR_MC2_STATUS		0x409
643 #define MSR_MC2_ADDR		0x40a
644 #define MSR_MC2_MISC		0x40b
645 #define MSR_MC4_CTL		0x40c
646 #define MSR_MC4_STATUS		0x40d
647 #define MSR_MC4_ADDR		0x40e
648 #define MSR_MC4_MISC		0x40f
649 #define MSR_MC3_CTL		0x410
650 #define MSR_MC3_STATUS		0x411
651 #define MSR_MC3_ADDR		0x412
652 #define MSR_MC3_MISC		0x413
653 #define MSR_PKG_C2_RESIDENCY	0x60d
654 #define MSR_PKG_C8_RESIDENCY	0x630
655 #define MSR_PKG_C9_RESIDENCY	0x631
656 #define MSR_PKG_C10_RESIDENCY	0x632
657 #define MSR_U_CET		0x6a0
658 #define MSR_CET_ENDBR_EN		(1 << 2)
659 #define MSR_CET_NO_TRACK_EN		(1 << 4)
660 #define MSR_S_CET		0x6a2
661 #define MSR_PKRS		0x6e1
662 #define MSR_XSS			0xda0
663 
664 /* VIA MSR */
665 #define MSR_CENT_TMTEMPERATURE	0x1423	/* Thermal monitor temperature */
666 
667 /*
668  * AMD K6/K7 MSRs.
669  */
670 #define	MSR_K6_UWCCR		0xc0000085
671 #define	MSR_K7_EVNTSEL0		0xc0010000
672 #define	MSR_K7_EVNTSEL1		0xc0010001
673 #define	MSR_K7_EVNTSEL2		0xc0010002
674 #define	MSR_K7_EVNTSEL3		0xc0010003
675 #define	MSR_K7_PERFCTR0		0xc0010004
676 #define	MSR_K7_PERFCTR1		0xc0010005
677 #define	MSR_K7_PERFCTR2		0xc0010006
678 #define	MSR_K7_PERFCTR3		0xc0010007
679 
680 /*
681  * AMD K8 (Opteron) MSRs.
682  */
683 #define	MSR_PATCH_LEVEL	0x0000008b
684 #define	MSR_SYSCFG	0xc0000010
685 
686 #define MSR_EFER	0xc0000080	/* Extended feature enable */
687 #define EFER_SCE	0x00000001	/* SYSCALL extension */
688 #define EFER_LME	0x00000100	/* Long Mode Enabled */
689 #define	EFER_LMA	0x00000400	/* Long Mode Active */
690 #define EFER_NXE	0x00000800	/* No-Execute Enabled */
691 #define EFER_SVME	0x00001000	/* SVM Enabled */
692 
693 #define MSR_STAR	0xc0000081	/* 32 bit syscall gate addr */
694 #define MSR_LSTAR	0xc0000082	/* 64 bit syscall gate addr */
695 #define MSR_CSTAR	0xc0000083	/* compat syscall gate addr */
696 #define MSR_SFMASK	0xc0000084	/* flags to clear on syscall */
697 
698 #define MSR_FSBASE	0xc0000100	/* 64bit offset for fs: */
699 #define MSR_GSBASE	0xc0000101	/* 64bit offset for gs: */
700 #define MSR_KERNELGSBASE 0xc0000102	/* storage for swapgs ins */
701 #define MSR_PATCH_LOADER	0xc0010020
702 #define MSR_INT_PEN_MSG	0xc0010055	/* Interrupt pending message */
703 
704 #define MSR_DE_CFG	0xc0011029	/* Decode Configuration */
705 #define	DE_CFG_721	0x00000001	/* errata 721 */
706 #define DE_CFG_SERIALIZE_LFENCE	(1 << 1)	/* Enable serializing lfence */
707 #define DE_CFG_SERIALIZE_9 (1 << 9)	/* Zenbleed chickenbit */
708 
709 #define IPM_C1E_CMP_HLT	0x10000000
710 #define IPM_SMI_CMP_HLT	0x08000000
711 
712 /*
713  * These require a 'passcode' for access.  See cpufunc.h.
714  */
715 #define	MSR_HWCR	0xc0010015
716 #define		HWCR_FFDIS		0x00000040
717 #define		HWCR_TSCFREQSEL		0x01000000
718 
719 #define	MSR_PSTATEDEF(_n)	(0xc0010064 + (_n))
720 #define		PSTATEDEF_EN		0x8000000000000000ULL
721 
722 #define	MSR_NB_CFG	0xc001001f
723 #define		NB_CFG_DISIOREQLOCK	0x0000000000000004ULL
724 #define		NB_CFG_DISDATMSK	0x0000001000000000ULL
725 
726 #define MSR_SEV_STATUS	0xc0010131
727 #define		SEV_STAT_ENABLED	0x00000001
728 
729 #define	MSR_LS_CFG	0xc0011020
730 #define		LS_CFG_DIS_LS2_SQUISH	0x02000000
731 
732 #define	MSR_IC_CFG	0xc0011021
733 #define		IC_CFG_DIS_SEQ_PREFETCH	0x00000800
734 
735 #define	MSR_DC_CFG	0xc0011022
736 #define		DC_CFG_DIS_CNV_WC_SSO	0x00000004
737 #define		DC_CFG_DIS_SMC_CHK_BUF	0x00000400
738 
739 #define	MSR_BU_CFG	0xc0011023
740 #define		BU_CFG_THRL2IDXCMPDIS	0x0000080000000000ULL
741 #define		BU_CFG_WBPFSMCCHKDIS	0x0000200000000000ULL
742 #define		BU_CFG_WBENHWSBDIS	0x0001000000000000ULL
743 
744 /*
745  * Constants related to MTRRs
746  */
747 #define MTRR_N64K		8	/* numbers of fixed-size entries */
748 #define MTRR_N16K		16
749 #define MTRR_N4K		64
750 
751 /*
752  * the following four 3-byte registers control the non-cacheable regions.
753  * These registers must be written as three separate bytes.
754  *
755  * NCRx+0: A31-A24 of starting address
756  * NCRx+1: A23-A16 of starting address
757  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
758  *
759  * The non-cacheable region's starting address must be aligned to the
760  * size indicated by the NCR_SIZE_xx field.
761  */
762 #define NCR1	0xc4
763 #define NCR2	0xc7
764 #define NCR3	0xca
765 #define NCR4	0xcd
766 
767 #define NCR_SIZE_0K	0
768 #define NCR_SIZE_4K	1
769 #define NCR_SIZE_8K	2
770 #define NCR_SIZE_16K	3
771 #define NCR_SIZE_32K	4
772 #define NCR_SIZE_64K	5
773 #define NCR_SIZE_128K	6
774 #define NCR_SIZE_256K	7
775 #define NCR_SIZE_512K	8
776 #define NCR_SIZE_1M	9
777 #define NCR_SIZE_2M	10
778 #define NCR_SIZE_4M	11
779 #define NCR_SIZE_8M	12
780 #define NCR_SIZE_16M	13
781 #define NCR_SIZE_32M	14
782 #define NCR_SIZE_4G	15
783 
784 /*
785  * Performance monitor events.
786  *
787  * Note that 586-class and 686-class CPUs have different performance
788  * monitors available, and they are accessed differently:
789  *
790  *	686-class: `rdpmc' instruction
791  *	586-class: `rdmsr' instruction, CESR MSR
792  *
793  * The descriptions of these events are too lengthy to include here.
794  * See Appendix A of "Intel Architecture Software Developer's
795  * Manual, Volume 3: System Programming" for more information.
796  */
797 
798 /*
799  * 586-class CESR MSR format.  Lower 16 bits is CTR0, upper 16 bits
800  * is CTR1.
801  */
802 
803 #define	PMC5_CESR_EVENT			0x003f
804 #define	PMC5_CESR_OS			0x0040
805 #define	PMC5_CESR_USR			0x0080
806 #define	PMC5_CESR_E			0x0100
807 #define	PMC5_CESR_P			0x0200
808 
809 #define PMC5_DATA_READ			0x00
810 #define PMC5_DATA_WRITE			0x01
811 #define PMC5_DATA_TLB_MISS		0x02
812 #define PMC5_DATA_READ_MISS		0x03
813 #define PMC5_DATA_WRITE_MISS		0x04
814 #define PMC5_WRITE_M_E			0x05
815 #define PMC5_DATA_LINES_WBACK		0x06
816 #define PMC5_DATA_CACHE_SNOOP		0x07
817 #define PMC5_DATA_CACHE_SNOOP_HIT	0x08
818 #define PMC5_MEM_ACCESS_BOTH_PIPES	0x09
819 #define PMC5_BANK_CONFLICTS		0x0a
820 #define PMC5_MISALIGNED_DATA		0x0b
821 #define PMC5_INST_READ			0x0c
822 #define PMC5_INST_TLB_MISS		0x0d
823 #define PMC5_INST_CACHE_MISS		0x0e
824 #define PMC5_SEGMENT_REG_LOAD		0x0f
825 #define PMC5_BRANCHES		 	0x12
826 #define PMC5_BTB_HITS		 	0x13
827 #define PMC5_BRANCH_TAKEN		0x14
828 #define PMC5_PIPELINE_FLUSH		0x15
829 #define PMC5_INST_EXECUTED		0x16
830 #define PMC5_INST_EXECUTED_V_PIPE	0x17
831 #define PMC5_BUS_UTILIZATION		0x18
832 #define PMC5_WRITE_BACKUP_STALL		0x19
833 #define PMC5_DATA_READ_STALL		0x1a
834 #define PMC5_WRITE_E_M_STALL		0x1b
835 #define PMC5_LOCKED_BUS			0x1c
836 #define PMC5_IO_CYCLE			0x1d
837 #define PMC5_NONCACHE_MEM_READ		0x1e
838 #define PMC5_AGI_STALL			0x1f
839 #define PMC5_FLOPS			0x22
840 #define PMC5_BP0_MATCH			0x23
841 #define PMC5_BP1_MATCH			0x24
842 #define PMC5_BP2_MATCH			0x25
843 #define PMC5_BP3_MATCH			0x26
844 #define PMC5_HARDWARE_INTR		0x27
845 #define PMC5_DATA_RW			0x28
846 #define PMC5_DATA_RW_MISS		0x29
847 
848 /*
849  * 686-class Event Selector MSR format.
850  */
851 
852 #define	PMC6_EVTSEL_EVENT		0x000000ff
853 #define	PMC6_EVTSEL_UNIT		0x0000ff00
854 #define	PMC6_EVTSEL_UNIT_SHIFT		8
855 #define	PMC6_EVTSEL_USR			(1 << 16)
856 #define	PMC6_EVTSEL_OS			(1 << 17)
857 #define	PMC6_EVTSEL_E			(1 << 18)
858 #define	PMC6_EVTSEL_PC			(1 << 19)
859 #define	PMC6_EVTSEL_INT			(1 << 20)
860 #define	PMC6_EVTSEL_EN			(1 << 22)	/* PerfEvtSel0 only */
861 #define	PMC6_EVTSEL_INV			(1 << 23)
862 #define	PMC6_EVTSEL_COUNTER_MASK	0xff000000
863 #define	PMC6_EVTSEL_COUNTER_MASK_SHIFT	24
864 
865 /* Data Cache Unit */
866 #define	PMC6_DATA_MEM_REFS		0x43
867 #define	PMC6_DCU_LINES_IN		0x45
868 #define	PMC6_DCU_M_LINES_IN		0x46
869 #define	PMC6_DCU_M_LINES_OUT		0x47
870 #define	PMC6_DCU_MISS_OUTSTANDING	0x48
871 
872 /* Instruction Fetch Unit */
873 #define	PMC6_IFU_IFETCH			0x80
874 #define	PMC6_IFU_IFETCH_MISS		0x81
875 #define	PMC6_ITLB_MISS			0x85
876 #define	PMC6_IFU_MEM_STALL		0x86
877 #define	PMC6_ILD_STALL			0x87
878 
879 /* L2 Cache */
880 #define	PMC6_L2_IFETCH			0x28
881 #define	PMC6_L2_LD			0x29
882 #define	PMC6_L2_ST			0x2a
883 #define	PMC6_L2_LINES_IN		0x24
884 #define	PMC6_L2_LINES_OUT		0x26
885 #define	PMC6_L2_M_LINES_INM		0x25
886 #define	PMC6_L2_M_LINES_OUTM		0x27
887 #define	PMC6_L2_RQSTS			0x2e
888 #define	PMC6_L2_ADS			0x21
889 #define	PMC6_L2_DBUS_BUSY		0x22
890 #define	PMC6_L2_DBUS_BUSY_RD		0x23
891 
892 /* External Bus Logic */
893 #define	PMC6_BUS_DRDY_CLOCKS		0x62
894 #define	PMC6_BUS_LOCK_CLOCKS		0x63
895 #define	PMC6_BUS_REQ_OUTSTANDING	0x60
896 #define	PMC6_BUS_TRAN_BRD		0x65
897 #define	PMC6_BUS_TRAN_RFO		0x66
898 #define	PMC6_BUS_TRANS_WB		0x67
899 #define	PMC6_BUS_TRAN_IFETCH		0x68
900 #define	PMC6_BUS_TRAN_INVAL		0x69
901 #define	PMC6_BUS_TRAN_PWR		0x6a
902 #define	PMC6_BUS_TRANS_P		0x6b
903 #define	PMC6_BUS_TRANS_IO		0x6c
904 #define	PMC6_BUS_TRAN_DEF		0x6d
905 #define	PMC6_BUS_TRAN_BURST		0x6e
906 #define	PMC6_BUS_TRAN_ANY		0x70
907 #define	PMC6_BUS_TRAN_MEM		0x6f
908 #define	PMC6_BUS_DATA_RCV		0x64
909 #define	PMC6_BUS_BNR_DRV		0x61
910 #define	PMC6_BUS_HIT_DRV		0x7a
911 #define	PMC6_BUS_HITM_DRDV		0x7b
912 #define	PMC6_BUS_SNOOP_STALL		0x7e
913 
914 /* Floating Point Unit */
915 #define	PMC6_FLOPS			0xc1
916 #define	PMC6_FP_COMP_OPS_EXE		0x10
917 #define	PMC6_FP_ASSIST			0x11
918 #define	PMC6_MUL			0x12
919 #define	PMC6_DIV			0x12
920 #define	PMC6_CYCLES_DIV_BUSY		0x14
921 
922 /* Memory Ordering */
923 #define	PMC6_LD_BLOCKS			0x03
924 #define	PMC6_SB_DRAINS			0x04
925 #define	PMC6_MISALIGN_MEM_REF		0x05
926 #define	PMC6_EMON_KNI_PREF_DISPATCHED	0x07	/* P-III only */
927 #define	PMC6_EMON_KNI_PREF_MISS		0x4b	/* P-III only */
928 
929 /* Instruction Decoding and Retirement */
930 #define	PMC6_INST_RETIRED		0xc0
931 #define	PMC6_UOPS_RETIRED		0xc2
932 #define	PMC6_INST_DECODED		0xd0
933 #define	PMC6_EMON_KNI_INST_RETIRED	0xd8
934 #define	PMC6_EMON_KNI_COMP_INST_RET	0xd9
935 
936 /* Interrupts */
937 #define	PMC6_HW_INT_RX			0xc8
938 #define	PMC6_CYCLES_INT_MASKED		0xc6
939 #define	PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
940 
941 /* Branches */
942 #define	PMC6_BR_INST_RETIRED		0xc4
943 #define	PMC6_BR_MISS_PRED_RETIRED	0xc5
944 #define	PMC6_BR_TAKEN_RETIRED		0xc9
945 #define	PMC6_BR_MISS_PRED_TAKEN_RET	0xca
946 #define	PMC6_BR_INST_DECODED		0xe0
947 #define	PMC6_BTB_MISSES			0xe2
948 #define	PMC6_BR_BOGUS			0xe4
949 #define	PMC6_BACLEARS			0xe6
950 
951 /* Stalls */
952 #define	PMC6_RESOURCE_STALLS		0xa2
953 #define	PMC6_PARTIAL_RAT_STALLS		0xd2
954 
955 /* Segment Register Loads */
956 #define	PMC6_SEGMENT_REG_LOADS		0x06
957 
958 /* Clocks */
959 #define	PMC6_CPU_CLK_UNHALTED		0x79
960 
961 /* MMX Unit */
962 #define	PMC6_MMX_INSTR_EXEC		0xb0	/* Celeron, P-II, P-IIX only */
963 #define	PMC6_MMX_SAT_INSTR_EXEC		0xb1	/* P-II and P-III only */
964 #define	PMC6_MMX_UOPS_EXEC		0xb2	/* P-II and P-III only */
965 #define	PMC6_MMX_INSTR_TYPE_EXEC	0xb3	/* P-II and P-III only */
966 #define	PMC6_FP_MMX_TRANS		0xcc	/* P-II and P-III only */
967 #define	PMC6_MMX_ASSIST			0xcd	/* P-II and P-III only */
968 #define	PMC6_MMX_INSTR_RET		0xc3	/* P-II only */
969 
970 /* Segment Register Renaming */
971 #define	PMC6_SEG_RENAME_STALLS		0xd4	/* P-II and P-III only */
972 #define	PMC6_SEG_REG_RENAMES		0xd5	/* P-II and P-III only */
973 #define	PMC6_RET_SEG_RENAMES		0xd6	/* P-II and P-III only */
974 
975 /*
976  * AMD K7 Event Selector MSR format.
977  */
978 
979 #define	K7_EVTSEL_EVENT			0x000000ff
980 #define	K7_EVTSEL_UNIT			0x0000ff00
981 #define	K7_EVTSEL_UNIT_SHIFT		8
982 #define	K7_EVTSEL_USR			(1 << 16)
983 #define	K7_EVTSEL_OS			(1 << 17)
984 #define	K7_EVTSEL_E			(1 << 18)
985 #define	K7_EVTSEL_PC			(1 << 19)
986 #define	K7_EVTSEL_INT			(1 << 20)
987 #define	K7_EVTSEL_EN			(1 << 22)
988 #define	K7_EVTSEL_INV			(1 << 23)
989 #define	K7_EVTSEL_COUNTER_MASK		0xff000000
990 #define	K7_EVTSEL_COUNTER_MASK_SHIFT	24
991 
992 /* Segment Register Loads */
993 #define	K7_SEGMENT_REG_LOADS		0x20
994 
995 #define	K7_STORES_TO_ACTIVE_INST_STREAM	0x21
996 
997 /* Data Cache Unit */
998 #define	K7_DATA_CACHE_ACCESS		0x40
999 #define	K7_DATA_CACHE_MISS		0x41
1000 #define	K7_DATA_CACHE_REFILL		0x42
1001 #define	K7_DATA_CACHE_REFILL_SYSTEM	0x43
1002 #define	K7_DATA_CACHE_WBACK		0x44
1003 #define	K7_L2_DTLB_HIT			0x45
1004 #define	K7_L2_DTLB_MISS			0x46
1005 #define	K7_MISALIGNED_DATA_REF		0x47
1006 #define	K7_SYSTEM_REQUEST		0x64
1007 #define	K7_SYSTEM_REQUEST_TYPE		0x65
1008 
1009 #define	K7_SNOOP_HIT			0x73
1010 #define	K7_SINGLE_BIT_ECC_ERROR		0x74
1011 #define	K7_CACHE_LINE_INVAL		0x75
1012 #define	K7_CYCLES_PROCESSOR_IS_RUNNING	0x76
1013 #define	K7_L2_REQUEST			0x79
1014 #define	K7_L2_REQUEST_BUSY		0x7a
1015 
1016 /* Instruction Fetch Unit */
1017 #define	K7_IFU_IFETCH			0x80
1018 #define	K7_IFU_IFETCH_MISS		0x81
1019 #define	K7_IFU_REFILL_FROM_L2		0x82
1020 #define	K7_IFU_REFILL_FROM_SYSTEM	0x83
1021 #define	K7_ITLB_L1_MISS			0x84
1022 #define	K7_ITLB_L2_MISS			0x85
1023 #define	K7_SNOOP_RESYNC			0x86
1024 #define	K7_IFU_STALL			0x87
1025 
1026 #define	K7_RETURN_STACK_HITS		0x88
1027 #define	K7_RETURN_STACK_OVERFLOW	0x89
1028 
1029 /* Retired */
1030 #define	K7_RETIRED_INST			0xc0
1031 #define	K7_RETIRED_OPS			0xc1
1032 #define	K7_RETIRED_BRANCHES		0xc2
1033 #define	K7_RETIRED_BRANCH_MISPREDICTED	0xc3
1034 #define	K7_RETIRED_TAKEN_BRANCH		0xc4
1035 #define	K7_RETIRED_TAKEN_BRANCH_MISPREDICTED	0xc5
1036 #define	K7_RETIRED_FAR_CONTROL_TRANSFER	0xc6
1037 #define	K7_RETIRED_RESYNC_BRANCH	0xc7
1038 #define	K7_RETIRED_NEAR_RETURNS		0xc8
1039 #define	K7_RETIRED_NEAR_RETURNS_MISPREDICTED	0xc9
1040 #define	K7_RETIRED_INDIRECT_MISPREDICTED	0xca
1041 
1042 /* Interrupts */
1043 #define	K7_CYCLES_INT_MASKED		0xcd
1044 #define	K7_CYCLES_INT_PENDING_AND_MASKED	0xce
1045 #define	K7_HW_INTR_RECV			0xcf
1046 
1047 #define	K7_INSTRUCTION_DECODER_EMPTY	0xd0
1048 #define	K7_DISPATCH_STALLS		0xd1
1049 #define	K7_BRANCH_ABORTS_TO_RETIRE	0xd2
1050 #define	K7_SERIALIZE			0xd3
1051 #define	K7_SEGMENT_LOAD_STALL		0xd4
1052 #define	K7_ICU_FULL			0xd5
1053 #define	K7_RESERVATION_STATIONS_FULL	0xd6
1054 #define	K7_FPU_FULL			0xd7
1055 #define	K7_LS_FULL			0xd8
1056 #define	K7_ALL_QUIET_STALL		0xd9
1057 #define	K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING	0xda
1058 
1059 #define	K7_BP0_MATCH			0xdc
1060 #define	K7_BP1_MATCH			0xdd
1061 #define	K7_BP2_MATCH			0xde
1062 #define	K7_BP3_MATCH			0xdf
1063 
1064 /* VIA C3 crypto featureset: for amd64_has_xcrypt */
1065 #define C3_HAS_AES			1	/* cpu has AES */
1066 #define C3_HAS_SHA			2	/* cpu has SHA1 & SHA256 */
1067 #define C3_HAS_MM			4	/* cpu has RSA instructions */
1068 #define C3_HAS_AESCTR			8	/* cpu has AES-CTR instructions */
1069 
1070 /* Centaur Extended Feature flags */
1071 #define C3_CPUID_HAS_RNG		0x000004
1072 #define C3_CPUID_DO_RNG			0x000008
1073 #define C3_CPUID_HAS_ACE		0x000040
1074 #define C3_CPUID_DO_ACE			0x000080
1075 #define C3_CPUID_HAS_ACE2		0x000100
1076 #define C3_CPUID_DO_ACE2		0x000200
1077 #define C3_CPUID_HAS_PHE		0x000400
1078 #define C3_CPUID_DO_PHE			0x000800
1079 #define C3_CPUID_HAS_PMM		0x001000
1080 #define C3_CPUID_DO_PMM			0x002000
1081 
1082 /* VIA C3 xcrypt-* instruction context control options */
1083 #define	C3_CRYPT_CWLO_ROUND_M		0x0000000f
1084 #define	C3_CRYPT_CWLO_ALG_M		0x00000070
1085 #define	C3_CRYPT_CWLO_ALG_AES		0x00000000
1086 #define	C3_CRYPT_CWLO_KEYGEN_M		0x00000080
1087 #define	C3_CRYPT_CWLO_KEYGEN_HW		0x00000000
1088 #define	C3_CRYPT_CWLO_KEYGEN_SW		0x00000080
1089 #define	C3_CRYPT_CWLO_NORMAL		0x00000000
1090 #define	C3_CRYPT_CWLO_INTERMEDIATE	0x00000100
1091 #define	C3_CRYPT_CWLO_ENCRYPT		0x00000000
1092 #define	C3_CRYPT_CWLO_DECRYPT		0x00000200
1093 #define	C3_CRYPT_CWLO_KEY128		0x0000000a	/* 128bit, 10 rds */
1094 #define	C3_CRYPT_CWLO_KEY192		0x0000040c	/* 192bit, 12 rds */
1095 #define	C3_CRYPT_CWLO_KEY256		0x0000080e	/* 256bit, 15 rds */
1096 
1097 /* Intel Silicon Debug */
1098 #define IA32_DEBUG_INTERFACE		0xc80
1099 #define IA32_DEBUG_INTERFACE_ENABLE	0x00000001
1100 #define IA32_DEBUG_INTERFACE_LOCK	0x40000000
1101 #define IA32_DEBUG_INTERFACE_MASK	0x80000000
1102 
1103 /*
1104  * VMX
1105  */
1106 #define IA32_FEATURE_CONTROL_LOCK	0x01
1107 #define IA32_FEATURE_CONTROL_SMX_EN	0x02
1108 #define IA32_FEATURE_CONTROL_VMX_EN	0x04
1109 #define IA32_FEATURE_CONTROL_SENTER_EN (1ULL << 15)
1110 #define IA32_FEATURE_CONTROL_SENTER_PARAM_MASK 0x7f00
1111 #define IA32_VMX_BASIC			0x480
1112 #define IA32_VMX_PINBASED_CTLS		0x481
1113 #define IA32_VMX_PROCBASED_CTLS		0x482
1114 #define IA32_VMX_EXIT_CTLS		0x483
1115 #define IA32_VMX_ENTRY_CTLS		0x484
1116 #define IA32_VMX_MISC			0x485
1117 #define IA32_VMX_CR0_FIXED0		0x486
1118 #define IA32_VMX_CR0_FIXED1		0x487
1119 #define IA32_VMX_CR4_FIXED0		0x488
1120 #define IA32_VMX_CR4_FIXED1		0x489
1121 #define IA32_VMX_PROCBASED2_CTLS	0x48B
1122 #define IA32_VMX_EPT_VPID_CAP		0x48C
1123 #define IA32_VMX_TRUE_PINBASED_CTLS	0x48D
1124 #define IA32_VMX_TRUE_PROCBASED_CTLS	0x48E
1125 #define IA32_VMX_TRUE_EXIT_CTLS		0x48F
1126 #define IA32_VMX_TRUE_ENTRY_CTLS	0x490
1127 #define IA32_VMX_VMFUNC			0x491
1128 
1129 #define IA32_EPT_VPID_CAP_XO_TRANSLATIONS	(1ULL << 0)
1130 #define IA32_EPT_VPID_CAP_PAGE_WALK_4		(1ULL << 6)
1131 #define IA32_EPT_VPID_CAP_WB			(1ULL << 14)
1132 #define IA32_EPT_VPID_CAP_AD_BITS		(1ULL << 21)
1133 #define IA32_EPT_VPID_CAP_INVEPT_CONTEXT	(1ULL << 25)
1134 #define IA32_EPT_VPID_CAP_INVEPT_ALL		(1ULL << 26)
1135 
1136 #define IA32_EPT_PAGING_CACHE_TYPE_UC	0x0
1137 #define IA32_EPT_PAGING_CACHE_TYPE_WB	0x6
1138 #define IA32_EPT_AD_BITS_ENABLE		(1ULL << 6)
1139 #define IA32_EPT_PAGE_WALK_LENGTH	0x4
1140 
1141 /* VMX : IA32_VMX_BASIC bits */
1142 #define IA32_VMX_TRUE_CTLS_AVAIL			(1ULL << 55)
1143 
1144 /* VMX : IA32_VMX_PINBASED_CTLS bits */
1145 #define IA32_VMX_EXTERNAL_INT_EXITING			(1ULL << 0)
1146 #define IA32_VMX_NMI_EXITING				(1ULL << 3)
1147 #define IA32_VMX_VIRTUAL_NMIS				(1ULL << 5)
1148 #define IA32_VMX_ACTIVATE_VMX_PREEMPTION_TIMER		(1ULL << 6)
1149 #define IA32_VMX_PROCESS_POSTED_INTERRUPTS		(1ULL << 7)
1150 
1151 /* VMX : IA32_VMX_PROCBASED_CTLS bits */
1152 #define IA32_VMX_INTERRUPT_WINDOW_EXITING		(1ULL << 2)
1153 #define IA32_VMX_USE_TSC_OFFSETTING			(1ULL << 3)
1154 #define IA32_VMX_HLT_EXITING				(1ULL << 7)
1155 #define IA32_VMX_INVLPG_EXITING				(1ULL << 9)
1156 #define IA32_VMX_MWAIT_EXITING				(1ULL << 10)
1157 #define IA32_VMX_RDPMC_EXITING				(1ULL << 11)
1158 #define IA32_VMX_RDTSC_EXITING				(1ULL << 12)
1159 #define IA32_VMX_CR3_LOAD_EXITING			(1ULL << 15)
1160 #define IA32_VMX_CR3_STORE_EXITING			(1ULL << 16)
1161 #define IA32_VMX_CR8_LOAD_EXITING			(1ULL << 19)
1162 #define IA32_VMX_CR8_STORE_EXITING			(1ULL << 20)
1163 #define IA32_VMX_USE_TPR_SHADOW				(1ULL << 21)
1164 #define IA32_VMX_NMI_WINDOW_EXITING			(1ULL << 22)
1165 #define IA32_VMX_MOV_DR_EXITING				(1ULL << 23)
1166 #define IA32_VMX_UNCONDITIONAL_IO_EXITING		(1ULL << 24)
1167 #define IA32_VMX_USE_IO_BITMAPS				(1ULL << 25)
1168 #define IA32_VMX_MONITOR_TRAP_FLAG			(1ULL << 27)
1169 #define IA32_VMX_USE_MSR_BITMAPS			(1ULL << 28)
1170 #define IA32_VMX_MONITOR_EXITING			(1ULL << 29)
1171 #define IA32_VMX_PAUSE_EXITING				(1ULL << 30)
1172 #define IA32_VMX_ACTIVATE_SECONDARY_CONTROLS		(1ULL << 31)
1173 
1174 /* VMX : IA32_VMX_PROCBASED2_CTLS bits */
1175 #define IA32_VMX_VIRTUALIZE_APIC			(1ULL << 0)
1176 #define IA32_VMX_ENABLE_EPT				(1ULL << 1)
1177 #define IA32_VMX_DESCRIPTOR_TABLE_EXITING		(1ULL << 2)
1178 #define IA32_VMX_ENABLE_RDTSCP				(1ULL << 3)
1179 #define IA32_VMX_VIRTUALIZE_X2APIC_MODE			(1ULL << 4)
1180 #define IA32_VMX_ENABLE_VPID				(1ULL << 5)
1181 #define IA32_VMX_WBINVD_EXITING				(1ULL << 6)
1182 #define IA32_VMX_UNRESTRICTED_GUEST			(1ULL << 7)
1183 #define IA32_VMX_APIC_REGISTER_VIRTUALIZATION		(1ULL << 8)
1184 #define IA32_VMX_VIRTUAL_INTERRUPT_DELIVERY		(1ULL << 9)
1185 #define IA32_VMX_PAUSE_LOOP_EXITING			(1ULL << 10)
1186 #define IA32_VMX_RDRAND_EXITING				(1ULL << 11)
1187 #define IA32_VMX_ENABLE_INVPCID				(1ULL << 12)
1188 #define IA32_VMX_ENABLE_VM_FUNCTIONS			(1ULL << 13)
1189 #define IA32_VMX_VMCS_SHADOWING				(1ULL << 14)
1190 #define IA32_VMX_ENABLE_ENCLS_EXITING			(1ULL << 15)
1191 #define IA32_VMX_RDSEED_EXITING				(1ULL << 16)
1192 #define IA32_VMX_ENABLE_PML				(1ULL << 17)
1193 #define IA32_VMX_EPT_VIOLATION_VE			(1ULL << 18)
1194 #define IA32_VMX_CONCEAL_VMX_FROM_PT			(1ULL << 19)
1195 #define IA32_VMX_ENABLE_XSAVES_XRSTORS			(1ULL << 20)
1196 #define IA32_VMX_ENABLE_TSC_SCALING			(1ULL << 25)
1197 
1198 /* VMX : IA32_VMX_EXIT_CTLS bits */
1199 #define IA32_VMX_SAVE_DEBUG_CONTROLS			(1ULL << 2)
1200 #define IA32_VMX_HOST_SPACE_ADDRESS_SIZE		(1ULL << 9)
1201 #define IA32_VMX_LOAD_IA32_PERF_GLOBAL_CTRL_ON_EXIT	(1ULL << 12)
1202 #define IA32_VMX_ACKNOWLEDGE_INTERRUPT_ON_EXIT		(1ULL << 15)
1203 #define IA32_VMX_SAVE_IA32_PAT_ON_EXIT			(1ULL << 18)
1204 #define IA32_VMX_LOAD_IA32_PAT_ON_EXIT			(1ULL << 19)
1205 #define IA32_VMX_SAVE_IA32_EFER_ON_EXIT			(1ULL << 20)
1206 #define IA32_VMX_LOAD_IA32_EFER_ON_EXIT			(1ULL << 21)
1207 #define IA32_VMX_SAVE_VMX_PREEMPTION_TIMER		(1ULL << 22)
1208 #define IA32_VMX_CLEAR_IA32_BNDCFGS_ON_EXIT		(1ULL << 23)
1209 #define IA32_VMX_CONCEAL_VM_EXITS_FROM_PT		(1ULL << 24)
1210 #define IA32_VMX_LOAD_HOST_CET_STATE			(1ULL << 28)
1211 
1212 /* VMX: IA32_VMX_ENTRY_CTLS bits */
1213 #define IA32_VMX_LOAD_DEBUG_CONTROLS			(1ULL << 2)
1214 #define IA32_VMX_IA32E_MODE_GUEST			(1ULL << 9)
1215 #define IA32_VMX_ENTRY_TO_SMM				(1ULL << 10)
1216 #define IA32_VMX_DEACTIVATE_DUAL_MONITOR_TREATMENT	(1ULL << 11)
1217 #define IA32_VMX_LOAD_IA32_PERF_GLOBAL_CTRL_ON_ENTRY	(1ULL << 13)
1218 #define IA32_VMX_LOAD_IA32_PAT_ON_ENTRY			(1ULL << 14)
1219 #define IA32_VMX_LOAD_IA32_EFER_ON_ENTRY		(1ULL << 15)
1220 #define IA32_VMX_LOAD_IA32_BNDCFGS_ON_ENTRY		(1ULL << 16)
1221 #define IA32_VMX_CONCEAL_VM_ENTRIES_FROM_PT		(1ULL << 17)
1222 #define IA32_VMX_LOAD_GUEST_CET_STATE			(1ULL << 20)
1223 
1224 /*
1225  * VMX : VMCS Fields
1226  */
1227 
1228 /* 16-bit control fields */
1229 #define VMCS_GUEST_VPID			0x0000
1230 #define VMCS_POSTED_INT_NOTIF_VECTOR	0x0002
1231 #define VMCS_EPTP_INDEX			0x0004
1232 
1233 /* 16-bit guest state fields */
1234 #define VMCS_GUEST_IA32_ES_SEL		0x0800
1235 #define VMCS_GUEST_IA32_CS_SEL		0x0802
1236 #define VMCS_GUEST_IA32_SS_SEL		0x0804
1237 #define VMCS_GUEST_IA32_DS_SEL		0x0806
1238 #define VMCS_GUEST_IA32_FS_SEL		0x0808
1239 #define VMCS_GUEST_IA32_GS_SEL		0x080A
1240 #define VMCS_GUEST_IA32_LDTR_SEL	0x080C
1241 #define VMCS_GUEST_IA32_TR_SEL		0x080E
1242 #define VMCS_GUEST_INTERRUPT_STATUS	0x0810
1243 #define VMCS_GUEST_PML_INDEX		0x0812
1244 
1245 /* 16-bit host state fields */
1246 #define VMCS_HOST_IA32_ES_SEL		0x0C00
1247 #define VMCS_HOST_IA32_CS_SEL		0x0C02
1248 #define VMCS_HOST_IA32_SS_SEL		0x0C04
1249 #define VMCS_HOST_IA32_DS_SEL		0x0C06
1250 #define VMCS_HOST_IA32_FS_SEL		0x0C08
1251 #define VMCS_HOST_IA32_GS_SEL		0x0C0A
1252 #define VMCS_HOST_IA32_TR_SEL		0x0C0C
1253 
1254 /* 64-bit control fields */
1255 #define VMCS_IO_BITMAP_A		0x2000
1256 #define VMCS_IO_BITMAP_B		0x2002
1257 #define VMCS_MSR_BITMAP_ADDRESS		0x2004
1258 #define VMCS_EXIT_STORE_MSR_ADDRESS	0x2006
1259 #define VMCS_EXIT_LOAD_MSR_ADDRESS	0x2008
1260 #define VMCS_ENTRY_LOAD_MSR_ADDRESS	0x200A
1261 #define VMCS_EXECUTIVE_VMCS_POINTER	0x200C
1262 #define VMCS_PML_ADDRESS		0x200E
1263 #define VMCS_TSC_OFFSET			0x2010
1264 #define VMCS_VIRTUAL_APIC_ADDRESS	0x2012
1265 #define VMCS_APIC_ACCESS_ADDRESS	0x2014
1266 #define VMCS_POSTED_INTERRUPT_DESC	0x2016
1267 #define VMCS_VM_FUNCTION_CONTROLS	0x2018
1268 #define VMCS_GUEST_IA32_EPTP		0x201A
1269 #define VMCS_EOI_EXIT_BITMAP_0		0x201C
1270 #define VMCS_EOI_EXIT_BITMAP_1		0x201E
1271 #define VMCS_EOI_EXIT_BITMAP_2		0x2020
1272 #define VMCS_EOI_EXIT_BITMAP_3		0x2022
1273 #define VMCS_EPTP_LIST_ADDRESS		0x2024
1274 #define VMCS_VMREAD_BITMAP_ADDRESS	0x2026
1275 #define VMCS_VMWRITE_BITMAP_ADDRESS	0x2028
1276 #define VMCS_VIRTUALIZATION_EXC_ADDRESS	0x202A
1277 #define VMCS_XSS_EXITING_BITMAP		0x202C
1278 #define VMCS_ENCLS_EXITING_BITMAP	0x202E
1279 #define VMCS_TSC_MULTIPLIER		0x2032
1280 
1281 /* 64-bit RO data field */
1282 #define VMCS_GUEST_PHYSICAL_ADDRESS	0x2400
1283 
1284 /* 64-bit guest state fields */
1285 #define VMCS_LINK_POINTER		0x2800
1286 #define VMCS_GUEST_IA32_DEBUGCTL	0x2802
1287 #define VMCS_GUEST_IA32_PAT		0x2804
1288 #define VMCS_GUEST_IA32_EFER		0x2806
1289 #define VMCS_GUEST_IA32_PERF_GBL_CTRL	0x2808
1290 #define VMCS_GUEST_PDPTE0		0x280A
1291 #define VMCS_GUEST_PDPTE1		0x280C
1292 #define VMCS_GUEST_PDPTE2		0x280E
1293 #define VMCS_GUEST_PDPTE3		0x2810
1294 #define VMCS_GUEST_IA32_BNDCFGS		0x2812
1295 
1296 /* 64-bit host state fields */
1297 #define VMCS_HOST_IA32_PAT		0x2C00
1298 #define VMCS_HOST_IA32_EFER		0x2C02
1299 #define VMCS_HOST_IA32_PERF_GBL_CTRL	0x2C04
1300 
1301 /* 32-bit control fields */
1302 #define VMCS_PINBASED_CTLS		0x4000
1303 #define VMCS_PROCBASED_CTLS		0x4002
1304 #define VMCS_EXCEPTION_BITMAP		0x4004
1305 #define VMCS_PF_ERROR_CODE_MASK		0x4006
1306 #define VMCS_PF_ERROR_CODE_MATCH	0x4008
1307 #define VMCS_CR3_TARGET_COUNT		0x400A
1308 #define VMCS_EXIT_CTLS			0x400C
1309 #define VMCS_EXIT_MSR_STORE_COUNT	0x400E
1310 #define VMCS_EXIT_MSR_LOAD_COUNT	0x4010
1311 #define VMCS_ENTRY_CTLS			0x4012
1312 #define VMCS_ENTRY_MSR_LOAD_COUNT	0x4014
1313 #define VMCS_ENTRY_INTERRUPTION_INFO	0x4016
1314 #define VMCS_ENTRY_EXCEPTION_ERROR_CODE	0x4018
1315 #define VMCS_ENTRY_INSTRUCTION_LENGTH	0x401A
1316 #define VMCS_TPR_THRESHOLD		0x401C
1317 #define VMCS_PROCBASED2_CTLS		0x401E
1318 #define VMCS_PLE_GAP			0x4020
1319 #define VMCS_PLE_WINDOW			0x4022
1320 
1321 /* 32-bit RO data fields */
1322 #define VMCS_INSTRUCTION_ERROR		0x4400
1323 #define VMCS_EXIT_REASON		0x4402
1324 #define VMCS_EXIT_INTERRUPTION_INFO	0x4404
1325 #define VMCS_EXIT_INTERRUPTION_ERR_CODE	0x4406
1326 #define VMCS_IDT_VECTORING_INFO		0x4408
1327 #define VMCS_IDT_VECTORING_ERROR_CODE	0x440A
1328 #define VMCS_INSTRUCTION_LENGTH		0x440C
1329 #define VMCS_EXIT_INSTRUCTION_INFO	0x440E
1330 
1331 /* 32-bit guest state fields */
1332 #define VMCS_GUEST_IA32_ES_LIMIT	0x4800
1333 #define VMCS_GUEST_IA32_CS_LIMIT	0x4802
1334 #define VMCS_GUEST_IA32_SS_LIMIT	0x4804
1335 #define VMCS_GUEST_IA32_DS_LIMIT	0x4806
1336 #define VMCS_GUEST_IA32_FS_LIMIT	0x4808
1337 #define VMCS_GUEST_IA32_GS_LIMIT	0x480A
1338 #define VMCS_GUEST_IA32_LDTR_LIMIT	0x480C
1339 #define VMCS_GUEST_IA32_TR_LIMIT	0x480E
1340 #define VMCS_GUEST_IA32_GDTR_LIMIT	0x4810
1341 #define VMCS_GUEST_IA32_IDTR_LIMIT	0x4812
1342 #define VMCS_GUEST_IA32_ES_AR		0x4814
1343 #define VMCS_GUEST_IA32_CS_AR		0x4816
1344 #define VMCS_GUEST_IA32_SS_AR		0x4818
1345 #define VMCS_GUEST_IA32_DS_AR		0x481A
1346 #define VMCS_GUEST_IA32_FS_AR		0x481C
1347 #define VMCS_GUEST_IA32_GS_AR		0x481E
1348 #define VMCS_GUEST_IA32_LDTR_AR		0x4820
1349 #define VMCS_GUEST_IA32_TR_AR		0x4822
1350 #define VMCS_GUEST_INTERRUPTIBILITY_ST	0x4824
1351 #define VMCS_GUEST_ACTIVITY_STATE	0x4826
1352 #define VMCS_GUEST_SMBASE		0x4828
1353 #define VMCS_GUEST_IA32_SYSENTER_CS	0x482A
1354 #define VMCS_VMX_PREEMPTION_TIMER_VAL	0x482E
1355 
1356 /* 32-bit host state field */
1357 #define VMCS_HOST_IA32_SYSENTER_CS	0x4C00
1358 
1359 /* Natural-width control fields */
1360 #define VMCS_CR0_MASK			0x6000
1361 #define VMCS_CR4_MASK			0x6002
1362 #define VMCS_CR0_READ_SHADOW		0x6004
1363 #define VMCS_CR4_READ_SHADOW		0x6006
1364 #define VMCS_CR3_TARGET_0		0x6008
1365 #define VMCS_CR3_TARGET_1		0x600A
1366 #define VMCS_CR3_TARGET_2		0x600C
1367 #define VMCS_CR3_TARGET_3		0x600E
1368 
1369 /* Natural-width RO fields */
1370 #define VMCS_GUEST_EXIT_QUALIFICATION	0x6400
1371 #define VMCS_IO_RCX			0x6402
1372 #define VMCS_IO_RSI			0x6404
1373 #define VMCS_IO_RDI			0x6406
1374 #define VMCS_IO_RIP			0x6408
1375 #define VMCS_GUEST_LINEAR_ADDRESS	0x640A
1376 
1377 /* Natural-width guest state fields */
1378 #define VMCS_GUEST_IA32_CR0		0x6800
1379 #define VMCS_GUEST_IA32_CR3		0x6802
1380 #define VMCS_GUEST_IA32_CR4		0x6804
1381 #define VMCS_GUEST_IA32_ES_BASE		0x6806
1382 #define VMCS_GUEST_IA32_CS_BASE		0x6808
1383 #define VMCS_GUEST_IA32_SS_BASE		0x680A
1384 #define VMCS_GUEST_IA32_DS_BASE		0x680C
1385 #define VMCS_GUEST_IA32_FS_BASE		0x680E
1386 #define VMCS_GUEST_IA32_GS_BASE		0x6810
1387 #define VMCS_GUEST_IA32_LDTR_BASE	0x6812
1388 #define VMCS_GUEST_IA32_TR_BASE		0x6814
1389 #define VMCS_GUEST_IA32_GDTR_BASE	0x6816
1390 #define VMCS_GUEST_IA32_IDTR_BASE	0x6818
1391 #define VMCS_GUEST_IA32_DR7		0x681A
1392 #define VMCS_GUEST_IA32_RSP		0x681C
1393 #define VMCS_GUEST_IA32_RIP		0x681E
1394 #define VMCS_GUEST_IA32_RFLAGS		0x6820
1395 #define VMCS_GUEST_PENDING_DBG_EXC	0x6822
1396 #define VMCS_GUEST_IA32_SYSENTER_ESP	0x6824
1397 #define VMCS_GUEST_IA32_SYSENTER_EIP	0x6826
1398 #define VMCS_GUEST_IA32_S_CET		0x6828
1399 
1400 /* Natural-width host state fields */
1401 #define VMCS_HOST_IA32_CR0		0x6C00
1402 #define VMCS_HOST_IA32_CR3		0x6C02
1403 #define VMCS_HOST_IA32_CR4		0x6C04
1404 #define VMCS_HOST_IA32_FS_BASE		0x6C06
1405 #define VMCS_HOST_IA32_GS_BASE		0x6C08
1406 #define VMCS_HOST_IA32_TR_BASE		0x6C0A
1407 #define VMCS_HOST_IA32_GDTR_BASE	0x6C0C
1408 #define VMCS_HOST_IA32_IDTR_BASE	0x6C0E
1409 #define VMCS_HOST_IA32_SYSENTER_ESP	0x6C10
1410 #define VMCS_HOST_IA32_SYSENTER_EIP	0x6C12
1411 #define VMCS_HOST_IA32_RSP		0x6C14
1412 #define VMCS_HOST_IA32_RIP		0x6C16
1413 #define VMCS_HOST_IA32_S_CET		0x6C18
1414 
1415 #define IA32_VMX_INVVPID_INDIV_ADDR_CTX	0x0
1416 #define IA32_VMX_INVVPID_SINGLE_CTX	0x1
1417 #define IA32_VMX_INVVPID_ALL_CTX	0x2
1418 #define IA32_VMX_INVVPID_SINGLE_CTX_GLB	0x3
1419 
1420 #define IA32_VMX_INVEPT_SINGLE_CTX	0x1
1421 #define IA32_VMX_INVEPT_GLOBAL_CTX	0x2
1422 
1423 #define IA32_VMX_EPT_FAULT_READ		(1ULL << 0)
1424 #define IA32_VMX_EPT_FAULT_WRITE	(1ULL << 1)
1425 #define IA32_VMX_EPT_FAULT_EXEC		(1ULL << 2)
1426 
1427 #define IA32_VMX_EPT_FAULT_WAS_READABLE (1ULL << 3)
1428 #define IA32_VMX_EPT_FAULT_WAS_WRITABLE	(1ULL << 4)
1429 #define IA32_VMX_EPT_FAULT_WAS_EXECABLE (1ULL << 5)
1430 
1431 #define IA32_VMX_MSR_LIST_SIZE_MASK	(7ULL << 25)
1432 #define IA32_VMX_CR3_TGT_SIZE_MASK	(0x1FFULL << 16)
1433 
1434 #define VMX_SKIP_L1D_FLUSH		2
1435 #define VMX_L1D_FLUSH_SIZE		(64 * 1024)
1436 
1437 /*
1438  * SVM
1439  */
1440 #define MSR_AMD_VM_CR			0xc0010114
1441 #define MSR_AMD_VM_HSAVE_PA		0xc0010117
1442 #define CPUID_AMD_SVM_CAP		0x8000000A
1443 #define AMD_SVM_NESTED_PAGING_CAP	(1 << 0)
1444 #define AMD_SVM_VMCB_CLEAN_CAP		(1 << 5)
1445 #define AMD_SVM_FLUSH_BY_ASID_CAP	(1 << 6)
1446 #define AMD_SVM_DECODE_ASSIST_CAP	(1 << 7)
1447 #define AMD_SVMDIS			0x10
1448 
1449 #define SVM_TLB_CONTROL_FLUSH_NONE	0
1450 #define SVM_TLB_CONTROL_FLUSH_ALL	1
1451 #define SVM_TLB_CONTROL_FLUSH_ASID	3
1452 #define SVM_TLB_CONTROL_FLUSH_ASID_GLB	7
1453 
1454 #define SVM_CLEANBITS_I			(1 << 0)
1455 #define SVM_CLEANBITS_IOPM		(1 << 1)
1456 #define SVM_CLEANBITS_ASID		(1 << 2)
1457 #define SVM_CLEANBITS_TPR		(1 << 3)
1458 #define SVM_CLEANBITS_NP		(1 << 4)
1459 #define SVM_CLEANBITS_CR		(1 << 5)
1460 #define SVM_CLEANBITS_DR		(1 << 6)
1461 #define SVM_CLEANBITS_DT		(1 << 7)
1462 #define SVM_CLEANBITS_SEG		(1 << 8)
1463 #define SVM_CLEANBITS_CR2		(1 << 9)
1464 #define SVM_CLEANBITS_LBR		(1 << 10)
1465 #define SVM_CLEANBITS_AVIC		(1 << 11)
1466 
1467 #define SVM_CLEANBITS_ALL \
1468 	(SVM_CLEANBITS_I | SVM_CLEANBITS_IOPM | SVM_CLEANBITS_ASID | \
1469 	 SVM_CLEANBITS_TPR | SVM_CLEANBITS_NP | SVM_CLEANBITS_CR | \
1470 	 SVM_CLEANBITS_DR | SVM_CLEANBITS_DT | SVM_CLEANBITS_SEG | \
1471 	 SVM_CLEANBITS_CR2 | SVM_CLEANBITS_LBR | SVM_CLEANBITS_AVIC )
1472 
1473 #define SVM_INTR_MISC_V_IGN_TPR 0x10
1474 
1475 /*
1476  * SVM : VMCB intercepts
1477  */
1478 #define SVM_INTERCEPT_CR0_READ		(1UL << 0)
1479 #define SVM_INTERCEPT_CR1_READ		(1UL << 1)
1480 #define SVM_INTERCEPT_CR2_READ		(1UL << 2)
1481 #define SVM_INTERCEPT_CR3_READ		(1UL << 2)
1482 #define SVM_INTERCEPT_CR4_READ		(1UL << 4)
1483 #define SVM_INTERCEPT_CR5_READ		(1UL << 5)
1484 #define SVM_INTERCEPT_CR6_READ		(1UL << 6)
1485 #define SVM_INTERCEPT_CR7_READ		(1UL << 7)
1486 #define SVM_INTERCEPT_CR8_READ		(1UL << 8)
1487 #define SVM_INTERCEPT_CR9_READ		(1UL << 9)
1488 #define SVM_INTERCEPT_CR10_READ		(1UL << 10)
1489 #define SVM_INTERCEPT_CR11_READ		(1UL << 11)
1490 #define SVM_INTERCEPT_CR12_READ		(1UL << 12)
1491 #define SVM_INTERCEPT_CR13_READ		(1UL << 13)
1492 #define SVM_INTERCEPT_CR14_READ		(1UL << 14)
1493 #define SVM_INTERCEPT_CR15_READ		(1UL << 15)
1494 #define SVM_INTERCEPT_CR0_WRITE		(1UL << 16)
1495 #define SVM_INTERCEPT_CR1_WRITE		(1UL << 17)
1496 #define SVM_INTERCEPT_CR2_WRITE		(1UL << 18)
1497 #define SVM_INTERCEPT_CR3_WRITE		(1UL << 19)
1498 #define SVM_INTERCEPT_CR4_WRITE		(1UL << 20)
1499 #define SVM_INTERCEPT_CR5_WRITE		(1UL << 21)
1500 #define SVM_INTERCEPT_CR6_WRITE		(1UL << 22)
1501 #define SVM_INTERCEPT_CR7_WRITE		(1UL << 23)
1502 #define SVM_INTERCEPT_CR8_WRITE		(1UL << 24)
1503 #define SVM_INTERCEPT_CR9_WRITE		(1UL << 25)
1504 #define SVM_INTERCEPT_CR10_WRITE	(1UL << 26)
1505 #define SVM_INTERCEPT_CR11_WRITE	(1UL << 27)
1506 #define SVM_INTERCEPT_CR12_WRITE	(1UL << 28)
1507 #define SVM_INTERCEPT_CR13_WRITE	(1UL << 29)
1508 #define SVM_INTERCEPT_CR14_WRITE	(1UL << 30)
1509 #define SVM_INTERCEPT_CR15_WRITE	(1UL << 31)
1510 #define SVM_INTERCEPT_DR0_READ		(1UL << 0)
1511 #define SVM_INTERCEPT_DR1_READ		(1UL << 1)
1512 #define SVM_INTERCEPT_DR2_READ		(1UL << 2)
1513 #define SVM_INTERCEPT_DR3_READ		(1UL << 2)
1514 #define SVM_INTERCEPT_DR4_READ		(1UL << 4)
1515 #define SVM_INTERCEPT_DR5_READ		(1UL << 5)
1516 #define SVM_INTERCEPT_DR6_READ		(1UL << 6)
1517 #define SVM_INTERCEPT_DR7_READ		(1UL << 7)
1518 #define SVM_INTERCEPT_DR8_READ		(1UL << 8)
1519 #define SVM_INTERCEPT_DR9_READ		(1UL << 9)
1520 #define SVM_INTERCEPT_DR10_READ		(1UL << 10)
1521 #define SVM_INTERCEPT_DR11_READ		(1UL << 11)
1522 #define SVM_INTERCEPT_DR12_READ		(1UL << 12)
1523 #define SVM_INTERCEPT_DR13_READ		(1UL << 13)
1524 #define SVM_INTERCEPT_DR14_READ		(1UL << 14)
1525 #define SVM_INTERCEPT_DR15_READ		(1UL << 15)
1526 #define SVM_INTERCEPT_DR0_WRITE		(1UL << 16)
1527 #define SVM_INTERCEPT_DR1_WRITE		(1UL << 17)
1528 #define SVM_INTERCEPT_DR2_WRITE		(1UL << 18)
1529 #define SVM_INTERCEPT_DR3_WRITE		(1UL << 19)
1530 #define SVM_INTERCEPT_DR4_WRITE		(1UL << 20)
1531 #define SVM_INTERCEPT_DR5_WRITE		(1UL << 21)
1532 #define SVM_INTERCEPT_DR6_WRITE		(1UL << 22)
1533 #define SVM_INTERCEPT_DR7_WRITE		(1UL << 23)
1534 #define SVM_INTERCEPT_DR8_WRITE		(1UL << 24)
1535 #define SVM_INTERCEPT_DR9_WRITE		(1UL << 25)
1536 #define SVM_INTERCEPT_DR10_WRITE	(1UL << 26)
1537 #define SVM_INTERCEPT_DR11_WRITE	(1UL << 27)
1538 #define SVM_INTERCEPT_DR12_WRITE	(1UL << 28)
1539 #define SVM_INTERCEPT_DR13_WRITE	(1UL << 29)
1540 #define SVM_INTERCEPT_DR14_WRITE	(1UL << 30)
1541 #define SVM_INTERCEPT_DR15_WRITE	(1UL << 31)
1542 #define SVM_INTERCEPT_INTR		(1UL << 0)
1543 #define SVM_INTERCEPT_NMI		(1UL << 1)
1544 #define SVM_INTERCEPT_SMI		(1UL << 2)
1545 #define SVM_INTERCEPT_INIT		(1UL << 3)
1546 #define SVM_INTERCEPT_VINTR		(1UL << 4)
1547 #define SVM_INTERCEPT_CR0_SEL_WRITE	(1UL << 5)
1548 #define SVM_INTERCEPT_IDTR_READ		(1UL << 6)
1549 #define SVM_INTERCEPT_GDTR_READ		(1UL << 7)
1550 #define SVM_INTERCEPT_LDTR_READ		(1UL << 8)
1551 #define SVM_INTERCEPT_TR_READ		(1UL << 9)
1552 #define SVM_INTERCEPT_IDTR_WRITE	(1UL << 10)
1553 #define SVM_INTERCEPT_GDTR_WRITE	(1UL << 11)
1554 #define SVM_INTERCEPT_LDTR_WRITE	(1UL << 12)
1555 #define SVM_INTERCEPT_TR_WRITE		(1UL << 13)
1556 #define SVM_INTERCEPT_RDTSC		(1UL << 14)
1557 #define SVM_INTERCEPT_RDPMC		(1UL << 15)
1558 #define SVM_INTERCEPT_PUSHF		(1UL << 16)
1559 #define SVM_INTERCEPT_POPF		(1UL << 17)
1560 #define SVM_INTERCEPT_CPUID		(1UL << 18)
1561 #define SVM_INTERCEPT_RSM		(1UL << 19)
1562 #define SVM_INTERCEPT_IRET		(1UL << 20)
1563 #define SVM_INTERCEPT_INTN		(1UL << 21)
1564 #define SVM_INTERCEPT_INVD		(1UL << 22)
1565 #define SVM_INTERCEPT_PAUSE		(1UL << 23)
1566 #define SVM_INTERCEPT_HLT		(1UL << 24)
1567 #define SVM_INTERCEPT_INVLPG		(1UL << 25)
1568 #define SVM_INTERCEPT_INVLPGA		(1UL << 26)
1569 #define SVM_INTERCEPT_INOUT		(1UL << 27)
1570 #define SVM_INTERCEPT_MSR		(1UL << 28)
1571 #define SVM_INTERCEPT_TASK_SWITCH	(1UL << 29)
1572 #define SVM_INTERCEPT_FERR_FREEZE	(1UL << 30)
1573 #define SVM_INTERCEPT_SHUTDOWN		(1UL << 31)
1574 #define SVM_INTERCEPT_VMRUN		(1UL << 0)
1575 #define SVM_INTERCEPT_VMMCALL		(1UL << 1)
1576 #define SVM_INTERCEPT_VMLOAD		(1UL << 2)
1577 #define SVM_INTERCEPT_VMSAVE		(1UL << 3)
1578 #define SVM_INTERCEPT_STGI		(1UL << 4)
1579 #define SVM_INTERCEPT_CLGI		(1UL << 5)
1580 #define SVM_INTERCEPT_SKINIT		(1UL << 6)
1581 #define SVM_INTERCEPT_RDTSCP		(1UL << 7)
1582 #define SVM_INTERCEPT_ICEBP		(1UL << 8)
1583 #define SVM_INTERCEPT_WBINVD		(1UL << 9)
1584 #define SVM_INTERCEPT_MONITOR		(1UL << 10)
1585 #define SVM_INTERCEPT_MWAIT_UNCOND	(1UL << 11)
1586 #define SVM_INTERCEPT_MWAIT_COND	(1UL << 12)
1587 #define SVM_INTERCEPT_XSETBV		(1UL << 13)
1588 #define SVM_INTERCEPT_EFER_WRITE	(1UL << 15)
1589 #define SVM_INTERCEPT_CR0_WRITE_POST	(1UL << 16)
1590 #define SVM_INTERCEPT_CR1_WRITE_POST	(1UL << 17)
1591 #define SVM_INTERCEPT_CR2_WRITE_POST	(1UL << 18)
1592 #define SVM_INTERCEPT_CR3_WRITE_POST	(1UL << 19)
1593 #define SVM_INTERCEPT_CR4_WRITE_POST	(1UL << 20)
1594 #define SVM_INTERCEPT_CR5_WRITE_POST	(1UL << 21)
1595 #define SVM_INTERCEPT_CR6_WRITE_POST	(1UL << 22)
1596 #define SVM_INTERCEPT_CR7_WRITE_POST	(1UL << 23)
1597 #define SVM_INTERCEPT_CR8_WRITE_POST	(1UL << 24)
1598 #define SVM_INTERCEPT_CR9_WRITE_POST	(1UL << 25)
1599 #define SVM_INTERCEPT_CR10_WRITE_POST	(1UL << 26)
1600 #define SVM_INTERCEPT_CR11_WRITE_POST	(1UL << 27)
1601 #define SVM_INTERCEPT_CR12_WRITE_POST	(1UL << 28)
1602 #define SVM_INTERCEPT_CR13_WRITE_POST	(1UL << 29)
1603 #define SVM_INTERCEPT_CR14_WRITE_POST	(1UL << 30)
1604 #define SVM_INTERCEPT_CR15_WRITE_POST	(1UL << 31)
1605 
1606 /*
1607  * SME and SEV
1608  */
1609 #define CPUID_AMD_SEV_CAP		0x8000001F
1610 #define AMD_SME_CAP			(1UL << 0)
1611 #define AMD_SEV_CAP			(1UL << 1)
1612 
1613 /*
1614  * PAT
1615  */
1616 #define PATENTRY(n, type)       (type << ((n) * 8))
1617 #define PAT_UC          0x0UL
1618 #define PAT_WC          0x1UL
1619 #define PAT_WT          0x4UL
1620 #define PAT_WP          0x5UL
1621 #define PAT_WB          0x6UL
1622 #define PAT_UCMINUS     0x7UL
1623 
1624 /*
1625  * XSAVE subfeatures (cpuid 0xd, leaf 1)
1626  */
1627 #define XSAVE_XSAVEOPT		0x01UL
1628 #define XSAVE_XSAVEC		0x02UL
1629 #define XSAVE_XGETBV1		0x04UL
1630 #define XSAVE_XSAVES		0x08UL
1631 #define XSAVE_XFD		0x10UL
1632 #define XSAVE_BITS \
1633     ("\20" "\01XSAVEOPT" "\02XSAVEC" "\03XGETBV1" "\04XSAVES" "\05XFD" )
1634 
1635 /*
1636  * Default cr0 and cr4 flags.
1637  */
1638 #define CR0_DEFAULT	(CR0_PE|CR0_PG|CR0_NE|CR0_WP)
1639 #define CR4_DEFAULT	(CR4_PAE|CR4_PGE|CR4_PSE|CR4_OSFXSR|CR4_OSXMMEXCPT)
1640