1 /* 2 * Copyright (C) 2007 VMware, Inc. All rights reserved. 3 * 4 * The contents of this file are subject to the terms of the Common 5 * Development and Distribution License (the "License") version 1.0 6 * and no later version. You may not use this file except in 7 * compliance with the License. 8 * 9 * You can obtain a copy of the License at 10 * http://www.opensource.org/licenses/cddl1.php 11 * 12 * See the License for the specific language governing permissions 13 * and limitations under the License. 14 */ 15 16 /* 17 * vmxnet3_defs.h -- 18 * 19 * Definitions shared by device emulation and guest drivers for 20 * VMXNET3 NIC 21 */ 22 23 #ifndef _VMXNET3_DEFS_H_ 24 #define _VMXNET3_DEFS_H_ 25 26 #include <upt1_defs.h> 27 28 /* all registers are 32 bit wide */ 29 /* BAR 1 */ 30 #define VMXNET3_REG_VRRS 0x0 /* Vmxnet3 Revision Report Selection */ 31 #define VMXNET3_REG_UVRS 0x8 /* UPT Version Report Selection */ 32 #define VMXNET3_REG_DSAL 0x10 /* Driver Shared Address Low */ 33 #define VMXNET3_REG_DSAH 0x18 /* Driver Shared Address High */ 34 #define VMXNET3_REG_CMD 0x20 /* Command */ 35 #define VMXNET3_REG_MACL 0x28 /* MAC Address Low */ 36 #define VMXNET3_REG_MACH 0x30 /* MAC Address High */ 37 #define VMXNET3_REG_ICR 0x38 /* Interrupt Cause Register */ 38 #define VMXNET3_REG_ECR 0x40 /* Event Cause Register */ 39 40 #define VMXNET3_REG_WSAL 0xF00 /* Wireless Shared Address Lo */ 41 #define VMXNET3_REG_WSAH 0xF08 /* Wireless Shared Address Hi */ 42 #define VMXNET3_REG_WCMD 0xF18 /* Wireless Command */ 43 44 /* BAR 0 */ 45 #define VMXNET3_REG_IMR 0x0 /* Interrupt Mask Register */ 46 #define VMXNET3_REG_TXPROD 0x600 /* Tx Producer Index */ 47 #define VMXNET3_REG_RXPROD 0x800 /* Rx Producer Index for ring 1 */ 48 #define VMXNET3_REG_RXPROD2 0xA00 /* Rx Producer Index for ring 2 */ 49 50 #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ 51 #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ 52 53 /* 54 * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at 55 * offset 14h) as well as the MSI-X BAR are combined into one PhysMem region: 56 * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE--> 57 * ------------------------------------------------------------------------- 58 * |Pass Thru Registers | Virtual Dev Registers | MSI-X Vector/PBA Table | 59 * ------------------------------------------------------------------------- 60 * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h" 61 */ 62 #define VMXNET3_PHYSMEM_PAGES 4 63 64 #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ 65 #define VMXNET3_REG_ALIGN_MASK 0x7 66 67 /* I/O Mapped access to registers */ 68 #define VMXNET3_IO_TYPE_PT 0 69 #define VMXNET3_IO_TYPE_VD 1 70 #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) 71 #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) 72 #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) 73 74 /* 75 * The Sun Studio compiler complains if enums overflow INT_MAX, so we can only 76 * use an enum with gcc. We keep this here for the convenience of merging 77 * from upstream. 78 */ 79 #ifdef __GNUC__ 80 81 typedef enum { 82 VMXNET3_CMD_FIRST_SET = 0xCAFE0000, 83 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, 84 VMXNET3_CMD_QUIESCE_DEV, 85 VMXNET3_CMD_RESET_DEV, 86 VMXNET3_CMD_UPDATE_RX_MODE, 87 VMXNET3_CMD_UPDATE_MAC_FILTERS, 88 VMXNET3_CMD_UPDATE_VLAN_FILTERS, 89 VMXNET3_CMD_UPDATE_RSSIDT, 90 VMXNET3_CMD_UPDATE_IML, 91 VMXNET3_CMD_UPDATE_PMCFG, 92 VMXNET3_CMD_UPDATE_FEATURE, 93 VMXNET3_CMD_STOP_EMULATION, 94 VMXNET3_CMD_LOAD_PLUGIN, 95 VMXNET3_CMD_ACTIVATE_VF, 96 97 VMXNET3_CMD_FIRST_GET = 0xF00D0000, 98 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, 99 VMXNET3_CMD_GET_STATS, 100 VMXNET3_CMD_GET_LINK, 101 VMXNET3_CMD_GET_PERM_MAC_LO, 102 VMXNET3_CMD_GET_PERM_MAC_HI, 103 VMXNET3_CMD_GET_DID_LO, 104 VMXNET3_CMD_GET_DID_HI, 105 VMXNET3_CMD_GET_DEV_EXTRA_INFO, 106 VMXNET3_CMD_GET_CONF_INTR, 107 VMXNET3_CMD_GET_ADAPTIVE_RING_INFO 108 } Vmxnet3_Cmd; 109 110 #else 111 112 #define VMXNET3_CMD_FIRST_SET 0xCAFE0000U 113 #define VMXNET3_CMD_ACTIVATE_DEV VMXNET3_CMD_FIRST_SET 114 #define VMXNET3_CMD_QUIESCE_DEV (VMXNET3_CMD_FIRST_SET + 1) 115 #define VMXNET3_CMD_RESET_DEV (VMXNET3_CMD_FIRST_SET + 2) 116 #define VMXNET3_CMD_UPDATE_RX_MODE (VMXNET3_CMD_FIRST_SET + 3) 117 #define VMXNET3_CMD_UPDATE_MAC_FILTERS (VMXNET3_CMD_FIRST_SET + 4) 118 #define VMXNET3_CMD_UPDATE_VLAN_FILTERS (VMXNET3_CMD_FIRST_SET + 5) 119 #define VMXNET3_CMD_UPDATE_RSSIDT (VMXNET3_CMD_FIRST_SET + 6) 120 #define VMXNET3_CMD_UPDATE_IML (VMXNET3_CMD_FIRST_SET + 7) 121 #define VMXNET3_CMD_UPDATE_PMCFG (VMXNET3_CMD_FIRST_SET + 8) 122 #define VMXNET3_CMD_UPDATE_FEATURE (VMXNET3_CMD_FIRST_SET + 9) 123 #define VMXNET3_CMD_STOP_EMULATION (VMXNET3_CMD_FIRST_SET + 10) 124 #define VMXNET3_CMD_LOAD_PLUGIN (VMXNET3_CMD_FIRST_SET + 11) 125 #define VMXNET3_CMD_ACTIVATE_VF (VMXNET3_CMD_FIRST_SET + 12) 126 127 #define VMXNET3_CMD_FIRST_GET 0xF00D0000U 128 #define VMXNET3_CMD_GET_QUEUE_STATUS VMXNET3_CMD_FIRST_GET 129 #define VMXNET3_CMD_GET_STATS (VMXNET3_CMD_FIRST_GET + 1) 130 #define VMXNET3_CMD_GET_LINK (VMXNET3_CMD_FIRST_GET + 2) 131 #define VMXNET3_CMD_GET_PERM_MAC_LO (VMXNET3_CMD_FIRST_GET + 3) 132 #define VMXNET3_CMD_GET_PERM_MAC_HI (VMXNET3_CMD_FIRST_GET + 4) 133 #define VMXNET3_CMD_GET_DID_LO (VMXNET3_CMD_FIRST_GET + 5) 134 #define VMXNET3_CMD_GET_DID_HI (VMXNET3_CMD_FIRST_GET + 6) 135 #define VMXNET3_CMD_GET_DEV_EXTRA_INFO (VMXNET3_CMD_FIRST_GET + 7) 136 #define VMXNET3_CMD_GET_CONF_INTR (VMXNET3_CMD_FIRST_GET + 8) 137 #define VMXNET3_CMD_GET_ADAPTIVE_RING_INFO (VMXNET3_CMD_FIRST_GET + 9) 138 139 #endif 140 141 /* Adaptive Ring Info Flags */ 142 #define VMXNET3_DISABLE_ADAPTIVE_RING 1 143 144 #pragma pack(1) 145 typedef struct Vmxnet3_TxDesc { 146 uint64_t addr; 147 uint32_t len:14; 148 uint32_t gen:1; /* generation bit */ 149 uint32_t rsvd:1; 150 uint32_t dtype:1; /* descriptor type */ 151 uint32_t ext1:1; 152 uint32_t msscof:14; /* MSS, checksum offset, flags */ 153 uint32_t hlen:10; /* header len */ 154 uint32_t om:2; /* offload mode */ 155 uint32_t eop:1; /* End Of Packet */ 156 uint32_t cq:1; /* completion request */ 157 uint32_t ext2:1; 158 uint32_t ti:1; /* VLAN Tag Insertion */ 159 uint32_t tci:16; /* Tag to Insert */ 160 } Vmxnet3_TxDesc; 161 #pragma pack() 162 163 /* TxDesc.OM values */ 164 #define VMXNET3_OM_NONE 0 165 #define VMXNET3_OM_CSUM 2 166 #define VMXNET3_OM_TSO 3 167 168 /* fields in TxDesc we access w/o using bit fields */ 169 #define VMXNET3_TXD_EOP_SHIFT 12 170 #define VMXNET3_TXD_CQ_SHIFT 13 171 #define VMXNET3_TXD_GEN_SHIFT 14 172 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 173 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 174 175 #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) 176 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) 177 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) 178 179 #define VMXNET3_TXD_GEN_SIZE 1 180 #define VMXNET3_TXD_EOP_SIZE 1 181 182 #define VMXNET3_HDR_COPY_SIZE 128 183 184 #pragma pack(1) 185 typedef struct Vmxnet3_TxDataDesc { 186 uint8_t data[VMXNET3_HDR_COPY_SIZE]; 187 } Vmxnet3_TxDataDesc; 188 #pragma pack() 189 190 #define VMXNET3_TCD_GEN_SHIFT 31 191 #define VMXNET3_TCD_GEN_SIZE 1 192 #define VMXNET3_TCD_TXIDX_SHIFT 0 193 #define VMXNET3_TCD_TXIDX_SIZE 12 194 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 195 196 #pragma pack(1) 197 typedef struct Vmxnet3_TxCompDesc { 198 uint32_t txdIdx:12; /* Index of the EOP TxDesc */ 199 uint32_t ext1:20; 200 201 uint32_t ext2; 202 uint32_t ext3; 203 204 uint32_t rsvd:24; 205 uint32_t type:7; /* completion type */ 206 uint32_t gen:1; /* generation bit */ 207 } Vmxnet3_TxCompDesc; 208 #pragma pack() 209 210 #pragma pack(1) 211 typedef struct Vmxnet3_RxDesc { 212 uint64_t addr; 213 uint32_t len:14; 214 uint32_t btype:1; /* Buffer Type */ 215 uint32_t dtype:1; /* Descriptor type */ 216 uint32_t rsvd:15; 217 uint32_t gen:1; /* Generation bit */ 218 uint32_t ext1; 219 } Vmxnet3_RxDesc; 220 #pragma pack() 221 222 /* values of RXD.BTYPE */ 223 #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ 224 #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ 225 226 /* fields in RxDesc we access w/o using bit fields */ 227 #define VMXNET3_RXD_BTYPE_SHIFT 14 228 #define VMXNET3_RXD_GEN_SHIFT 31 229 230 #pragma pack(1) 231 typedef struct Vmxnet3_RxCompDesc { 232 uint32_t rxdIdx:12; /* Index of the RxDesc */ 233 uint32_t ext1:2; 234 uint32_t eop:1; /* End of Packet */ 235 uint32_t sop:1; /* Start of Packet */ 236 uint32_t rqID:10; /* rx queue/ring ID */ 237 uint32_t rssType:4; /* RSS hash type used */ 238 uint32_t cnc:1; /* Checksum Not Calculated */ 239 uint32_t ext2:1; 240 uint32_t rssHash; /* RSS hash value */ 241 uint32_t len:14; /* data length */ 242 uint32_t err:1; /* Error */ 243 uint32_t ts:1; /* Tag is stripped */ 244 uint32_t tci:16; /* Tag stripped */ 245 uint32_t csum:16; 246 uint32_t tuc:1; /* TCP/UDP Checksum Correct */ 247 uint32_t udp:1; /* UDP packet */ 248 uint32_t tcp:1; /* TCP packet */ 249 uint32_t ipc:1; /* IP Checksum Correct */ 250 uint32_t v6:1; /* IPv6 */ 251 uint32_t v4:1; /* IPv4 */ 252 uint32_t frg:1; /* IP Fragment */ 253 uint32_t fcs:1; /* Frame CRC correct */ 254 uint32_t type:7; /* completion type */ 255 uint32_t gen:1; /* generation bit */ 256 } Vmxnet3_RxCompDesc; 257 #pragma pack() 258 259 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ 260 #define VMXNET3_RCD_TUC_SHIFT 16 261 #define VMXNET3_RCD_IPC_SHIFT 19 262 263 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ 264 #define VMXNET3_RCD_TYPE_SHIFT 56 265 #define VMXNET3_RCD_GEN_SHIFT 63 266 267 /* csum OK for TCP/UDP pkts over IP */ 268 #define VMXNET3_RCD_CSUM_OK \ 269 (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT) 270 271 /* value of RxCompDesc.rssType */ 272 #define VMXNET3_RCD_RSS_TYPE_NONE 0 273 #define VMXNET3_RCD_RSS_TYPE_IPV4 1 274 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4 2 275 #define VMXNET3_RCD_RSS_TYPE_IPV6 3 276 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6 4 277 278 /* a union for accessing all cmd/completion descriptors */ 279 typedef union Vmxnet3_GenericDesc { 280 uint64_t qword[2]; 281 uint32_t dword[4]; 282 uint16_t word[8]; 283 Vmxnet3_TxDesc txd; 284 Vmxnet3_RxDesc rxd; 285 Vmxnet3_TxCompDesc tcd; 286 Vmxnet3_RxCompDesc rcd; 287 } Vmxnet3_GenericDesc; 288 289 #define VMXNET3_INIT_GEN 1 290 291 /* Max size of a single tx buffer */ 292 #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) 293 294 /* # of tx desc needed for a tx buffer size */ 295 #define VMXNET3_TXD_NEEDED(size) \ 296 (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE) 297 298 /* max # of tx descs for a non-tso pkt */ 299 #define VMXNET3_MAX_TXD_PER_PKT 16 300 301 /* Max size of a single rx buffer */ 302 #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) 303 /* Minimum size of a type 0 buffer */ 304 #define VMXNET3_MIN_T0_BUF_SIZE 128 305 #define VMXNET3_MAX_CSUM_OFFSET 1024 306 307 /* Ring base address alignment */ 308 #define VMXNET3_RING_BA_ALIGN 512 309 #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) 310 311 /* Ring size must be a multiple of 32 */ 312 #define VMXNET3_RING_SIZE_ALIGN 32 313 #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) 314 315 /* Max ring size */ 316 #define VMXNET3_TX_RING_MAX_SIZE 4096 317 #define VMXNET3_TC_RING_MAX_SIZE 4096 318 #define VMXNET3_RX_RING_MAX_SIZE 4096 319 #define VMXNET3_RC_RING_MAX_SIZE 8192 320 321 /* a list of reasons for queue stop */ 322 323 #define VMXNET3_ERR_NOEOP 0x80000000 /* cannot find the */ 324 /* EOP desc of a pkt */ 325 #define VMXNET3_ERR_TXD_REUSE 0x80000001 /* reuse a TxDesc before tx */ 326 /* completion */ 327 #define VMXNET3_ERR_BIG_PKT 0x80000002 /* too many TxDesc for a pkt */ 328 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003 /* descriptor type not */ 329 /* supported */ 330 #define VMXNET3_ERR_SMALL_BUF 0x80000004 /* type 0 buffer too small */ 331 #define VMXNET3_ERR_STRESS 0x80000005 /* stress option firing */ 332 /* in vmkernel */ 333 #define VMXNET3_ERR_SWITCH 0x80000006 /* mode switch failure */ 334 #define VMXNET3_ERR_TXD_INVALID 0x80000007 /* invalid TxDesc */ 335 336 /* completion descriptor types */ 337 #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ 338 #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ 339 340 #define VMXNET3_GOS_BITS_UNK 0 /* unknown */ 341 #define VMXNET3_GOS_BITS_32 1 342 #define VMXNET3_GOS_BITS_64 2 343 344 #define VMXNET3_GOS_TYPE_UNK 0 /* unknown */ 345 #define VMXNET3_GOS_TYPE_LINUX 1 346 #define VMXNET3_GOS_TYPE_WIN 2 347 #define VMXNET3_GOS_TYPE_SOLARIS 3 348 #define VMXNET3_GOS_TYPE_FREEBSD 4 349 #define VMXNET3_GOS_TYPE_PXE 5 350 351 /* All structures in DriverShared are padded to multiples of 8 bytes */ 352 353 #pragma pack(1) 354 typedef struct Vmxnet3_GOSInfo { 355 uint32_t gosBits: 2; /* 32-bit or 64-bit? */ 356 uint32_t gosType: 4; /* which guest */ 357 uint32_t gosVer: 16; /* gos version */ 358 uint32_t gosMisc: 10; /* other info about gos */ 359 } Vmxnet3_GOSInfo; 360 #pragma pack() 361 362 #pragma pack(1) 363 typedef struct Vmxnet3_DriverInfo { 364 uint32_t version; /* driver version */ 365 Vmxnet3_GOSInfo gos; 366 uint32_t vmxnet3RevSpt; /* vmxnet3 revision supported */ 367 uint32_t uptVerSpt; /* upt version supported */ 368 } Vmxnet3_DriverInfo; 369 #pragma pack() 370 371 #define VMXNET3_REV1_MAGIC 0xbabefee1 372 373 /* 374 * QueueDescPA must be 128 bytes aligned. It points to an array of 375 * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. 376 * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by 377 * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. 378 */ 379 #define VMXNET3_QUEUE_DESC_ALIGN 128 380 381 #pragma pack(1) 382 typedef struct Vmxnet3_MiscConf { 383 Vmxnet3_DriverInfo driverInfo; 384 uint64_t uptFeatures; 385 uint64_t ddPA; /* driver data PA */ 386 uint64_t queueDescPA; /* queue descriptor table PA */ 387 uint32_t ddLen; /* driver data len */ 388 uint32_t queueDescLen; /* queue descriptor table len, bytes */ 389 uint32_t mtu; 390 uint16_t maxNumRxSG; 391 uint8_t numTxQueues; 392 uint8_t numRxQueues; 393 uint32_t reserved[4]; 394 } Vmxnet3_MiscConf; 395 #pragma pack() 396 397 #pragma pack(1) 398 typedef struct Vmxnet3_TxQueueConf { 399 uint64_t txRingBasePA; 400 uint64_t dataRingBasePA; 401 uint64_t compRingBasePA; 402 uint64_t ddPA; /* driver data */ 403 uint64_t reserved; 404 uint32_t txRingSize; /* # of tx desc */ 405 uint32_t dataRingSize; /* # of data desc */ 406 uint32_t compRingSize; /* # of comp desc */ 407 uint32_t ddLen; /* size of driver data */ 408 uint8_t intrIdx; 409 uint8_t _pad[7]; 410 } Vmxnet3_TxQueueConf; 411 #pragma pack() 412 413 #pragma pack(1) 414 typedef struct Vmxnet3_RxQueueConf { 415 uint64_t rxRingBasePA[2]; 416 uint64_t compRingBasePA; 417 uint64_t ddPA; /* driver data */ 418 uint64_t reserved; 419 uint32_t rxRingSize[2]; /* # of rx desc */ 420 uint32_t compRingSize; /* # of rx comp desc */ 421 uint32_t ddLen; /* size of driver data */ 422 uint8_t intrIdx; 423 uint8_t _pad[7]; 424 } Vmxnet3_RxQueueConf; 425 #pragma pack() 426 427 enum vmxnet3_intr_mask_mode { 428 VMXNET3_IMM_AUTO = 0, 429 VMXNET3_IMM_ACTIVE = 1, 430 VMXNET3_IMM_LAZY = 2 431 }; 432 433 enum vmxnet3_intr_type { 434 VMXNET3_IT_AUTO = 0, 435 VMXNET3_IT_INTX = 1, 436 VMXNET3_IT_MSI = 2, 437 VMXNET3_IT_MSIX = 3 438 }; 439 440 #define VMXNET3_MAX_TX_QUEUES 8 441 #define VMXNET3_MAX_RX_QUEUES 16 442 /* addition 1 for events */ 443 #define VMXNET3_MAX_INTRS 25 444 445 /* value of intrCtrl */ 446 #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ 447 448 #pragma pack(1) 449 typedef struct Vmxnet3_IntrConf { 450 char autoMask; 451 uint8_t numIntrs; /* # of interrupts */ 452 uint8_t eventIntrIdx; 453 uint8_t modLevels[VMXNET3_MAX_INTRS]; /* moderation level */ 454 /* for each intr */ 455 uint32_t intrCtrl; 456 uint32_t reserved[2]; 457 } Vmxnet3_IntrConf; 458 #pragma pack() 459 460 /* one bit per VLAN ID, the size is in the units of uint32_t */ 461 #define VMXNET3_VFT_SIZE (4096 / (sizeof (uint32_t) * 8)) 462 463 #pragma pack(1) 464 typedef struct Vmxnet3_QueueStatus { 465 char stopped; 466 uint8_t _pad[3]; 467 uint32_t error; 468 } Vmxnet3_QueueStatus; 469 #pragma pack() 470 471 #pragma pack(1) 472 typedef struct Vmxnet3_TxQueueCtrl { 473 uint32_t txNumDeferred; 474 uint32_t txThreshold; 475 uint64_t reserved; 476 } Vmxnet3_TxQueueCtrl; 477 #pragma pack() 478 479 #pragma pack(1) 480 typedef struct Vmxnet3_RxQueueCtrl { 481 char updateRxProd; 482 uint8_t _pad[7]; 483 uint64_t reserved; 484 } Vmxnet3_RxQueueCtrl; 485 #pragma pack() 486 487 #define VMXNET3_RXM_UCAST 0x01 /* unicast only */ 488 #define VMXNET3_RXM_MCAST 0x02 /* multicast passing the filters */ 489 #define VMXNET3_RXM_BCAST 0x04 /* broadcast only */ 490 #define VMXNET3_RXM_ALL_MULTI 0x08 /* all multicast */ 491 #define VMXNET3_RXM_PROMISC 0x10 /* promiscuous */ 492 493 #pragma pack(1) 494 typedef struct Vmxnet3_RxFilterConf { 495 uint32_t rxMode; /* VMXNET3_RXM_xxx */ 496 uint16_t mfTableLen; /* size of the multicast filter table */ 497 uint16_t _pad1; 498 uint64_t mfTablePA; /* PA of the multicast filters table */ 499 uint32_t vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ 500 } Vmxnet3_RxFilterConf; 501 #pragma pack() 502 503 #define VMXNET3_PM_MAX_FILTERS 6 504 #define VMXNET3_PM_MAX_PATTERN_SIZE 128 505 #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) 506 507 #define VMXNET3_PM_WAKEUP_MAGIC 0x01 /* wake up on magic pkts */ 508 #define VMXNET3_PM_WAKEUP_FILTER 0x02 /* wake up on pkts matching */ 509 /* filters */ 510 511 #pragma pack(1) 512 typedef struct Vmxnet3_PM_PktFilter { 513 uint8_t maskSize; 514 uint8_t patternSize; 515 uint8_t mask[VMXNET3_PM_MAX_MASK_SIZE]; 516 uint8_t pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; 517 uint8_t pad[6]; 518 } Vmxnet3_PM_PktFilter; 519 #pragma pack() 520 521 #pragma pack(1) 522 typedef struct Vmxnet3_PMConf { 523 uint16_t wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ 524 uint8_t numFilters; 525 uint8_t pad[5]; 526 Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; 527 } Vmxnet3_PMConf; 528 #pragma pack() 529 530 #pragma pack(1) 531 typedef struct Vmxnet3_VariableLenConfDesc { 532 uint32_t confVer; 533 uint32_t confLen; 534 uint64_t confPA; 535 } Vmxnet3_VariableLenConfDesc; 536 #pragma pack() 537 538 #pragma pack(1) 539 typedef struct Vmxnet3_DSDevRead { 540 /* read-only region for device, read by dev in response to a SET cmd */ 541 Vmxnet3_MiscConf misc; 542 Vmxnet3_IntrConf intrConf; 543 Vmxnet3_RxFilterConf rxFilterConf; 544 Vmxnet3_VariableLenConfDesc rssConfDesc; 545 Vmxnet3_VariableLenConfDesc pmConfDesc; 546 Vmxnet3_VariableLenConfDesc pluginConfDesc; 547 } Vmxnet3_DSDevRead; 548 #pragma pack() 549 550 #pragma pack(1) 551 typedef struct Vmxnet3_TxQueueDesc { 552 Vmxnet3_TxQueueCtrl ctrl; 553 Vmxnet3_TxQueueConf conf; 554 /* Driver read after a GET command */ 555 Vmxnet3_QueueStatus status; 556 UPT1_TxStats stats; 557 uint8_t _pad[88]; /* 128 aligned */ 558 } Vmxnet3_TxQueueDesc; 559 #pragma pack() 560 561 #pragma pack(1) 562 typedef struct Vmxnet3_RxQueueDesc { 563 Vmxnet3_RxQueueCtrl ctrl; 564 Vmxnet3_RxQueueConf conf; 565 /* Driver read after a GET command */ 566 Vmxnet3_QueueStatus status; 567 UPT1_RxStats stats; 568 uint8_t _pad[88]; /* 128 aligned */ 569 } Vmxnet3_RxQueueDesc; 570 #pragma pack() 571 572 #pragma pack(1) 573 typedef struct Vmxnet3_DriverShared { 574 uint32_t magic; 575 uint32_t pad; /* make devRead start at */ 576 /* 64-bit boundaries */ 577 Vmxnet3_DSDevRead devRead; 578 uint32_t ecr; 579 uint32_t reserved[5]; 580 } Vmxnet3_DriverShared; 581 #pragma pack() 582 583 #define VMXNET3_ECR_RQERR (1 << 0) 584 #define VMXNET3_ECR_TQERR (1 << 1) 585 #define VMXNET3_ECR_LINK (1 << 2) 586 #define VMXNET3_ECR_DIC (1 << 3) 587 #define VMXNET3_ECR_DEBUG (1 << 4) 588 589 /* flip the gen bit of a ring */ 590 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) 591 592 /* only use this if moving the idx won't affect the gen bit */ 593 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) { \ 594 (idx)++; \ 595 if (UNLIKELY((idx) == (ring_size))) { \ 596 (idx) = 0; \ 597 } \ 598 } 599 600 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ 601 vfTable[vid >> 5] |= (1 << (vid & 31)) 602 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ 603 vfTable[vid >> 5] &= ~(1 << (vid & 31)) 604 605 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ 606 ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) 607 608 #define VMXNET3_MAX_MTU 9000 609 #define VMXNET3_MIN_MTU 60 610 611 #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ 612 #define VMXNET3_LINK_DOWN 0 613 614 #define VMXWIFI_DRIVER_SHARED_LEN 8192 615 616 #define VMXNET3_DID_PASSTHRU 0xFFFF 617 618 #endif /* _VMXNET3_DEFS_H_ */ 619