1 /** @file 2 Register names for Ver2 PCH PMC device 3 4 Conventions: 5 6 - Register definition format: 7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName 8 - Prefix: 9 Definitions beginning with "R_" are registers 10 Definitions beginning with "B_" are bits within registers 11 Definitions beginning with "V_" are meaningful values within the bits 12 Definitions beginning with "S_" are register size 13 Definitions beginning with "N_" are the bit position 14 - [GenerationName]: 15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). 16 Register name without GenerationName applies to all generations. 17 - [ComponentName]: 18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) 19 Register name without ComponentName applies to all components. 20 Register that is specific to -LP denoted by "_PCH_LP_" in component name. 21 - SubsystemName: 22 This field indicates the subsystem name of the component that the register belongs to 23 (e.g. PCIE, USB, SATA, GPIO, PMC etc.). 24 - RegisterSpace: 25 MEM - MMIO space register of subsystem. 26 IO - IO space register of subsystem. 27 PCR - Private configuration register of subsystem. 28 CFG - PCI configuration space register of subsystem. 29 - RegisterName: 30 Full register name. 31 32 Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> 33 SPDX-License-Identifier: BSD-2-Clause-Patent 34 **/ 35 #ifndef _PCH_REGS_PMC_TGL_H_ 36 #define _PCH_REGS_PMC_TGL_H_ 37 38 // 39 // PWRM Registers 40 // 41 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_B 0x0 42 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_A 0x2 43 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_R 0x3 44 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPD 0x4 45 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_S 0x5 46 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_H 0x6 47 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_D 0x7 48 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_F 0xA 49 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_C 0xB 50 #define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_E 0xC 51 52 #endif // _PCH_REGS_PMC_TGL_H_ 53