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Searched defs:Verilog (Results 1 – 15 of 15) sorted by relevance

/dports/cad/yosys/yosys-yosys-0.12/manual/
H A DCHAPTER_Basics.tex252 \subsection{Structural Verilog}
271 \subsection{Expressions in Verilog}
287 \subsection{Behavioural Modelling}
366 \subsection{Functions and Tasks}
373 \subsection{Conditionals, Loops and Generate-Statements}
393 \subsection{Arrays and Memories}
/dports/www/gitlab-workhorse/gitlab-foss-0a901d60f8ae4a60c04ae82e6e9c3a03e9321417/workhorse/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLexer( var
/dports/devel/gh/cli-2.4.0/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLexer( var
/dports/sysutils/glow/glow-0.2.0/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLexer( var
/dports/sysutils/go-wtf/wtf-0.21.0/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLexer( var
/dports/sysutils/go-wtf/wtf-0.21.0/vendor/github.com/alecthomas/chroma/chroma-0.6.3/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLexer( var
/dports/misc/cheat/cheat-4.2.2/vendor/github.com/alecthomas/chroma/chroma-0.9.1/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLazyLexer( var
/dports/misc/cheat/cheat-4.2.2/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLazyLexer( var
/dports/www/gitea/gitea-1.16.5/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLazyLexer( var
/dports/sysutils/chezmoi/chezmoi-2.9.3/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLazyLexer( var
/dports/www/gohugo/hugo-0.91.2/vendor/github.com/alecthomas/chroma/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLazyLexer( var
/dports/devel/chroma/chroma-0.9.2/lexers/v/
H A Dverilog.go9 var Verilog = internal.Register(MustNewLazyLexer( var
/dports/cad/alliance/alliance/src/vasy/src/
H A Dvasy_drvvex.c335 void VasyDriveVexExpr( File, RtlFigure, Expr, Verilog ) in VasyDriveVexExpr() argument
/dports/devel/tokei/tokei-12.1.2/
H A Dlanguages.json1306 "Verilog": { object
/dports/sysutils/onefetch/onefetch-2.10.2/cargo-crates/tokei-12.1.2/
H A Dlanguages.json1306 "Verilog": { object