Searched defs:WCK (Results 1 – 3 of 3) sorted by relevance
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/ecp5/ |
| H A D | cells_sim.v | 141 input WRE, WCK, port
194 input WCK, port
238 input WCK, WRE, port
439 input WRE, WCK, port
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/machxo2/ |
| H A D | cells_sim.v | 109 input WRE, WCK, port
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| /dports/cad/yosys/yosys-yosys-0.12/techlibs/nexus/ |
| H A D | cells_sim.v | 319 input WCK, WRE, // LUTRAM write clock and enable port
361 input WRE, WCK, port
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