1 /* $OpenBSD: atareg.h,v 1.14 2010/07/23 07:47:13 jsg Exp $ */ 2 /* $NetBSD: atareg.h,v 1.5 1999/01/18 20:06:24 bouyer Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _DEV_ATA_ATAREG_H_ 29 #define _DEV_ATA_ATAREG_H_ 30 31 /* 32 * Drive parameter structure for ATA/ATAPI. 33 * Bit fields: WDC_* : common to ATA/ATAPI 34 * ATA_* : ATA only 35 * ATAPI_* : ATAPI only. 36 */ 37 struct ataparams { 38 /* drive info */ 39 u_int16_t atap_config; /* 0: general configuration */ 40 #define WDC_CFG_ATAPI_MASK 0xc000 41 #define WDC_CFG_ATAPI 0x8000 42 #define ATA_CFG_REMOVABLE 0x0080 43 #define ATA_CFG_FIXED 0x0040 44 #define ATAPI_CFG_TYPE_MASK 0x1f00 45 #define ATAPI_CFG_TYPE(x) (((x) & ATAPI_CFG_TYPE_MASK) >> 8) 46 #define ATAPI_CFG_TYPE_DIRECT 0x00 47 #define ATAPI_CFG_TYPE_SEQUENTIAL 0x01 48 #define ATAPI_CFG_TYPE_CDROM 0x05 49 #define ATAPI_CFG_TYPE_OPTICAL 0x07 50 #define ATAPI_CFG_TYPE_NODEVICE 0x1F 51 #define ATAPI_CFG_REMOV 0x0080 52 #define ATAPI_CFG_DRQ_MASK 0x0060 53 #define ATAPI_CFG_STD_DRQ 0x0000 54 #define ATAPI_CFG_IRQ_DRQ 0x0020 55 #define ATAPI_CFG_ACCEL_DRQ 0x0040 56 #define ATAPI_CFG_CMD_MASK 0x0003 57 #define ATAPI_CFG_CMD_12 0x0000 58 #define ATAPI_CFG_CMD_16 0x0001 59 /* words 1-9 are ATA only */ 60 u_int16_t atap_cylinders; /* 1: # of non-removable cylinders */ 61 u_int16_t __reserved1; 62 u_int16_t atap_heads; /* 3: # of heads */ 63 u_int16_t __retired1[2]; /* 4-5: # of unform. bytes/track */ 64 u_int16_t atap_sectors; /* 6: # of sectors */ 65 u_int16_t __retired2[3]; 66 67 u_int8_t atap_serial[20]; /* 10-19: serial number */ 68 u_int16_t __retired3[2]; 69 u_int16_t __obsolete1; 70 u_int8_t atap_revision[8]; /* 23-26: firmware revision */ 71 u_int8_t atap_model[40]; /* 27-46: model number */ 72 u_int16_t atap_multi; /* 47: maximum sectors per irq (ATA) */ 73 u_int16_t __reserved2; 74 u_int16_t atap_capabilities1; /* 49: capability flags */ 75 #define WDC_CAP_IORDY 0x0800 76 #define WDC_CAP_IORDY_DSBL 0x0400 77 #define WDC_CAP_LBA 0x0200 78 #define WDC_CAP_DMA 0x0100 79 #define ATA_CAP_STBY 0x2000 80 #define ATAPI_CAP_INTERL_DMA 0x8000 81 #define ATAPI_CAP_CMD_QUEUE 0x4000 82 #define ATAPI_CAP_OVERLP 0x2000 83 #define ATAPI_CAP_ATA_RST 0x1000 84 u_int16_t atap_capabilities2; /* 50: capability flags (ATA) */ 85 #if BYTE_ORDER == LITTLE_ENDIAN 86 u_int8_t __junk2; 87 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 88 u_int8_t __junk3; 89 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 90 #else 91 u_int8_t atap_oldpiotiming; /* 51: old PIO timing mode */ 92 u_int8_t __junk2; 93 u_int8_t atap_olddmatiming; /* 52: old DMA timing mode (ATA) */ 94 u_int8_t __junk3; 95 #endif 96 u_int16_t atap_extensions; /* 53: extensions supported */ 97 #define WDC_EXT_UDMA_MODES 0x0004 98 #define WDC_EXT_MODES 0x0002 99 #define WDC_EXT_GEOM 0x0001 100 /* words 54-62 are ATA only */ 101 u_int16_t atap_curcylinders; /* 54: current logical cylinders */ 102 u_int16_t atap_curheads; /* 55: current logical heads */ 103 u_int16_t atap_cursectors; /* 56: current logical sectors/tracks */ 104 u_int16_t atap_curcapacity[2]; /* 57-58: current capacity */ 105 u_int16_t atap_curmulti; /* 59: current multi-sector setting */ 106 #define WDC_MULTI_VALID 0x0100 107 #define WDC_MULTI_MASK 0x00ff 108 u_int16_t atap_capacity[2]; /* 60-61: total capacity (LBA only) */ 109 u_int16_t __retired4; 110 #if BYTE_ORDER == LITTLE_ENDIAN 111 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 112 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 113 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 114 u_int8_t __junk4; 115 #else 116 u_int8_t atap_dmamode_act; /* multiword DMA mode active */ 117 u_int8_t atap_dmamode_supp; /* 63: multiword DMA mode supported */ 118 u_int8_t __junk4; 119 u_int8_t atap_piomode_supp; /* 64: PIO mode supported */ 120 #endif 121 u_int16_t atap_dmatiming_mimi; /* 65: minimum DMA cycle time */ 122 u_int16_t atap_dmatiming_recom; /* 66: recommended DMA cycle time */ 123 u_int16_t atap_piotiming; /* 67: mini PIO cycle time without FC */ 124 u_int16_t atap_piotiming_iordy; /* 68: mini PIO cycle time with IORDY FC */ 125 u_int16_t __reserved3[2]; 126 /* words 71-72 are ATAPI only */ 127 u_int16_t atap_pkt_br; /* 71: time (ns) to bus release */ 128 u_int16_t atap_pkt_bsyclr; /* 72: tme to clear BSY after service */ 129 u_int16_t __reserved4[2]; 130 u_int16_t atap_queuedepth; /* 75: */ 131 #define WDC_QUEUE_DEPTH_MASK 0x1f 132 u_int16_t atap_sata_caps; /* 76: SATA capabilities */ 133 #define SATA_SIGNAL_GEN1 0x0002 /* SATA Gen-1 signaling speed */ 134 #define SATA_SIGNAL_GEN2 0x0004 /* SATA Gen-2 signaling speed */ 135 #define SATA_NATIVE_CMDQ 0x0100 /* native command queuing */ 136 #define SATA_HOST_PWR_MGMT 0x0200 /* power management (host) */ 137 u_int16_t atap_sata_reserved; /* 77: reserved */ 138 u_int16_t atap_sata_features_supp;/* 78: SATA features supported */ 139 #define SATA_NONZERO_OFFSETS 0x0002 /* non-zero buffer offsets */ 140 #define SATA_DMA_SETUP_AUTO 0x0004 /* DMA setup auto-activate */ 141 #define SATA_DRIVE_PWR_MGMT 0x0008 /* power management (device) */ 142 u_int16_t atap_sata_features_en; /* 79: SATA features enabled */ 143 u_int16_t atap_ata_major; /* 80: Major version number */ 144 #define WDC_VER_ATA1 0x0002 145 #define WDC_VER_ATA2 0x0004 146 #define WDC_VER_ATA3 0x0008 147 #define WDC_VER_ATA4 0x0010 148 #define WDC_VER_ATA5 0x0020 149 #define WDC_VER_ATA6 0x0040 150 #define WDC_VER_ATA7 0x0080 151 #define WDC_VER_ATA8 0x0100 152 #define WDC_VER_ATA9 0x0200 153 #define WDC_VER_ATA10 0x0400 154 #define WDC_VER_ATA11 0x0800 155 #define WDC_VER_ATA12 0x1000 156 #define WDC_VER_ATA13 0x2000 157 #define WDC_VER_ATA14 0x4000 158 u_int16_t atap_ata_minor; /* 81: Minor version number */ 159 u_int16_t atap_cmd_set1; /* 82: command set supported */ 160 #define WDC_CMD1_NOP 0x4000 161 #define WDC_CMD1_RB 0x2000 162 #define WDC_CMD1_WB 0x1000 163 #define WDC_CMD1_HPA 0x0400 164 #define WDC_CMD1_DVRST 0x0200 165 #define WDC_CMD1_SRV 0x0100 166 #define WDC_CMD1_RLSE 0x0080 167 #define WDC_CMD1_AHEAD 0x0040 168 #define WDC_CMD1_CACHE 0x0020 169 #define WDC_CMD1_PKT 0x0010 170 #define WDC_CMD1_PM 0x0008 171 #define WDC_CMD1_REMOV 0x0004 172 #define WDC_CMD1_SEC 0x0002 173 #define WDC_CMD1_SMART 0x0001 174 u_int16_t atap_cmd_set2; /* 83: command set supported */ 175 #define ATAPI_CMD2_FCE 0x2000 /* Flush Cache Ext supported */ 176 #define ATAPI_CMD2_FC 0x1000 /* Flush Cache supported */ 177 #define ATAPI_CMD2_DCO 0x0800 /* Device Configuration Overlay supported */ 178 #define ATAPI_CMD2_48AD 0x0400 /* 48bit address supported */ 179 #define ATAPI_CMD2_AAM 0x0200 /* Automatic Acoustic Management supported */ 180 #define ATAPI_CMD2_SM 0x0100 /* Set Max security extension supported */ 181 #define ATAPI_CMD2_SF 0x0040 /* Set Features subcommand required */ 182 #define ATAPI_CMD2_PUIS 0x0020 /* Power up in standby supported */ 183 #define WDC_CMD2_RMSN 0x0010 184 #define ATA_CMD2_APM 0x0008 185 #define ATA_CMD2_CFA 0x0004 186 #define ATA_CMD2_RWQ 0x0002 187 #define WDC_CMD2_DM 0x0001 /* Download Microcode supported */ 188 u_int16_t atap_cmd_ext; /* 84: command/features supp. ext. */ 189 #define ATAPI_CMDE_IIUF 0x2000 /* IDLE IMMEDIATE with UNLOAD FEATURE */ 190 #define ATAPI_CMDE_MSER 0x0004 /* Media serial number supported */ 191 #define ATAPI_CMDE_TEST 0x0002 /* SMART self-test supported */ 192 #define ATAPI_CMDE_SLOG 0x0001 /* SMART error logging supported */ 193 u_int16_t atap_cmd1_en; /* 85: cmd/features enabled */ 194 /* bits are the same as atap_cmd_set1 */ 195 u_int16_t atap_cmd2_en; /* 86: cmd/features enabled */ 196 /* bits are the same as atap_cmd_set2 */ 197 u_int16_t atap_cmd_def; /* 87: cmd/features default */ 198 /* bits are NOT the same as atap_cmd_ext */ 199 #if BYTE_ORDER == LITTLE_ENDIAN 200 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 201 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 202 #else 203 u_int8_t atap_udmamode_act; /* Ultra-DMA mode active */ 204 u_int8_t atap_udmamode_supp; /* 88: Ultra-DMA mode supported */ 205 #endif 206 /* 89-92 are ATA-only */ 207 u_int16_t atap_seu_time; /* 89: Sec. Erase Unit compl. time */ 208 u_int16_t atap_eseu_time; /* 90: Enhanced SEU compl. time */ 209 u_int16_t atap_apm_val; /* 91: current APM value */ 210 u_int16_t atap_mpasswd_rev; /* 92: Master Password revision */ 211 u_int16_t atap_hwreset_res; /* 93: Hardware reset value */ 212 #define ATA_HWRES_CBLID 0x2000 /* CBLID above Vih */ 213 #define ATA_HWRES_D1_PDIAG 0x0800 /* Device 1 PDIAG detect OK */ 214 #define ATA_HWRES_D1_CSEL 0x0400 /* Device 1 used CSEL for address */ 215 #define ATA_HWRES_D1_JUMP 0x0200 /* Device 1 jumpered to address */ 216 #define ATA_HWRES_D0_SEL 0x0040 /* Device 0 responds when Dev 1 selected */ 217 #define ATA_HWRES_D0_DASP 0x0020 /* Device 0 DASP detect OK */ 218 #define ATA_HWRES_D0_PDIAG 0x0010 /* Device 0 PDIAG detect OK */ 219 #define ATA_HWRES_D0_DIAG 0x0008 /* Device 0 diag OK */ 220 #define ATA_HWRES_D0_CSEL 0x0004 /* Device 0 used CSEL for address */ 221 #define ATA_HWRES_D0_JUMP 0x0002 /* Device 0 jumpered to address */ 222 #if BYTE_ORDER == LITTLE_ENDIAN 223 u_int8_t atap_acoustic_val; /* 94: Current acoustic level */ 224 u_int8_t atap_acoustic_def; /* recommended level */ 225 #else 226 u_int8_t atap_acoustic_def; /* recommended level */ 227 u_int8_t atap_acoustic_val; /* 94: Current acoustic level */ 228 #endif 229 u_int16_t __reserved6[5]; /* 95-99: reserved */ 230 u_int16_t atap_max_lba[4]; /* 100-103: Max. user LBA add */ 231 u_int16_t __reserved7[23]; /* 104-126: reserved */ 232 u_int16_t atap_rmsn_supp; /* 127: remov. media status notif. */ 233 #define WDC_RMSN_SUPP_MASK 0x0003 234 #define WDC_RMSN_SUPP 0x0001 235 u_int16_t atap_sec_st; /* 128: security status */ 236 #define WDC_SEC_LEV_MAX 0x0100 237 #define WDC_SEC_ESE_SUPP 0x0020 238 #define WDC_SEC_EXP 0x0010 239 #define WDC_SEC_FROZEN 0x0008 240 #define WDC_SEC_LOCKED 0x0004 241 #define WDC_SEC_EN 0x0002 242 #define WDC_SEC_SUPP 0x0001 243 u_int16_t __reserved8[31]; /* 129-159: vendor specific */ 244 u_int16_t atap_cfa_power; /* 160: CFA powermode */ 245 #define ATAPI_CFA_MAX_MASK 0x0FFF 246 #define ATAPI_CFA_MODE1_DIS 0x1000 /* CFA Mode 1 Disabled */ 247 #define ATAPI_CFA_MODE1_REQ 0x2000 /* CFA Mode 1 Required */ 248 #define ATAPI_CFA_WORD160 0x8000 /* Word 160 supported */ 249 u_int16_t __reserved9[15]; /* 161-175: reserved for CFA */ 250 u_int8_t atap_media_serial[60]; /* 176-205: media serial number */ 251 u_int16_t __reserved10[49]; /* 206-254: reserved */ 252 #if BYTE_ORDER == LITTLE_ENDIAN 253 u_int8_t atap_signature; /* 255: Signature */ 254 u_int8_t atap_checksum; /* Checksum */ 255 #else 256 u_int8_t atap_checksum; /* Checksum */ 257 u_int8_t atap_signature; /* 255: Signature */ 258 #endif 259 }; 260 261 #endif /* !_DEV_ATA_ATAREG_H_ */ 262