1 /* $NetBSD: wdsreg.h,v 1.8 2005/12/11 12:22:03 christos Exp $ */ 2 3 typedef u_char physaddr[3]; 4 typedef u_char physlen[3]; 5 #define ltophys _lto3b 6 #define phystol _3btol 7 8 /* WD7000 registers */ 9 #define WDS_STAT 0 /* read */ 10 #define WDS_IRQSTAT 1 /* read */ 11 12 #define WDS_CMD 0 /* write */ 13 #define WDS_IRQACK 1 /* write */ 14 #define WDS_HCR 2 /* write */ 15 16 /* WDS_STAT (read) defs */ 17 #define WDSS_IRQ 0x80 18 #define WDSS_RDY 0x40 19 #define WDSS_REJ 0x20 20 #define WDSS_INIT 0x10 21 22 /* WDS_IRQSTAT (read) defs */ 23 #define WDSI_MASK 0xc0 24 #define WDSI_ERR 0x00 25 #define WDSI_MFREE 0x80 26 #define WDSI_MSVC 0xc0 27 28 /* WDS_CMD (write) defs */ 29 #define WDSC_NOOP 0x00 30 #define WDSC_INIT 0x01 31 #define WDSC_DISUNSOL 0x02 32 #define WDSC_ENAUNSOL 0x03 33 #define WDSC_IRQMFREE 0x04 34 #define WDSC_SCSIRESETSOFT 0x05 35 #define WDSC_SCSIRESETHARD 0x06 36 #define WDSC_MSTART(m) (0x80 + (m)) 37 #define WDSC_MMSTART(m) (0xc0 + (m)) 38 39 /* WDS_HCR (write) defs */ 40 #define WDSH_IRQEN 0x08 41 #define WDSH_DRQEN 0x04 42 #define WDSH_SCSIRESET 0x02 43 #define WDSH_ASCRESET 0x01 44 45 #define WDS_NSEG 17 46 47 struct wds_scat_gath { 48 physlen seg_len; 49 physaddr seg_addr; 50 }; 51 52 struct wds_cmd { 53 u_char opcode; 54 u_char targ; 55 u_char scb[12]; 56 u_char stat; 57 u_char venderr; 58 physlen len; 59 physaddr data; 60 physaddr link; 61 u_char write; 62 u_char xx[6]; 63 }; 64 65 struct wds_scb { 66 struct wds_cmd cmd; 67 struct wds_cmd sense; 68 69 struct wds_scat_gath scat_gath[WDS_NSEG]; 70 struct scsi_sense_data sense_data; 71 72 TAILQ_ENTRY(wds_scb) chain; 73 struct wds_scb *nexthash; 74 u_long hashkey; 75 struct scsipi_xfer *xs; 76 int flags; 77 #define SCB_ALLOC 0x01 78 #define SCB_ABORT 0x02 79 #ifdef WDSDIAG 80 #define SCB_SENDING 0x04 81 #endif 82 #define SCB_POLLED 0x08 83 #define SCB_SENSE 0x10 84 #define SCB_DONE 0x20 /* for internal commands only */ 85 #define SCB_BUFFER 0x40 86 int timeout; 87 88 /* 89 * DMA maps used by the SCB. These maps are created in 90 * wds_init_scb(). 91 */ 92 93 /* 94 * The DMA map maps an individual SCB. This map is permanently 95 * loaded in wds_init_scb(). 96 */ 97 bus_dmamap_t dmamap_self; 98 99 /* 100 * This map maps the buffer involved in the transfer. 101 * Its contents are loaded into "scat_gath" above. 102 */ 103 bus_dmamap_t dmamap_xfer; 104 }; 105 106 #define WDSX_SCSICMD 0x00 107 #define WDSX_SCSISG 0x01 108 #define WDSX_OPEN_RCVBUF 0x80 109 #define WDSX_RCV_CMD 0x81 110 #define WDSX_RCV_DATA 0x82 111 #define WDSX_RCV_DATASTAT 0x83 112 #define WDSX_SND_DATA 0x84 113 #define WDSX_SND_DATASTAT 0x85 114 #define WDSX_SND_CMDSTAT 0x86 115 #define WDSX_READINIT 0x88 116 #define WDSX_READSCSIID 0x89 117 #define WDSX_SETUNSOLIRQMASK 0x8a 118 #define WDSX_GETUNSOLIRQMASK 0x8b 119 #define WDSX_GETFIRMREV 0x8c 120 #define WDSX_EXECDIAG 0x8d 121 #define WDSX_SETEXECPARM 0x8e 122 #define WDSX_GETEXECPARM 0x8f 123 124 struct wds_mbx_out { 125 u_char cmd; 126 physaddr scb_addr; 127 }; 128 129 struct wds_mbx_in { 130 u_char stat; 131 physaddr scb_addr; 132 }; 133 134 /* 135 * mbo.cmd values 136 */ 137 #define WDS_MBO_FREE 0x0 /* MBO entry is free */ 138 #define WDS_MBO_START 0x1 /* MBO activate entry */ 139 140 /* 141 * mbi.stat values 142 */ 143 #define WDS_MBI_FREE 0x00 /* MBI entry is free */ 144 #define WDS_MBI_OK 0x01 /* completed without error */ 145 #define WDS_MBI_OKERR 0x02 /* completed with error */ 146 #define WDS_MBI_ETIME 0x04 147 #define WDS_MBI_ERESET 0x05 148 #define WDS_MBI_ETARCMD 0x06 149 #define WDS_MBI_ERESEL 0x80 150 #define WDS_MBI_ESEL 0x81 151 #define WDS_MBI_EABORT 0x82 152 #define WDS_MBI_ESRESET 0x83 153 #define WDS_MBI_EHRESET 0x84 154 155 struct wds_setup { 156 u_char opcode; 157 u_char scsi_id; 158 u_char buson_t; 159 u_char busoff_t; 160 u_char xx; 161 physaddr mbaddr; 162 u_char nomb; 163 u_char nimb; 164 }; 165