1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
4 * All rights reserved.
5 */
6
7 #ifndef WILC_WLAN_H
8 #define WILC_WLAN_H
9
10 #include <linux/types.h>
11 #include <linux/bitfield.h>
12
13 /********************************************
14 *
15 * Mac eth header length
16 *
17 ********************************************/
18 #define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
19 #define SUB_MSDU_HEADER_LENGTH 14
20 #define SNAP_HDR_LEN 8
21 #define ETHERNET_HDR_LEN 14
22 #define WORD_ALIGNMENT_PAD 0
23
24 #define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \
25 SUB_MSDU_HEADER_LENGTH + \
26 SNAP_HDR_LEN - \
27 ETHERNET_HDR_LEN + \
28 WORD_ALIGNMENT_PAD)
29
30 #define HOST_HDR_OFFSET 4
31 #define ETHERNET_HDR_LEN 14
32 #define IP_HDR_LEN 20
33 #define IP_HDR_OFFSET ETHERNET_HDR_LEN
34 #define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
35 #define UDP_HDR_LEN 8
36 #define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
37 #define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
38
39 #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
40 ETH_CONFIG_PKT_HDR_LEN)
41
42 /********************************************
43 *
44 * Register Defines
45 *
46 ********************************************/
47 #define WILC_PERIPH_REG_BASE 0x1000
48 #define WILC_CHANGING_VIR_IF 0x108c
49 #define WILC_CHIPID WILC_PERIPH_REG_BASE
50 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
51 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
52 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
53 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
54 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
55 #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
56 #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
57 #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
58 #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
59 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
60 #define WILC_INTR_ENABLE WILC_INTR_REG_BASE
61 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
62
63 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
64 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
65 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
66 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
67
68 #define WILC_RF_REVISION_ID 0x13f4
69
70 #define WILC_VMM_TBL_SIZE 64
71 #define WILC_VMM_TX_TBL_BASE 0x150400
72 #define WILC_VMM_RX_TBL_BASE 0x150500
73
74 #define WILC_VMM_BASE 0x150000
75 #define WILC_VMM_CORE_CTL WILC_VMM_BASE
76 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
77 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
78 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
79 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
80 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
81 #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
82 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
83
84 #define WILC_SPI_REG_BASE 0xe800
85 #define WILC_SPI_CTL WILC_SPI_REG_BASE
86 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
87 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
88 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
89 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
90 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
91 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
92 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
93 #define WILC_SPI_INT_STATUS (WILC_SPI_REG_BASE + 0x40)
94 #define WILC_SPI_INT_CLEAR (WILC_SPI_REG_BASE + 0x44)
95
96 #define WILC_SPI_WAKEUP_REG 0x1
97 #define WILC_SPI_WAKEUP_BIT BIT(1)
98
99 #define WILC_SPI_CLK_STATUS_REG 0x0f
100 #define WILC_SPI_CLK_STATUS_BIT BIT(2)
101 #define WILC_SPI_HOST_TO_FW_REG 0x0b
102 #define WILC_SPI_HOST_TO_FW_BIT BIT(0)
103
104 #define WILC_SPI_FW_TO_HOST_REG 0x10
105 #define WILC_SPI_FW_TO_HOST_BIT BIT(0)
106
107 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \
108 WILC_SPI_REG_BASE)
109
110 #define WILC_SPI_CLOCKLESS_ADDR_LIMIT 0x30
111
112 /* Functions IO enables bits */
113 #define WILC_SDIO_CCCR_IO_EN_FUNC1 BIT(1)
114
115 /* Function/Interrupt enables bits */
116 #define WILC_SDIO_CCCR_IEN_MASTER BIT(0)
117 #define WILC_SDIO_CCCR_IEN_FUNC1 BIT(1)
118
119 /* Abort CCCR register bits */
120 #define WILC_SDIO_CCCR_ABORT_RESET BIT(3)
121
122 /* Vendor specific CCCR registers */
123 #define WILC_SDIO_WAKEUP_REG 0xf0
124 #define WILC_SDIO_WAKEUP_BIT BIT(0)
125
126 #define WILC_SDIO_CLK_STATUS_REG 0xf1
127 #define WILC_SDIO_CLK_STATUS_BIT BIT(0)
128
129 #define WILC_SDIO_INTERRUPT_DATA_SZ_REG 0xf2 /* Read size (2 bytes) */
130
131 #define WILC_SDIO_VMM_TBL_CTRL_REG 0xf6
132 #define WILC_SDIO_IRQ_FLAG_REG 0xf7
133 #define WILC_SDIO_IRQ_CLEAR_FLAG_REG 0xf8
134
135 #define WILC_SDIO_HOST_TO_FW_REG 0xfa
136 #define WILC_SDIO_HOST_TO_FW_BIT BIT(0)
137
138 #define WILC_SDIO_FW_TO_HOST_REG 0xfc
139 #define WILC_SDIO_FW_TO_HOST_BIT BIT(0)
140
141 /* Function 1 specific FBR register */
142 #define WILC_SDIO_FBR_CSA_REG 0x10C /* CSA pointer (3 bytes) */
143 #define WILC_SDIO_FBR_DATA_REG 0x10F
144
145 #define WILC_SDIO_F1_DATA_REG 0x0
146 #define WILC_SDIO_EXT_IRQ_FLAG_REG 0x4
147
148 #define WILC_AHB_DATA_MEM_BASE 0x30000
149 #define WILC_AHB_SHARE_MEM_BASE 0xd0000
150
151 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE
152 #define WILC_VMM_TBL_RX_SHADOW_SIZE 256
153
154 #define WILC_FW_HOST_COMM 0x13c0
155 #define WILC_GP_REG_0 0x149c
156 #define WILC_GP_REG_1 0x14a0
157
158 #define GLOBAL_MODE_CONTROL 0x1614
159 #define PWR_SEQ_MISC_CTRL 0x3008
160
161 #define WILC_GLOBAL_MODE_ENABLE_WIFI BIT(0)
162 #define WILC_PWR_SEQ_ENABLE_WIFI_SLEEP BIT(28)
163
164 #define WILC_HAVE_SDIO_IRQ_GPIO BIT(0)
165 #define WILC_HAVE_USE_PMU BIT(1)
166 #define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2)
167 #define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3)
168 #define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4)
169 #define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5)
170 #define WILC_HAVE_XTAL_24 BIT(6)
171 #define WILC_HAVE_DISABLE_WILC_UART BIT(7)
172 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8)
173
174 #define WILC_CORTUS_INTERRUPT_BASE 0x10A8
175 #define WILC_CORTUS_INTERRUPT_1 (WILC_CORTUS_INTERRUPT_BASE + 0x4)
176 #define WILC_CORTUS_INTERRUPT_2 (WILC_CORTUS_INTERRUPT_BASE + 0x8)
177
178 /* tx control register 1 to 4 for RX */
179 #define WILC_REG_4_TO_1_RX 0x1e1c
180
181 /* tx control register 1 to 4 for TX Bank_0 */
182 #define WILC_REG_4_TO_1_TX_BANK0 0x1e9c
183
184 #define WILC_CORTUS_RESET_MUX_SEL 0x1118
185 #define WILC_CORTUS_BOOT_REGISTER 0xc0000
186
187 #define WILC_CORTUS_BOOT_FROM_IRAM 0x71
188
189 #define WILC_1000_BASE_ID 0x100000
190
191 #define WILC_1000_BASE_ID_2A 0x1002A0
192 #define WILC_1000_BASE_ID_2A_REV1 (WILC_1000_BASE_ID_2A + 1)
193
194 #define WILC_1000_BASE_ID_2B 0x1002B0
195 #define WILC_1000_BASE_ID_2B_REV1 (WILC_1000_BASE_ID_2B + 1)
196 #define WILC_1000_BASE_ID_2B_REV2 (WILC_1000_BASE_ID_2B + 2)
197
198 #define WILC_CHIP_REV_FIELD GENMASK(11, 0)
199
200 /********************************************
201 *
202 * Wlan Defines
203 *
204 ********************************************/
205 #define WILC_CFG_PKT 1
206 #define WILC_NET_PKT 0
207 #define WILC_MGMT_PKT 2
208
209 #define WILC_CFG_SET 1
210 #define WILC_CFG_QUERY 0
211
212 #define WILC_CFG_RSP 1
213 #define WILC_CFG_RSP_STATUS 2
214 #define WILC_CFG_RSP_SCAN 3
215
216 #define WILC_ABORT_REQ_BIT BIT(31)
217
218 #define WILC_RX_BUFF_SIZE (96 * 1024)
219 #define WILC_TX_BUFF_SIZE (64 * 1024)
220
221 #define NQUEUES 4
222 #define AC_BUFFER_SIZE 1000
223
224 #define VO_AC_COUNT_FIELD GENMASK(31, 25)
225 #define VO_AC_ACM_STAT_FIELD BIT(24)
226 #define VI_AC_COUNT_FIELD GENMASK(23, 17)
227 #define VI_AC_ACM_STAT_FIELD BIT(16)
228 #define BE_AC_COUNT_FIELD GENMASK(15, 9)
229 #define BE_AC_ACM_STAT_FIELD BIT(8)
230 #define BK_AC_COUNT_FIELD GENMASK(7, 3)
231 #define BK_AC_ACM_STAT_FIELD BIT(1)
232
233 #define WILC_PKT_HDR_CONFIG_FIELD BIT(31)
234 #define WILC_PKT_HDR_OFFSET_FIELD GENMASK(30, 22)
235 #define WILC_PKT_HDR_TOTAL_LEN_FIELD GENMASK(21, 11)
236 #define WILC_PKT_HDR_LEN_FIELD GENMASK(10, 0)
237
238 #define WILC_INTERRUPT_DATA_SIZE GENMASK(14, 0)
239
240 #define WILC_VMM_BUFFER_SIZE GENMASK(9, 0)
241
242 #define WILC_VMM_HDR_TYPE BIT(31)
243 #define WILC_VMM_HDR_MGMT_FIELD BIT(30)
244 #define WILC_VMM_HDR_PKT_SIZE GENMASK(29, 15)
245 #define WILC_VMM_HDR_BUFF_SIZE GENMASK(14, 0)
246
247 #define WILC_VMM_ENTRY_COUNT GENMASK(8, 3)
248 #define WILC_VMM_ENTRY_AVAILABLE BIT(2)
249 /*******************************************/
250 /* E0 and later Interrupt flags. */
251 /*******************************************/
252 /*******************************************/
253 /* E0 and later Interrupt flags. */
254 /* IRQ Status word */
255 /* 15:0 = DMA count in words. */
256 /* 16: INT0 flag */
257 /* 17: INT1 flag */
258 /* 18: INT2 flag */
259 /* 19: INT3 flag */
260 /* 20: INT4 flag */
261 /* 21: INT5 flag */
262 /*******************************************/
263 #define IRG_FLAGS_OFFSET 16
264 #define IRQ_DMA_WD_CNT_MASK GENMASK(IRG_FLAGS_OFFSET - 1, 0)
265 #define INT_0 BIT(IRG_FLAGS_OFFSET)
266 #define INT_1 BIT(IRG_FLAGS_OFFSET + 1)
267 #define INT_2 BIT(IRG_FLAGS_OFFSET + 2)
268 #define INT_3 BIT(IRG_FLAGS_OFFSET + 3)
269 #define INT_4 BIT(IRG_FLAGS_OFFSET + 4)
270 #define INT_5 BIT(IRG_FLAGS_OFFSET + 5)
271 #define MAX_NUM_INT 5
272 #define IRG_FLAGS_MASK GENMASK(IRG_FLAGS_OFFSET + MAX_NUM_INT, \
273 IRG_FLAGS_OFFSET)
274
275 /*******************************************/
276 /* E0 and later Interrupt flags. */
277 /* IRQ Clear word */
278 /* 0: Clear INT0 */
279 /* 1: Clear INT1 */
280 /* 2: Clear INT2 */
281 /* 3: Clear INT3 */
282 /* 4: Clear INT4 */
283 /* 5: Clear INT5 */
284 /* 6: Select VMM table 1 */
285 /* 7: Select VMM table 2 */
286 /* 8: Enable VMM */
287 /*******************************************/
288 #define CLR_INT0 BIT(0)
289 #define CLR_INT1 BIT(1)
290 #define CLR_INT2 BIT(2)
291 #define CLR_INT3 BIT(3)
292 #define CLR_INT4 BIT(4)
293 #define CLR_INT5 BIT(5)
294 #define SEL_VMM_TBL0 BIT(6)
295 #define SEL_VMM_TBL1 BIT(7)
296 #define EN_VMM BIT(8)
297
298 #define DATA_INT_EXT INT_0
299 #define ALL_INT_EXT DATA_INT_EXT
300 #define NUM_INT_EXT 1
301 #define UNHANDLED_IRQ_MASK GENMASK(MAX_NUM_INT - 1, NUM_INT_EXT)
302
303 #define DATA_INT_CLR CLR_INT0
304
305 #define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
306 #define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
307 /* time for expiring the completion of cfg packets */
308 #define WILC_CFG_PKTS_TIMEOUT msecs_to_jiffies(3000)
309
310 #define IS_MANAGMEMENT 0x100
311 #define IS_MANAGMEMENT_CALLBACK 0x080
312 #define IS_MGMT_STATUS_SUCCES 0x040
313 #define IS_MGMT_AUTH_PKT 0x010
314
315 #define WILC_WID_TYPE GENMASK(15, 12)
316 #define WILC_VMM_ENTRY_FULL_RETRY 1
317 /********************************************
318 *
319 * Tx/Rx Queue Structure
320 *
321 ********************************************/
322 enum ip_pkt_priority {
323 AC_VO_Q = 0,
324 AC_VI_Q = 1,
325 AC_BE_Q = 2,
326 AC_BK_Q = 3
327 };
328
329 struct txq_entry_t {
330 struct list_head list;
331 int type;
332 u8 q_num;
333 int ack_idx;
334 u8 *buffer;
335 int buffer_size;
336 void *priv;
337 int status;
338 struct wilc_vif *vif;
339 void (*tx_complete_func)(void *priv, int status);
340 };
341
342 struct txq_fw_recv_queue_stat {
343 u8 acm;
344 u8 count;
345 };
346
347 struct txq_handle {
348 struct txq_entry_t txq_head;
349 u16 count;
350 struct txq_fw_recv_queue_stat fw;
351 };
352
353 struct rxq_entry_t {
354 struct list_head list;
355 u8 *buffer;
356 int buffer_size;
357 };
358
359 /********************************************
360 *
361 * Host IF Structure
362 *
363 ********************************************/
364 struct wilc;
365 struct wilc_hif_func {
366 int (*hif_init)(struct wilc *wilc, bool resume);
367 int (*hif_deinit)(struct wilc *wilc);
368 int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data);
369 int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data);
370 int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
371 int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
372 int (*hif_read_int)(struct wilc *wilc, u32 *int_status);
373 int (*hif_clear_int_ext)(struct wilc *wilc, u32 val);
374 int (*hif_read_size)(struct wilc *wilc, u32 *size);
375 int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
376 int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size);
377 int (*hif_sync_ext)(struct wilc *wilc, int nint);
378 int (*enable_interrupt)(struct wilc *nic);
379 void (*disable_interrupt)(struct wilc *nic);
380 int (*hif_reset)(struct wilc *wilc);
381 bool (*hif_is_init)(struct wilc *wilc);
382 };
383
384 #define WILC_MAX_CFG_FRAME_SIZE 1468
385
386 struct tx_complete_data {
387 int size;
388 void *buff;
389 struct sk_buff *skb;
390 };
391
392 struct wilc_cfg_cmd_hdr {
393 u8 cmd_type;
394 u8 seq_no;
395 __le16 total_len;
396 __le32 driver_handler;
397 };
398
399 struct wilc_cfg_frame {
400 struct wilc_cfg_cmd_hdr hdr;
401 u8 frame[WILC_MAX_CFG_FRAME_SIZE];
402 };
403
404 struct wilc_cfg_rsp {
405 u8 type;
406 u8 seq_no;
407 };
408
409 struct wilc_vif;
410
is_wilc1000(u32 id)411 static inline bool is_wilc1000(u32 id)
412 {
413 return (id & (~WILC_CHIP_REV_FIELD)) == WILC_1000_BASE_ID;
414 }
415
416 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer,
417 u32 buffer_size);
418 int wilc_wlan_start(struct wilc *wilc);
419 int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif);
420 int wilc_wlan_txq_add_net_pkt(struct net_device *dev,
421 struct tx_complete_data *tx_data, u8 *buffer,
422 u32 buffer_size,
423 void (*tx_complete_fn)(void *, int));
424 int wilc_wlan_handle_txq(struct wilc *wl, u32 *txq_count);
425 void wilc_handle_isr(struct wilc *wilc);
426 void wilc_wlan_cleanup(struct net_device *dev);
427 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer,
428 u32 buffer_size, int commit, u32 drv_handler);
429 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit,
430 u32 drv_handler);
431 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer,
432 u32 buffer_size, void (*func)(void *, int));
433 void wilc_enable_tcp_ack_filter(struct wilc_vif *vif, bool value);
434 int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc);
435 netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev);
436
437 void wilc_wfi_p2p_rx(struct wilc_vif *vif, u8 *buff, u32 size);
438 bool wilc_wfi_mgmt_frame_rx(struct wilc_vif *vif, u8 *buff, u32 size);
439 void host_wakeup_notify(struct wilc *wilc);
440 void host_sleep_notify(struct wilc *wilc);
441 void chip_allow_sleep(struct wilc *wilc);
442 void chip_wakeup(struct wilc *wilc);
443 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids,
444 u32 count);
445 int wilc_wlan_init(struct net_device *dev);
446 u32 wilc_get_chipid(struct wilc *wilc, bool update);
447 int wilc_load_mac_from_nv(struct wilc *wilc);
448 #endif
449