1 /* $OpenBSD: xhcireg.h,v 1.20 2024/09/04 07:54:52 mglocker Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Martin Pieuchot. All rights reserved. 5 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _XHCIREG_H_ 30 #define _XHCIREG_H_ 31 32 /* Data Structure Boundary and Alignment Requirement. */ 33 #define XHCI_DCBAA_ALIGN 64 34 #define XHCI_ICTX_ALIGN 64 35 #define XHCI_SCTX_ALIGN 32 36 #define XHCI_OCTX_ALIGN 32 37 #define XHCI_XFER_RING_ALIGN 16 38 #define XHCI_CMDS_RING_ALIGN 64 39 #define XHCI_EVTS_RING_ALIGN 64 40 #define XHCI_RING_BOUNDARY (64 * 1024) 41 #define XHCI_ERST_ALIGN 64 42 #define XHCI_ERST_BOUNDARY 0 43 #define XHCI_SPAD_TABLE_ALIGN 64 44 45 /* XHCI PCI config registers */ 46 #define PCI_CBMEM 0x10 /* configuration base MEM */ 47 48 #define PCI_INTERFACE_XHCI 0x30 49 50 #define PCI_USBREV 0x60 /* RO USB protocol revision */ 51 #define PCI_USBREV_MASK 0xff 52 #define PCI_USBREV_3_0 0x30 /* USB 3.0 */ 53 54 #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ 55 56 #define PCI_XHCI_INTEL_XUSB2PR 0xd0 /* Intel USB2 Port Routing */ 57 #define PCI_XHCI_INTEL_XUSB2PRM 0xd4 /* Intel USB2 Port Routing Mask */ 58 #define PCI_XHCI_INTEL_USB3_PSSEN 0xd8 /* Intel USB3 Port SuperSpeed Enable */ 59 #define PCI_XHCI_INTEL_USB3PRM 0xdc /* Intel USB3 Port Routing Mask */ 60 61 /* XHCI capability registers */ 62 #define XHCI_CAPLENGTH 0x00 /* RO Capability reg. length field */ 63 #define XHCI_RESERVED 0x01 /* Reserved */ 64 #define XHCI_HCIVERSION 0x02 /* RO Interface version number */ 65 #define XHCI_HCIVERSION_0_9 0x0090 /* xHCI version 0.9 */ 66 #define XHCI_HCIVERSION_1_0 0x0100 /* xHCI version 1.0 */ 67 68 #define XHCI_HCSPARAMS1 0x04 /* RO structural parameters 1 */ 69 #define XHCI_HCS1_DEVSLOT_MAX(x)((x) & 0xff) 70 #define XHCI_HCS1_IRQ_MAX(x) (((x) >> 8) & 0x3ff) 71 #define XHCI_HCS1_N_PORTS(x) (((x) >> 24) & 0xff) 72 73 #define XHCI_HCSPARAMS2 0x08 /* RO structural parameters 2 */ 74 #define XHCI_HCS2_IST(x) ((x) & 0x7) 75 #define XHCI_HCS2_IST_MICRO(x) (!((x) & 0x8)) 76 #define XHCI_HCS2_ERST_MAX(x) (((x) >> 4) & 0xf) 77 #define XHCI_HCS2_ETE(x) (((x) >> 8) & 0x1) 78 #define XHCI_HCS2_SPR(x) (((x) >> 26) & 0x1) 79 #define XHCI_HCS2_SPB_MAX(x) ((((x) >> 16) & 0x3e0) | (((x) >> 27) & 0x1f)) 80 81 #define XHCI_HCSPARAMS3 0x0c /* RO structural parameters 3 */ 82 #define XHCI_HCS3_U1_DEL(x) ((x) & 0xff) 83 #define XHCI_HCS3_U2_DEL(x) (((x) >> 16) & 0xffff) 84 85 #define XHCI_HCCPARAMS 0x10 /* RO capability parameters */ 86 #define XHCI_HCC_AC64(x) (((x) >> 0) & 0x1) /* 64-bit capable */ 87 #define XHCI_HCC_BNC(x) (((x) >> 1) & 0x1) /* BW negotiation */ 88 #define XHCI_HCC_CSZ(x) (((x) >> 2) & 0x1) /* Context size */ 89 #define XHCI_HCC_PPC(x) (((x) >> 3) & 0x1) /* Port power control */ 90 #define XHCI_HCC_PIND(x) (((x) >> 4) & 0x1) /* Port indicators */ 91 #define XHCI_HCC_LHRC(x) (((x) >> 5) & 0x1) /* Light HC reset */ 92 #define XHCI_HCC_LTC(x) (((x) >> 6) & 0x1) /* Latency tolerance msg */ 93 #define XHCI_HCC_NSS(x) (((x) >> 7) & 0x1) /* No secondary sid */ 94 #define XHCI_HCC_PAE(x) (((x) >> 8) & 0x1) /* Parse All Event Data */ 95 #define XHCI_HCC_SPC(x) (((x) >> 9) & 0x1) /* Short packet */ 96 #define XHCI_HCC_SEC(x) (((x) >> 10) & 0x1) /* Stopped EDTLA */ 97 #define XHCI_HCC_CFC(x) (((x) >> 11) & 0x1) /* Contiguous Frame ID */ 98 #define XHCI_HCC_MAX_PSA_SZ(x) (((x) >> 12) & 0xf) /* Max pri. stream arr. */ 99 #define XHCI_HCC_XECP(x) (((x) >> 16) & 0xffff) /* Ext. capabilities */ 100 101 #define XHCI_DBOFF 0x14 /* RO doorbell offset */ 102 #define XHCI_RTSOFF 0x18 /* RO runtime register space offset */ 103 104 /* 105 * XHCI operational registers. 106 * Offset given by XHCI_CAPLENGTH register. 107 */ 108 #define XHCI_USBCMD 0x00 /* XHCI command */ 109 #define XHCI_CMD_RS 0x00000001 /* RW Run/Stop */ 110 #define XHCI_CMD_HCRST 0x00000002 /* RW Host Controller Reset */ 111 #define XHCI_CMD_INTE 0x00000004 /* RW Interrupter Enable */ 112 #define XHCI_CMD_HSEE 0x00000008 /* RW Host System Error Enable */ 113 #define XHCI_CMD_LHCRST 0x00000080 /* RO/RW Light HC Reset */ 114 #define XHCI_CMD_CSS 0x00000100 /* RW Controller Save State */ 115 #define XHCI_CMD_CRS 0x00000200 /* RW Controller Restore State */ 116 #define XHCI_CMD_EWE 0x00000400 /* RW Enable Wrap Event */ 117 #define XHCI_CMD_EU3S 0x00000800 /* RW Enable U3 MFINDEX Stop */ 118 119 #define XHCI_USBSTS 0x04 /* XHCI status */ 120 #define XHCI_STS_HCH 0x00000001 /* RO - Host Controller Halted */ 121 #define XHCI_STS_HSE 0x00000004 /* RW - Host System Error */ 122 #define XHCI_STS_EINT 0x00000008 /* RW - Event Interrupt */ 123 #define XHCI_STS_PCD 0x00000010 /* RW - Port Change Detect */ 124 #define XHCI_STS_SSS 0x00000100 /* RO - Save State Status */ 125 #define XHCI_STS_RSS 0x00000200 /* RO - Restore State Status */ 126 #define XHCI_STS_SRE 0x00000400 /* RW - Save/Restore Error */ 127 #define XHCI_STS_CNR 0x00000800 /* RO - Controller Not Ready */ 128 #define XHCI_STS_HCE 0x00001000 /* RO - Host Controller Error */ 129 130 #define XHCI_PAGESIZE 0x08 /* XHCI page size mask */ 131 #define XHCI_PAGESIZE_4K 0x00000001 /* 4K Page Size */ 132 #define XHCI_PAGESIZE_8K 0x00000002 /* 8K Page Size */ 133 #define XHCI_PAGESIZE_16K 0x00000004 /* 16K Page Size */ 134 #define XHCI_PAGESIZE_32K 0x00000008 /* 32K Page Size */ 135 #define XHCI_PAGESIZE_64K 0x00000010 /* 64K Page Size */ 136 137 #define XHCI_DNCTRL 0x14 /* XHCI device notification control */ 138 #define XHCI_DNCTRL_MASK(n) (1 << (n)) 139 140 #define XHCI_CRCR_LO 0x18 /* XHCI command ring control */ 141 #define XHCI_CRCR_LO_RCS 0x00000001 /* RW - consumer cycle state */ 142 #define XHCI_CRCR_LO_CS 0x00000002 /* RW - command stop */ 143 #define XHCI_CRCR_LO_CA 0x00000004 /* RW - command abort */ 144 #define XHCI_CRCR_LO_CRR 0x00000008 /* RW - command ring running */ 145 #define XHCI_CRCR_LO_MASK 0x0000000F 146 147 #define XHCI_CRCR_HI 0x1C /* XHCI command ring control */ 148 #define XHCI_DCBAAP_LO 0x30 /* XHCI dev context BA pointer */ 149 #define XHCI_DCBAAP_HI 0x34 /* XHCI dev context BA pointer */ 150 #define XHCI_CONFIG 0x38 151 #define XHCI_CONFIG_SLOTS_MASK 0x000000ff /* RW - nb of device slots enabled */ 152 153 /* 154 * XHCI port status registers. 155 */ 156 #define XHCI_PORTSC(n) (0x3f0 + (0x10 * (n))) /* XHCI port status */ 157 #define XHCI_PS_CCS 0x00000001 /* RO - current connect status */ 158 #define XHCI_PS_PED 0x00000002 /* RW - port enabled / disabled */ 159 #define XHCI_PS_OCA 0x00000008 /* RO - over current active */ 160 #define XHCI_PS_PR 0x00000010 /* RW - port reset */ 161 #define XHCI_PS_GET_PLS(x) (((x) >> 5) & 0xf) /* RW - port link state */ 162 #define XHCI_PS_SET_PLS(x) (((x) & 0xf) << 5) /* RW - port link state */ 163 #define XHCI_PS_PP 0x00000200 /* RW - port power */ 164 #define XHCI_PS_SPEED(x) (((x) >> 10) & 0xf) /* RO - port speed */ 165 #define XHCI_PS_GET_PIC(x) (((x) >> 14) & 0x3) /* RW - port indicator */ 166 #define XHCI_PS_SET_PIC(x) (((x) & 0x3) << 14) /* RW - port indicator */ 167 #define XHCI_PS_LWS 0x00010000 /* RW - link state write strobe */ 168 #define XHCI_PS_CSC 0x00020000 /* RW - connect status change */ 169 #define XHCI_PS_PEC 0x00040000 /* RW - port enable/disable change */ 170 #define XHCI_PS_WRC 0x00080000 /* RW - warm port reset change */ 171 #define XHCI_PS_OCC 0x00100000 /* RW - over-current change */ 172 #define XHCI_PS_PRC 0x00200000 /* RW - port reset change */ 173 #define XHCI_PS_PLC 0x00400000 /* RW - port link state change */ 174 #define XHCI_PS_CEC 0x00800000 /* RW - config error change */ 175 #define XHCI_PS_CAS 0x01000000 /* RO - cold attach status */ 176 #define XHCI_PS_WCE 0x02000000 /* RW - wake on connect enable */ 177 #define XHCI_PS_WDE 0x04000000 /* RW - wake on disconnect enable */ 178 #define XHCI_PS_WOE 0x08000000 /* RW - wake on over-current enable*/ 179 #define XHCI_PS_DR 0x40000000 /* RO - device removable */ 180 #define XHCI_PS_WPR 0x80000000U /* RW - warm port reset */ 181 #define XHCI_PS_CLEAR 0x80ff01ffu /* command bits */ 182 183 #define XHCI_PORTPMSC(n) (0x3f4 + (0x10 * (n))) /* XHCI status & ctrl */ 184 #define XHCI_PM3_U1TO(x) (((x) & 0xff) << 0) /* RW - U1 timeout */ 185 #define XHCI_PM3_U2TO(x) (((x) & 0xff) << 8) /* RW - U2 timeout */ 186 #define XHCI_PM3_FLA 0x00010000 /* RW - Force Link PM Accept */ 187 #define XHCI_PM2_L1S(x) (((x) >> 0) & 0x7) /* RO - L1 status */ 188 #define XHCI_PM2_RWE 0x00000008 /* RW - remote wakeup enable */ 189 #define XHCI_PM2_HIRD(x) (((x) & 0xf) << 4) /* RW - resume duration */ 190 #define XHCI_PM2_L1SLOT(x) (((x) & 0xff) << 8) /* RW - L1 device slot */ 191 #define XHCI_PM2_HLE 0x00010000 /* RW - hardware LPM enable */ 192 #define XHCI_PORTLI(n) (0x3f8 + (0x10 * (n))) /* XHCI port link info */ 193 #define XHCI_PORTRSV(n) (0x3fC + (0x10 * (n))) /* XHCI port reserved */ 194 195 /* 196 * XHCI runtime registers. 197 * Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers. 198 */ 199 #define XHCI_MFINDEX 0x0000 /* RO - microframe index */ 200 #define XHCI_GET_MFINDEX(x) ((x) & 0x3fff) 201 #define XHCI_IMAN(n) (0x0020 + (0x20 * (n))) /* intr.management */ 202 #define XHCI_IMAN_INTR_PEND 0x00000001 /* RW - interrupt pending */ 203 #define XHCI_IMAN_INTR_ENA 0x00000002 /* RW - interrupt enable */ 204 205 /* XHCI interrupt moderation */ 206 #define XHCI_IMOD(n) (0x0024 + (0x20 * (n))) 207 #define XHCI_IMOD_IVAL_GET(x) (((x) >> 0) & 0xffff) /* 250ns unit */ 208 #define XHCI_IMOD_IVAL_SET(x) (((x) & 0xffff) << 0) /* 250ns unit */ 209 #define XHCI_IMOD_ICNT_GET(x) (((x) >> 16) & 0xffff) /* 250ns unit */ 210 #define XHCI_IMOD_ICNT_SET(x) (((x) & 0xffff) << 16) /* 250ns unit */ 211 #define XHCI_IMOD_DEFAULT 0x000001F4U /* 8000 IRQ/second */ 212 #define XHCI_IMOD_DEFAULT_LP 0x000003E8U /* 4000 IRQ/second */ 213 214 /* XHCI event ring segment table size */ 215 #define XHCI_ERSTSZ(n) (0x0028 + (0x20 * (n))) 216 #define XHCI_ERSTS_SET(x) ((x) & 0xffff) 217 218 /* XHCI event ring segment table BA */ 219 #define XHCI_ERSTBA_LO(n) (0x0030 + (0x20 * (n))) 220 #define XHCI_ERSTBA_HI(n) (0x0034 + (0x20 * (n))) 221 222 /* XHCI event ring dequeue pointer */ 223 #define XHCI_ERDP_LO(n) (0x0038 + (0x20 * (n))) 224 #define XHCI_ERDP_LO_BUSY 0x00000008 /* RW - event handler busy */ 225 #define XHCI_ERDP_HI(n) (0x003c + (0x20 * (n))) 226 227 /* 228 * XHCI doorbell registers. 229 * Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers. 230 */ 231 #define XHCI_DOORBELL(n) (0x0000 + (4 * (n))) 232 #define XHCI_DB_GET_SID(x) (((x) >> 16) & 0xffff) /* RW - stream ID */ 233 #define XHCI_DB_SET_SID(x) (((x) & 0xffff) << 16) /* RW - stream ID */ 234 235 /* XHCI legacy support */ 236 #define XHCI_XECP_ID(x) ((x) & 0xff) 237 #define XHCI_XECP_NEXT(x) (((x) >> 8) & 0xff) 238 #define XHCI_XECP_BIOS_SEM 0x0002 239 #define XHCI_XECP_OS_SEM 0x0003 240 241 /* XHCI capability ID's */ 242 #define XHCI_ID_USB_LEGACY 0x0001 243 #define XHCI_ID_PROTOCOLS 0x0002 244 #define XHCI_ID_POWER_MGMT 0x0003 245 #define XHCI_ID_VIRTUALIZATION 0x0004 246 #define XHCI_ID_MSG_IRQ 0x0005 247 #define XHCI_ID_USB_LOCAL_MEM 0x0006 248 249 250 struct xhci_erseg { 251 uint64_t er_addr; 252 uint32_t er_size; 253 uint32_t er_rsvd; 254 }; 255 256 257 struct xhci_sctx { 258 uint32_t info_lo; 259 #define XHCI_SCTX_ROUTE(x) ((x) & 0xfffff) 260 #define XHCI_SCTX_SPEED(x) (((x) & 0xf) << 20) 261 #define XHCI_SCTX_MTT(x) (((x) & 0x1) << 25) 262 #define XHCI_SCTX_HUB(x) (((x) & 0x1) << 26) 263 #define XHCI_SCTX_DCI(x) (((x) & 0x1f) << 27) 264 265 uint32_t info_hi; 266 #define XHCI_SCTX_MAX_EL(x) ((x) & 0xffff) 267 #define XHCI_SCTX_RHPORT(x) (((x) & 0xff) << 16) 268 #define XHCI_SCTX_NPORTS(x) (((x) & 0xff) << 24) 269 270 uint32_t tt; 271 #define XHCI_SCTX_TT_HUB_SID(x) ((x) & 0xff) 272 #define XHCI_SCTX_TT_PORT_NUM(x) (((x) & 0xff) << 8) 273 #define XHCI_SCTX_TT_THINK_TIME(x) (((x) & 0x3) << 16) 274 #define XHCI_SCTX_SET_IRQ_TARGET(x) (((x) & 0x3ff) << 22) 275 #define XHCI_SCTX_GET_IRQ_TARGET(x) (((x) >> 22) & 0x3ff) 276 277 uint32_t state; 278 #define XHCI_SCTX_DEV_ADDR(x) ((x) & 0xff) 279 #define XHCI_SCTX_SLOT_STATE(x) (((x) >> 27) & 0x1f) 280 281 uint32_t rsvd[4]; 282 }; 283 284 struct xhci_epctx { 285 uint32_t info_lo; 286 #define XHCI_EPCTX_STATE(x) ((x) & 0x7) 287 #define XHCI_EP_DISABLED 0x0 288 #define XHCI_EP_RUNNING 0x1 289 #define XHCI_EP_HALTED 0x2 290 #define XHCI_EP_STOPPED 0x3 291 #define XHCI_EP_ERROR 0x4 292 #define XHCI_EPCTX_SET_MULT(x) (((x) & 0x3) << 8) 293 #define XHCI_EPCTX_GET_MULT(x) (((x) >> 8) & 0x3) 294 #define XHCI_EPCTX_SET_MAXP_STREAMS(x) (((x) & 0x1F) << 10) 295 #define XHCI_EPCTX_GET_MAXP_STREAMS(x) (((x) >> 10) & 0x1F) 296 #define XHCI_EPCTX_SET_LSA(x) (((x) & 0x1) << 15) 297 #define XHCI_EPCTX_GET_LSA(x) (((x) >> 15) & 0x1) 298 #define XHCI_EPCTX_SET_IVAL(x) (((x) & 0xff) << 16) 299 #define XHCI_EPCTX_GET_IVAL(x) (((x) >> 16) & 0xFF) 300 #define XHCI_EPCTX_MAX_IVAL 15 /* Poll rates: 2^(n-1) * 0.125us */ 301 302 uint32_t info_hi; 303 #define XHCI_EPCTX_SET_CERR(x) (((x) & 0x3) << 1) 304 #define XHCI_EPCTX_SET_EPTYPE(x) (((x) & 0x7) << 3) 305 #define XHCI_EPCTX_GET_EPTYPE(x) (((x) >> 3) & 0x7) 306 #define XHCI_EPCTX_SET_HID(x) (((x) & 0x1) << 7) 307 #define XHCI_EPCTX_GET_HID(x) (((x) >> 7) & 0x1) 308 #define XHCI_EPCTX_SET_MAXB(x) (((x) & 0xff) << 8) 309 #define XHCI_EPCTX_GET_MAXB(x) (((x) >> 8) & 0xff) 310 #define XHCI_EPCTX_SET_MPS(x) (((x) & 0xffff) << 16) 311 #define XHCI_EPCTX_GET_MPS(x) (((x) >> 16) & 0xffff) 312 #define XHCI_SPEED_FULL 1 313 #define XHCI_SPEED_LOW 2 314 #define XHCI_SPEED_HIGH 3 315 #define XHCI_SPEED_SUPER 4 316 317 uint64_t deqp; 318 319 uint32_t txinfo; 320 #define XHCI_EPCTX_AVG_TRB_LEN(x) ((x) & 0xffff) 321 #define XHCI_EPCTX_MAX_ESIT_PAYLOAD(x) (((x) & 0xffff) << 16) 322 323 uint32_t rsvd[3]; 324 }; 325 326 327 struct xhci_inctx { 328 uint32_t drop_flags; 329 uint32_t add_flags; 330 #define XHCI_INCTX_MASK_DCI(n) (0x1 << (n)) 331 332 uint32_t rsvd[6]; 333 }; 334 335 336 struct xhci_trb { 337 uint64_t trb_paddr; 338 #define XHCI_TRB_PORTID(x) (((x) >> 24) & 0xff) /* Port ID */ 339 #define XHCI_TRB_MAXSIZE (64 * 1024) 340 341 uint32_t trb_status; 342 #define XHCI_TRB_GET_CODE(x) (((x) >> 24) & 0xff) 343 #define XHCI_TRB_TDREM(x) (((x) & 0x1f) << 17) /* TD remaining len. */ 344 #define XHCI_TRB_REMAIN(x) ((x) & 0xffffff) /* Remaining length */ 345 #define XHCI_TRB_LEN(x) ((x) & 0x1ffff) /* Transfer length */ 346 #define XHCI_TRB_INTR(x) (((x) & 0x3ff) << 22) /* MSI-X intr. target */ 347 348 uint32_t trb_flags; 349 #define XHCI_TRB_CYCLE (1 << 0) /* Enqueue point of xfer ring */ 350 #define XHCI_TRB_ENT (1 << 1) /* Evaluate next TRB */ 351 #define XHCI_TRB_LINKSEG XHCI_TRB_ENT /* Link to next segment */ 352 #define XHCI_TRB_ISP (1 << 2) /* Interrupt on short packet */ 353 #define XHCI_TRB_NOSNOOP (1 << 3) /* PCIe no snoop */ 354 #define XHCI_TRB_CHAIN (1 << 4) /* Chained with next TRB */ 355 #define XHCI_TRB_IOC (1 << 5) /* Interrupt On Completion */ 356 #define XHCI_TRB_IDT (1 << 6) /* Immediate DaTa */ 357 #define XHCI_TRB_ISOC_TBC(x) (((x) & 0x3) << 7) /* Transfer Burst Count */ 358 #define XHCI_TRB_BSR (1 << 9) /* Block Set Address Request */ 359 #define XHCI_TRB_ISOC_BEI (1 << 9) /* Block Event Interrupt */ 360 #define XHCI_TRB_DIR_IN (1 << 16) 361 #define XHCI_TRB_TRT_OUT (2 << 16) 362 #define XHCI_TRB_TRT_IN (3 << 16) 363 #define XHCI_TRB_GET_EP(x) (((x) >> 16) & 0x1f) 364 #define XHCI_TRB_SET_EP(x) (((x) & 0x1f) << 16) 365 #define XHCI_TRB_ISOC_TLBPC(x) (((x) & 0xf) << 16) 366 #define XHCI_TRB_ISOC_FRAME(x) (((x) & 0x7ff) << 20) 367 #define XHCI_TRB_GET_SLOT(x) (((x) >> 24) & 0xff) 368 #define XHCI_TRB_SET_SLOT(x) (((x) & 0xff) << 24) 369 #define XHCI_TRB_SIA (1U << 31) 370 }; 371 372 #define XHCI_TRB_FLAGS_BITMASK \ 373 "\20" "\040SIA" "\022TRT_OUT" "\021DIR_IN" "\012BSR" "\007IDT" \ 374 "\006IOC" "\005CHAIN" "\004NOSNOOP" "\003ISP" "\002LINKSEG" "\001CYCLE" 375 376 #define XHCI_TRB_TYPE_MASK 0xfc00 377 #define XHCI_TRB_TYPE(x) (((x) & XHCI_TRB_TYPE_MASK) >> 10) 378 379 /* Transfer Ring Types */ 380 #define XHCI_TRB_TYPE_NORMAL (1 << 10) 381 #define XHCI_TRB_TYPE_SETUP (2 << 10) /* Setup stage (ctrl only) */ 382 #define XHCI_TRB_TYPE_DATA (3 << 10) /* Data stage (ctrl only) */ 383 #define XHCI_TRB_TYPE_STATUS (4 << 10) /* Status stage (ctrl only) */ 384 #define XHCI_TRB_TYPE_ISOCH (5 << 10) 385 #define XHCI_TRB_TYPE_LINK (6 << 10) /* Link next seg. (all+cmd) */ 386 #define XHCI_TRB_TYPE_EVENT (7 << 10) /* Generate event (all) */ 387 #define XHCI_TRB_TYPE_NOOP (8 << 10) /* No-Op (all) */ 388 389 /* Command ring Types */ 390 #define XHCI_CMD_ENABLE_SLOT (9 << 10) 391 #define XHCI_CMD_DISABLE_SLOT (10 << 10) 392 #define XHCI_CMD_ADDRESS_DEVICE (11 << 10) 393 #define XHCI_CMD_CONFIG_EP (12 << 10) 394 #define XHCI_CMD_EVAL_CTX (13 << 10) 395 #define XHCI_CMD_RESET_EP (14 << 10) 396 #define XHCI_CMD_STOP_EP (15 << 10) 397 #define XHCI_CMD_SET_TR_DEQ (16 << 10) 398 #define XHCI_CMD_RESET_DEV (17 << 10) 399 #define XHCI_CMD_FEVENT (18 << 10) 400 #define XHCI_CMD_NEG_BW (19 << 10) /* Negotiate bandwidth */ 401 #define XHCI_CMD_SET_LT (20 << 10) /* Set latency tolerance */ 402 #define XHCI_CMD_GET_BW (21 << 10) /* Get port bandwidth */ 403 #define XHCI_CMD_FHEADER (22 << 10) 404 #define XHCI_CMD_NOOP (23 << 10) /* To test the command ring */ 405 406 /* Event ring Types */ 407 #define XHCI_EVT_XFER (32 << 10) /* Transfer event */ 408 #define XHCI_EVT_CMD_COMPLETE (33 << 10) 409 #define XHCI_EVT_PORT_CHANGE (34 << 10) /* Port status change */ 410 #define XHCI_EVT_BW_REQUEST (35 << 10) 411 #define XHCI_EVT_DOORBELL (36 << 10) 412 #define XHCI_EVT_HOST_CTRL (37 << 10) 413 #define XHCI_EVT_DEVICE_NOTIFY (38 << 10) 414 #define XHCI_EVT_MFINDEX_WRAP (39 << 10) 415 416 /* TRB Completion codes */ 417 #define XHCI_CODE_INVALID 0 /* Producer didn't update the code. */ 418 #define XHCI_CODE_SUCCESS 1 /* Badaboum, plaf, plouf, yeepee! */ 419 #define XHCI_CODE_DATA_BUF 2 /* Overrun or underrun */ 420 #define XHCI_CODE_BABBLE 3 /* Device is "babbling" */ 421 #define XHCI_CODE_TXERR 4 /* USB Transaction error */ 422 #define XHCI_CODE_TRB 5 /* Invalid TRB */ 423 #define XHCI_CODE_STALL 6 /* Stall condition */ 424 #define XHCI_CODE_RESOURCE 7 /* No resource available for the cmd */ 425 #define XHCI_CODE_BANDWIDTH 8 /* Not enough bandwidth for the cmd */ 426 #define XHCI_CODE_NO_SLOTS 9 /* MaxSlots limit reached */ 427 #define XHCI_CODE_STREAM_TYPE 10 /* Stream Context Type value detected */ 428 #define XHCI_CODE_SLOT_NOT_ON 11 /* Related device slot is disabled */ 429 #define XHCI_CODE_ENDP_NOT_ON 12 /* Related endpoint is disabled */ 430 #define XHCI_CODE_SHORT_XFER 13 /* Short packet */ 431 #define XHCI_CODE_RING_UNDERRUN 14 /* Empty ring when transmitting isoc */ 432 #define XHCI_CODE_RING_OVERRUN 15 /* Empty ring when receiving isoc */ 433 #define XHCI_CODE_VF_RING_FULL 16 /* VF's event ring is full */ 434 #define XHCI_CODE_PARAMETER 17 /* Context parameter is invalid */ 435 #define XHCI_CODE_BW_OVERRUN 18 /* TD exceeds the bandwidth */ 436 #define XHCI_CODE_CONTEXT_STATE 19 /* Transition from illegal ctx state */ 437 #define XHCI_CODE_NO_PING_RESP 20 /* Unable to complete periodic xfer */ 438 #define XHCI_CODE_EV_RING_FULL 21 /* Unable to post an evt to the ring */ 439 #define XHCI_CODE_INCOMPAT_DEV 22 /* Device cannot be accessed */ 440 #define XHCI_CODE_MISSED_SRV 23 /* Unable to service isoc EP in ESIT */ 441 #define XHCI_CODE_CMD_RING_STOP 24 /* Command Stop (CS) requested */ 442 #define XHCI_CODE_CMD_ABORTED 25 /* Command Abort (CA) operation */ 443 #define XHCI_CODE_XFER_STOPPED 26 /* xfer terminated by a stop endpoint */ 444 #define XHCI_CODE_XFER_STOPINV 27 /* TRB transfer length invalid */ 445 #define XHCI_CODE_XFER_SHORTPKT 28 /* Stopped before reaching end of TD */ 446 #define XHCI_CODE_MELAT 29 /* Max Exit Latency too large */ 447 #define XHCI_CODE_RESERVED 30 448 #define XHCI_CODE_ISOC_OVERRUN 31 /* IN data buffer < Max ESIT Payload */ 449 #define XHCI_CODE_EVENT_LOST 32 /* Internal overrun - impl. specific */ 450 #define XHCI_CODE_UNDEFINED 33 /* Fatal error - impl. specific */ 451 #define XHCI_CODE_INVALID_SID 34 /* Invalid stream ID received */ 452 #define XHCI_CODE_SEC_BW 35 /* Cannot alloc secondary BW Domain */ 453 #define XHCI_CODE_SPLITERR 36 /* USB2 split transaction */ 454 455 #endif /* _XHCIREG_H_ */ 456