1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_REG_DEFS_H__ 7 #define __INTEL_DISPLAY_REG_DEFS_H__ 8 9 #include "i915_reg_defs.h" 10 11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset) 12 13 #define VLV_DISPLAY_BASE 0x180000 14 15 /* 16 * Named helper wrappers around _PICK_EVEN() and _PICK_EVEN_2RANGES(). 17 */ 18 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) 19 #define _PLANE(plane, a, b) _PICK_EVEN(plane, a, b) 20 #define _TRANS(tran, a, b) _PICK_EVEN(tran, a, b) 21 #define _PORT(port, a, b) _PICK_EVEN(port, a, b) 22 #define _PLL(pll, a, b) _PICK_EVEN(pll, a, b) 23 #define _PHY(phy, a, b) _PICK_EVEN(phy, a, b) 24 25 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) 26 #define _MMIO_PLANE(plane, a, b) _MMIO(_PLANE(plane, a, b)) 27 #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) 28 #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) 29 #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) 30 #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) 31 32 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 33 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) 34 35 /* 36 * Device info offset array based helpers for groups of registers with unevenly 37 * spaced base offsets. 38 */ 39 #define _MMIO_PIPE2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->pipe_offsets[(pipe)] - \ 40 DISPLAY_INFO(dev_priv)->pipe_offsets[PIPE_A] + \ 41 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 42 #define _MMIO_TRANS2(tran, reg) _MMIO(DISPLAY_INFO(dev_priv)->trans_offsets[(tran)] - \ 43 DISPLAY_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + \ 44 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 45 #define _MMIO_CURSOR2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->cursor_offsets[(pipe)] - \ 46 DISPLAY_INFO(dev_priv)->cursor_offsets[PIPE_A] + \ 47 DISPLAY_MMIO_BASE(dev_priv) + (reg)) 48 49 #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */ 50