1 2module example001(a, y); 3 4input [15:0] a; 5output y; 6 7wire gt = a > 12345; 8wire lt = a < 12345; 9assign y = !gt && !lt; 10 11endmodule 12 13// ------------------------------------ 14 15module example002(a, y); 16 17input [3:0] a; 18output y; 19reg [1:0] t1, t2; 20 21always @* begin 22 casex (a) 23 16'b1xxx: 24 t1 <= 1; 25 16'bx1xx: 26 t1 <= 2; 27 16'bxx1x: 28 t1 <= 3; 29 16'bxxx1: 30 t1 <= 4; 31 default: 32 t1 <= 0; 33 endcase 34 casex (a) 35 16'b1xxx: 36 t2 <= 1; 37 16'b01xx: 38 t2 <= 2; 39 16'b001x: 40 t2 <= 3; 41 16'b0001: 42 t2 <= 4; 43 default: 44 t2 <= 0; 45 endcase 46end 47 48assign y = t1 != t2; 49 50endmodule 51 52// ------------------------------------ 53 54module example003(a_shl, a_shr, a_sshl, a_sshr, sh, y_shl, y_shr, y_sshl, y_sshr); 55 56input [7:0] a_shl, a_shr; 57input signed [7:0] a_sshl, a_sshr; 58input [3:0] sh; 59 60output [7:0] y_shl = a_shl << sh, y_shr = a_shr >> sh; 61output signed [7:0] y_sshl = a_sshl <<< sh, y_sshr = a_sshr >>> sh; 62 63endmodule 64 65// ------------------------------------ 66 67module example004(clk, rst, y); 68 69input clk, rst; 70output y; 71 72reg [3:0] counter; 73 74always @(posedge clk) 75 case (1'b1) 76 rst, counter == 9: 77 counter <= 0; 78 default: 79 counter <= counter+1; 80 endcase 81 82assign y = counter == 12; 83 84endmodule 85 86