1 #ifndef INCLUDE_SHARED_MEMORY 2 #define INCLUDE_SHARED_MEMORY 3 4 #include "cleantyp.h" 5 6 #define VRAMSIZE 0x10000 7 8 #define PSG_DIRECT_ACCESS_BUFSIZE 1024 9 10 #define SHM_HANDLE 0x25679 11 #define SHM_ROM_HANDLE 0x25680 12 13 typedef union 14 { 15 #if defined(WORDS_BIGENDIAN) 16 struct { UChar h,l; } B; 17 #else 18 struct { UChar l,h; } B; 19 #endif 20 UInt16 W; 21 } pair; 22 23 /* The structure containing all variables relatives to Input and Output */ 24 typedef struct tagIO { 25 /* VCE */ 26 pair VCE[0x200]; /* palette info */ 27 pair vce_reg; /* currently selected color */ 28 UChar vce_ratch; /* temporary value to keep track of the first byte 29 * when setting a 16 bits value with two byte access 30 */ 31 /* VDC */ 32 pair VDC[32]; /* value of each VDC register */ 33 UInt16 vdc_inc; /* VRAM pointer increment once accessed */ 34 UInt16 vdc_raster_count; /* unused as far as I know */ 35 UChar vdc_reg; /* currently selected VDC register */ 36 UChar vdc_status; /* current VCD status (end of line, end of screen, ...) */ 37 UChar vdc_ratch; /* temporary value to keep track of the first byte 38 * when setting a 16 bits value with two byte access 39 */ 40 UChar vdc_satb; /* boolean which keeps track of the need to copy 41 * the SATB from VRAM to internal SATB 42 */ 43 UChar vdc_pendvsync; /* unsure, set if a end of screen IRQ is waiting */ 44 Int32 bg_h; /* number of tiles vertically in virtual screen */ 45 Int32 bg_w; /* number of tiles horizontaly in virtual screen */ 46 Int32 screen_w; /* size of real screen in pixels */ 47 Int32 screen_h; /* size of real screen in pixels */ 48 Int32 scroll_y; 49 Int32 minline; 50 Int32 maxline; 51 52 UInt16 vdc_min_display; // First scanline of active display 53 UInt16 vdc_max_display; // Last scanline of active display 54 55 /* joypad */ 56 UChar JOY[16]; /* value of pressed button/direct for each pad 57 * (why 16 ? 5 should be enough for everyone :) 58 */ 59 UChar joy_select; /* used to know what nibble we must return */ 60 UChar joy_counter; /* current addressed joypad */ 61 62 /* PSG */ 63 UChar PSG[6][8], wave[6][32]; 64 // PSG STRUCTURE 65 // 0 : dda_out 66 // 2 : freq (lo byte) | In reality it's a divisor 67 // 3 : freq (hi byte) | 3.7 Mhz / freq => true snd freq 68 // 4 : dda_ctrl 69 // 000XXXXX 70 // ^^ ^ 71 // || ch. volume 72 // || 73 // |direct access (everything at byte 0) 74 // | 75 // enable 76 // 5 : pan (left vol = hi nibble, right vol = low nibble) 77 // 6 : wave ringbuffer index 78 // 7 : noise data for channels 5 and 6 79 80 UChar psg_ch,psg_volume,psg_lfo_freq,psg_lfo_ctrl; 81 82 UChar psg_da_data[6][PSG_DIRECT_ACCESS_BUFSIZE]; 83 UInt16 psg_da_index[6], psg_da_count[6]; 84 boolean psg_channel_disabled[6]; 85 86 /* TIMER */ 87 UChar timer_reload,timer_start,timer_counter; 88 89 /* IRQ */ 90 UChar irq_mask,irq_status; 91 92 /* CDROM extention */ 93 SInt32 backup,adpcm_firstread; 94 UChar cd_port_1800; 95 UChar cd_port_1801; 96 UChar cd_port_1802; 97 UChar cd_port_1804; 98 99 /* Adpcm related variables */ 100 pair adpcm_ptr; 101 UInt16 adpcm_rptr,adpcm_wptr; 102 UInt16 adpcm_dmaptr; 103 UChar adpcm_rate; 104 UInt32 adpcm_pptr; /* to know where to begin playing adpcm (in nibbles) */ 105 UInt32 adpcm_psize; /* to know how many 4-bit samples to play */ 106 107 /* Arcade Card variables */ 108 UInt32 ac_base[4]; /* base address for AC ram accessing */ 109 UInt16 ac_offset[4]; /* offset address for AC ram accessing */ 110 UInt16 ac_incr[4]; /* incrment value after read or write accordingly to the control bit */ 111 112 UChar ac_control[4]; /* bit 7: unused 113 * bit 6: only $1AX6 hits will add offset to base 114 * bit 5 + bit 6: either hit to $1AX6 or $1AXA will add offset to base 115 * bit 4: auto increment offset if 0, and auto 116 * increment base if 1 117 * bit 3: unknown 118 * bit 2: unknown 119 * bit 1: use offset address in the effective address 120 * computation 121 * bit 0: apply autoincrement if set 122 */ 123 UInt32 ac_shift; 124 UChar ac_shiftbits; /* number of bits to shift by */ 125 126 /* UChar ac_unknown3; */ 127 UChar ac_unknown4; 128 129 /* Remanence latch */ 130 UChar io_buffer; 131 132 } IO; 133 134 typedef struct { 135 UChar RAM[0x8000]; 136 UChar PCM[0x10000]; 137 UChar WRAM[0x2000]; 138 UChar VRAM[VRAMSIZE]; 139 140 UChar VRAM2[VRAMSIZE]; 141 UChar VRAMS[VRAMSIZE]; 142 UChar vchange[VRAMSIZE / 32]; 143 UChar vchanges[VRAMSIZE / 128]; 144 145 UChar cd_extra_mem[0x10000]; 146 UChar cd_extra_super_mem[0x30000]; 147 UChar ac_extra_mem[0x200000]; 148 UChar cd_sector_buffer[0x2000]; 149 150 UInt32 s_scanline; 151 152 UInt16 SPRAM[64 * 4]; 153 UChar Pal[512]; 154 155 UInt16 s_reg_pc; 156 UChar s_reg_a; 157 UChar s_reg_x; 158 UChar s_reg_y; 159 UChar s_reg_p; 160 UChar s_reg_s; 161 162 UInt32 s_cyclecount; 163 UInt32 s_cyclecountold; 164 165 UInt32 s_cycles; 166 167 SInt32 s_external_control_cpu; 168 169 UChar mmr[8]; 170 171 IO s_io; 172 173 UInt32 rom_shared_memory_size; 174 175 } struct_hard_pce; 176 177 #endif 178