1 /*-
2 * Product specific probe and attach routines for:
3 * 3940, 2940, aic7895, aic7890, aic7880,
4 * aic7870, aic7860 and aic7850 SCSI controllers
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 *
8 * Copyright (c) 1994-2001 Justin T. Gibbs.
9 * Copyright (c) 2000-2001 Adaptec Inc.
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * substantially similar to the "NO WARRANTY" disclaimer below
20 * ("Disclaimer") and any redistribution must be conditioned upon
21 * including a substantially similar Disclaimer requirement for further
22 * binary redistribution.
23 * 3. Neither the names of the above-listed copyright holders nor the names
24 * of any contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * Alternatively, this software may be distributed under the terms of the
28 * GNU General Public License ("GPL") version 2 as published by the Free
29 * Software Foundation.
30 *
31 * NO WARRANTY
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
35 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
36 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
41 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
42 * POSSIBILITY OF SUCH DAMAGES.
43 *
44 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#78 $
45 */
46
47 #include <dev/aic7xxx/aic7xxx_osm.h>
48 #include <dev/aic7xxx/aic7xxx_inline.h>
49 #include <dev/aic7xxx/aic7xxx_93cx6.h>
50
51 static __inline uint64_t
ahc_compose_id(u_int device,u_int vendor,u_int subdevice,u_int subvendor)52 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
53 {
54 uint64_t id;
55
56 id = subvendor
57 | (subdevice << 16)
58 | ((uint64_t)vendor << 32)
59 | ((uint64_t)device << 48);
60
61 return (id);
62 }
63
64 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
65 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
66 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
67 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
68 #define ID_9005_SISL_ID 0x0005900500000000ull
69 #define ID_AIC7850 0x5078900400000000ull
70 #define ID_AHA_2902_04_10_15_20C_30C 0x5078900478509004ull
71 #define ID_AIC7855 0x5578900400000000ull
72 #define ID_AIC7859 0x3860900400000000ull
73 #define ID_AHA_2930CU 0x3860900438699004ull
74 #define ID_AIC7860 0x6078900400000000ull
75 #define ID_AIC7860C 0x6078900478609004ull
76 #define ID_AHA_1480A 0x6075900400000000ull
77 #define ID_AHA_2940AU_0 0x6178900400000000ull
78 #define ID_AHA_2940AU_1 0x6178900478619004ull
79 #define ID_AHA_2940AU_CN 0x2178900478219004ull
80 #define ID_AHA_2930C_VAR 0x6038900438689004ull
81
82 #define ID_AIC7870 0x7078900400000000ull
83 #define ID_AHA_2940 0x7178900400000000ull
84 #define ID_AHA_3940 0x7278900400000000ull
85 #define ID_AHA_398X 0x7378900400000000ull
86 #define ID_AHA_2944 0x7478900400000000ull
87 #define ID_AHA_3944 0x7578900400000000ull
88 #define ID_AHA_4944 0x7678900400000000ull
89
90 #define ID_AIC7880 0x8078900400000000ull
91 #define ID_AIC7880_B 0x8078900478809004ull
92 #define ID_AHA_2940U 0x8178900400000000ull
93 #define ID_AHA_3940U 0x8278900400000000ull
94 #define ID_AHA_2944U 0x8478900400000000ull
95 #define ID_AHA_3944U 0x8578900400000000ull
96 #define ID_AHA_398XU 0x8378900400000000ull
97 #define ID_AHA_4944U 0x8678900400000000ull
98 #define ID_AHA_2940UB 0x8178900478819004ull
99 #define ID_AHA_2930U 0x8878900478889004ull
100 #define ID_AHA_2940U_PRO 0x8778900478879004ull
101 #define ID_AHA_2940U_CN 0x0078900478009004ull
102
103 #define ID_AIC7895 0x7895900478959004ull
104 #define ID_AIC7895_ARO 0x7890900478939004ull
105 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
106 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
107 #define ID_AHA_3940AU 0x7895900478929004ull
108 #define ID_AHA_3944AU 0x7895900478949004ull
109
110 #define ID_AIC7890 0x001F9005000F9005ull
111 #define ID_AIC7890_ARO 0x00139005000F9005ull
112 #define ID_AAA_131U2 0x0013900500039005ull
113 #define ID_AHA_2930U2 0x0011900501819005ull
114 #define ID_AHA_2940U2B 0x00109005A1009005ull
115 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
116 #define ID_AHA_2940U2 0x00109005A1809005ull
117 #define ID_AHA_2950U2B 0x00109005E1009005ull
118
119 #define ID_AIC7892 0x008F9005FFFF9005ull
120 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
121 #define ID_AHA_29160 0x00809005E2A09005ull
122 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
123 #define ID_AHA_29160N 0x0080900562A09005ull
124 #define ID_AHA_29160C 0x0080900562209005ull
125 #define ID_AHA_29160B 0x00809005E2209005ull
126 #define ID_AHA_19160B 0x0081900562A19005ull
127 #define ID_AHA_2915_30LP 0x0082900502109005ull
128
129 #define ID_AIC7896 0x005F9005FFFF9005ull
130 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
131 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
132 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
133 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
134 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
135
136 #define ID_AIC7899 0x00CF9005FFFF9005ull
137 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
138 #define ID_AHA_3960D 0x00C09005F6209005ull
139 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
140
141 #define ID_AIC7810 0x1078900400000000ull
142 #define ID_AIC7815 0x7815900400000000ull
143
144 #define DEVID_9005_TYPE(id) ((id) & 0xF)
145 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
146 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
147 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
148 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
149
150 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
151 #define DEVID_9005_MAXRATE_U160 0x0
152 #define DEVID_9005_MAXRATE_ULTRA2 0x1
153 #define DEVID_9005_MAXRATE_ULTRA 0x2
154 #define DEVID_9005_MAXRATE_FAST 0x3
155
156 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
157
158 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
159 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
160
161 #define SUBID_9005_TYPE(id) ((id) & 0xF)
162 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
163 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
164 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
165 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
166
167 #define SUBID_9005_TYPE_KNOWN(id) \
168 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
169 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
170 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
171 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
172
173 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
174 #define SUBID_9005_MAXRATE_ULTRA2 0x0
175 #define SUBID_9005_MAXRATE_ULTRA 0x1
176 #define SUBID_9005_MAXRATE_U160 0x2
177 #define SUBID_9005_MAXRATE_RESERVED 0x3
178
179 #define SUBID_9005_SEEPTYPE(id) \
180 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
181 ? ((id) & 0xC0) >> 6 \
182 : ((id) & 0x300) >> 8)
183 #define SUBID_9005_SEEPTYPE_NONE 0x0
184 #define SUBID_9005_SEEPTYPE_1K 0x1
185 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
186 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
187 #define SUBID_9005_AUTOTERM(id) \
188 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
189 ? (((id) & 0x400) >> 10) == 0 \
190 : (((id) & 0x40) >> 6) == 0)
191
192 #define SUBID_9005_NUMCHAN(id) \
193 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
194 ? ((id) & 0x300) >> 8 \
195 : ((id) & 0xC00) >> 10)
196
197 #define SUBID_9005_LEGACYCONN(id) \
198 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
199 ? 0 \
200 : ((id) & 0x80) >> 7)
201
202 #define SUBID_9005_MFUNCENB(id) \
203 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
204 ? ((id) & 0x800) >> 11 \
205 : ((id) & 0x1000) >> 12)
206 /*
207 * Informational only. Should use chip register to be
208 * certain, but may be use in identification strings.
209 */
210 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
211 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
212 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
213
214 static ahc_device_setup_t ahc_aic785X_setup;
215 static ahc_device_setup_t ahc_aic7860_setup;
216 static ahc_device_setup_t ahc_apa1480_setup;
217 static ahc_device_setup_t ahc_aic7870_setup;
218 static ahc_device_setup_t ahc_aha394X_setup;
219 static ahc_device_setup_t ahc_aha494X_setup;
220 static ahc_device_setup_t ahc_aha398X_setup;
221 static ahc_device_setup_t ahc_aic7880_setup;
222 static ahc_device_setup_t ahc_aha2940Pro_setup;
223 static ahc_device_setup_t ahc_aha394XU_setup;
224 static ahc_device_setup_t ahc_aha398XU_setup;
225 static ahc_device_setup_t ahc_aic7890_setup;
226 static ahc_device_setup_t ahc_aic7892_setup;
227 static ahc_device_setup_t ahc_aic7895_setup;
228 static ahc_device_setup_t ahc_aic7896_setup;
229 static ahc_device_setup_t ahc_aic7899_setup;
230 static ahc_device_setup_t ahc_aha29160C_setup;
231 static ahc_device_setup_t ahc_raid_setup;
232 static ahc_device_setup_t ahc_aha394XX_setup;
233 static ahc_device_setup_t ahc_aha494XX_setup;
234 static ahc_device_setup_t ahc_aha398XX_setup;
235
236 struct ahc_pci_identity ahc_pci_ident_table [] =
237 {
238 /* aic7850 based controllers */
239 {
240 ID_AHA_2902_04_10_15_20C_30C,
241 ID_ALL_MASK,
242 "Adaptec 2902/04/10/15/20C/30C SCSI adapter",
243 ahc_aic785X_setup
244 },
245 /* aic7860 based controllers */
246 {
247 ID_AHA_2930CU,
248 ID_ALL_MASK,
249 "Adaptec 2930CU SCSI adapter",
250 ahc_aic7860_setup
251 },
252 {
253 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
254 ID_DEV_VENDOR_MASK,
255 "Adaptec 1480A Ultra SCSI adapter",
256 ahc_apa1480_setup
257 },
258 {
259 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
260 ID_DEV_VENDOR_MASK,
261 "Adaptec 2940A Ultra SCSI adapter",
262 ahc_aic7860_setup
263 },
264 {
265 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
266 ID_DEV_VENDOR_MASK,
267 "Adaptec 2940A/CN Ultra SCSI adapter",
268 ahc_aic7860_setup
269 },
270 {
271 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
272 ID_DEV_VENDOR_MASK,
273 "Adaptec 2930C Ultra SCSI adapter (VAR)",
274 ahc_aic7860_setup
275 },
276 /* aic7870 based controllers */
277 {
278 ID_AHA_2940,
279 ID_ALL_MASK,
280 "Adaptec 2940 SCSI adapter",
281 ahc_aic7870_setup
282 },
283 {
284 ID_AHA_3940,
285 ID_ALL_MASK,
286 "Adaptec 3940 SCSI adapter",
287 ahc_aha394X_setup
288 },
289 {
290 ID_AHA_398X,
291 ID_ALL_MASK,
292 "Adaptec 398X SCSI RAID adapter",
293 ahc_aha398X_setup
294 },
295 {
296 ID_AHA_2944,
297 ID_ALL_MASK,
298 "Adaptec 2944 SCSI adapter",
299 ahc_aic7870_setup
300 },
301 {
302 ID_AHA_3944,
303 ID_ALL_MASK,
304 "Adaptec 3944 SCSI adapter",
305 ahc_aha394X_setup
306 },
307 {
308 ID_AHA_4944,
309 ID_ALL_MASK,
310 "Adaptec 4944 SCSI adapter",
311 ahc_aha494X_setup
312 },
313 /* aic7880 based controllers */
314 {
315 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
316 ID_DEV_VENDOR_MASK,
317 "Adaptec 2940 Ultra SCSI adapter",
318 ahc_aic7880_setup
319 },
320 {
321 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
322 ID_DEV_VENDOR_MASK,
323 "Adaptec 3940 Ultra SCSI adapter",
324 ahc_aha394XU_setup
325 },
326 {
327 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
328 ID_DEV_VENDOR_MASK,
329 "Adaptec 2944 Ultra SCSI adapter",
330 ahc_aic7880_setup
331 },
332 {
333 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
334 ID_DEV_VENDOR_MASK,
335 "Adaptec 3944 Ultra SCSI adapter",
336 ahc_aha394XU_setup
337 },
338 {
339 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
340 ID_DEV_VENDOR_MASK,
341 "Adaptec 398X Ultra SCSI RAID adapter",
342 ahc_aha398XU_setup
343 },
344 {
345 /*
346 * XXX Don't know the slot numbers
347 * so we can't identify channels
348 */
349 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
350 ID_DEV_VENDOR_MASK,
351 "Adaptec 4944 Ultra SCSI adapter",
352 ahc_aic7880_setup
353 },
354 {
355 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
356 ID_DEV_VENDOR_MASK,
357 "Adaptec 2930 Ultra SCSI adapter",
358 ahc_aic7880_setup
359 },
360 {
361 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
362 ID_DEV_VENDOR_MASK,
363 "Adaptec 2940 Pro Ultra SCSI adapter",
364 ahc_aha2940Pro_setup
365 },
366 {
367 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
368 ID_DEV_VENDOR_MASK,
369 "Adaptec 2940/CN Ultra SCSI adapter",
370 ahc_aic7880_setup
371 },
372 /* Ignore all SISL (AAC on MB) based controllers. */
373 {
374 ID_9005_SISL_ID,
375 ID_9005_SISL_MASK,
376 NULL,
377 NULL
378 },
379 /* aic7890 based controllers */
380 {
381 ID_AHA_2930U2,
382 ID_ALL_MASK,
383 "Adaptec 2930 Ultra2 SCSI adapter",
384 ahc_aic7890_setup
385 },
386 {
387 ID_AHA_2940U2B,
388 ID_ALL_MASK,
389 "Adaptec 2940B Ultra2 SCSI adapter",
390 ahc_aic7890_setup
391 },
392 {
393 ID_AHA_2940U2_OEM,
394 ID_ALL_MASK,
395 "Adaptec 2940 Ultra2 SCSI adapter (OEM)",
396 ahc_aic7890_setup
397 },
398 {
399 ID_AHA_2940U2,
400 ID_ALL_MASK,
401 "Adaptec 2940 Ultra2 SCSI adapter",
402 ahc_aic7890_setup
403 },
404 {
405 ID_AHA_2950U2B,
406 ID_ALL_MASK,
407 "Adaptec 2950 Ultra2 SCSI adapter",
408 ahc_aic7890_setup
409 },
410 {
411 ID_AIC7890_ARO,
412 ID_ALL_MASK,
413 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)",
414 ahc_aic7890_setup
415 },
416 {
417 ID_AAA_131U2,
418 ID_ALL_MASK,
419 "Adaptec AAA-131 Ultra2 RAID adapter",
420 ahc_aic7890_setup
421 },
422 /* aic7892 based controllers */
423 {
424 ID_AHA_29160,
425 ID_ALL_MASK,
426 "Adaptec 29160 Ultra160 SCSI adapter",
427 ahc_aic7892_setup
428 },
429 {
430 ID_AHA_29160_CPQ,
431 ID_ALL_MASK,
432 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter",
433 ahc_aic7892_setup
434 },
435 {
436 ID_AHA_29160N,
437 ID_ALL_MASK,
438 "Adaptec 29160N Ultra160 SCSI adapter",
439 ahc_aic7892_setup
440 },
441 {
442 ID_AHA_29160C,
443 ID_ALL_MASK,
444 "Adaptec 29160C Ultra160 SCSI adapter",
445 ahc_aha29160C_setup
446 },
447 {
448 ID_AHA_29160B,
449 ID_ALL_MASK,
450 "Adaptec 29160B Ultra160 SCSI adapter",
451 ahc_aic7892_setup
452 },
453 {
454 ID_AHA_19160B,
455 ID_ALL_MASK,
456 "Adaptec 19160B Ultra160 SCSI adapter",
457 ahc_aic7892_setup
458 },
459 {
460 ID_AIC7892_ARO,
461 ID_ALL_MASK,
462 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)",
463 ahc_aic7892_setup
464 },
465 {
466 ID_AHA_2915_30LP,
467 ID_ALL_MASK,
468 "Adaptec 2915/30LP Ultra160 SCSI adapter",
469 ahc_aic7892_setup
470 },
471 /* aic7895 based controllers */
472 {
473 ID_AHA_2940U_DUAL,
474 ID_ALL_MASK,
475 "Adaptec 2940/DUAL Ultra SCSI adapter",
476 ahc_aic7895_setup
477 },
478 {
479 ID_AHA_3940AU,
480 ID_ALL_MASK,
481 "Adaptec 3940A Ultra SCSI adapter",
482 ahc_aic7895_setup
483 },
484 {
485 ID_AHA_3944AU,
486 ID_ALL_MASK,
487 "Adaptec 3944A Ultra SCSI adapter",
488 ahc_aic7895_setup
489 },
490 {
491 ID_AIC7895_ARO,
492 ID_AIC7895_ARO_MASK,
493 "Adaptec aic7895 Ultra SCSI adapter (ARO)",
494 ahc_aic7895_setup
495 },
496 /* aic7896/97 based controllers */
497 {
498 ID_AHA_3950U2B_0,
499 ID_ALL_MASK,
500 "Adaptec 3950B Ultra2 SCSI adapter",
501 ahc_aic7896_setup
502 },
503 {
504 ID_AHA_3950U2B_1,
505 ID_ALL_MASK,
506 "Adaptec 3950B Ultra2 SCSI adapter",
507 ahc_aic7896_setup
508 },
509 {
510 ID_AHA_3950U2D_0,
511 ID_ALL_MASK,
512 "Adaptec 3950D Ultra2 SCSI adapter",
513 ahc_aic7896_setup
514 },
515 {
516 ID_AHA_3950U2D_1,
517 ID_ALL_MASK,
518 "Adaptec 3950D Ultra2 SCSI adapter",
519 ahc_aic7896_setup
520 },
521 {
522 ID_AIC7896_ARO,
523 ID_ALL_MASK,
524 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)",
525 ahc_aic7896_setup
526 },
527 /* aic7899 based controllers */
528 {
529 ID_AHA_3960D,
530 ID_ALL_MASK,
531 "Adaptec 3960D Ultra160 SCSI adapter",
532 ahc_aic7899_setup
533 },
534 {
535 ID_AHA_3960D_CPQ,
536 ID_ALL_MASK,
537 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter",
538 ahc_aic7899_setup
539 },
540 {
541 ID_AIC7899_ARO,
542 ID_ALL_MASK,
543 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)",
544 ahc_aic7899_setup
545 },
546 /* Generic chip probes for devices we don't know 'exactly' */
547 {
548 ID_AIC7850 & ID_DEV_VENDOR_MASK,
549 ID_DEV_VENDOR_MASK,
550 "Adaptec aic7850 SCSI adapter",
551 ahc_aic785X_setup
552 },
553 {
554 ID_AIC7855 & ID_DEV_VENDOR_MASK,
555 ID_DEV_VENDOR_MASK,
556 "Adaptec aic7855 SCSI adapter",
557 ahc_aic785X_setup
558 },
559 {
560 ID_AIC7859 & ID_DEV_VENDOR_MASK,
561 ID_DEV_VENDOR_MASK,
562 "Adaptec aic7859 SCSI adapter",
563 ahc_aic7860_setup
564 },
565 {
566 ID_AIC7860 & ID_DEV_VENDOR_MASK,
567 ID_DEV_VENDOR_MASK,
568 "Adaptec aic7860 Ultra SCSI adapter",
569 ahc_aic7860_setup
570 },
571 {
572 ID_AIC7870 & ID_DEV_VENDOR_MASK,
573 ID_DEV_VENDOR_MASK,
574 "Adaptec aic7870 SCSI adapter",
575 ahc_aic7870_setup
576 },
577 {
578 ID_AIC7880 & ID_DEV_VENDOR_MASK,
579 ID_DEV_VENDOR_MASK,
580 "Adaptec aic7880 Ultra SCSI adapter",
581 ahc_aic7880_setup
582 },
583 {
584 ID_AIC7890 & ID_9005_GENERIC_MASK,
585 ID_9005_GENERIC_MASK,
586 "Adaptec aic7890/91 Ultra2 SCSI adapter",
587 ahc_aic7890_setup
588 },
589 {
590 ID_AIC7892 & ID_9005_GENERIC_MASK,
591 ID_9005_GENERIC_MASK,
592 "Adaptec aic7892 Ultra160 SCSI adapter",
593 ahc_aic7892_setup
594 },
595 {
596 ID_AIC7895 & ID_DEV_VENDOR_MASK,
597 ID_DEV_VENDOR_MASK,
598 "Adaptec aic7895 Ultra SCSI adapter",
599 ahc_aic7895_setup
600 },
601 {
602 ID_AIC7896 & ID_9005_GENERIC_MASK,
603 ID_9005_GENERIC_MASK,
604 "Adaptec aic7896/97 Ultra2 SCSI adapter",
605 ahc_aic7896_setup
606 },
607 {
608 ID_AIC7899 & ID_9005_GENERIC_MASK,
609 ID_9005_GENERIC_MASK,
610 "Adaptec aic7899 Ultra160 SCSI adapter",
611 ahc_aic7899_setup
612 },
613 {
614 ID_AIC7810 & ID_DEV_VENDOR_MASK,
615 ID_DEV_VENDOR_MASK,
616 "Adaptec aic7810 RAID memory controller",
617 ahc_raid_setup
618 },
619 {
620 ID_AIC7815 & ID_DEV_VENDOR_MASK,
621 ID_DEV_VENDOR_MASK,
622 "Adaptec aic7815 RAID memory controller",
623 ahc_raid_setup
624 }
625 };
626
627 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table);
628
629 #define AHC_394X_SLOT_CHANNEL_A 4
630 #define AHC_394X_SLOT_CHANNEL_B 5
631
632 #define AHC_398X_SLOT_CHANNEL_A 4
633 #define AHC_398X_SLOT_CHANNEL_B 8
634 #define AHC_398X_SLOT_CHANNEL_C 12
635
636 #define AHC_494X_SLOT_CHANNEL_A 4
637 #define AHC_494X_SLOT_CHANNEL_B 5
638 #define AHC_494X_SLOT_CHANNEL_C 6
639 #define AHC_494X_SLOT_CHANNEL_D 7
640
641 #define DEVCONFIG 0x40
642 #define PCIERRGENDIS 0x80000000ul
643 #define SCBSIZE32 0x00010000ul /* aic789X only */
644 #define REXTVALID 0x00001000ul /* ultra cards only */
645 #define MPORTMODE 0x00000400ul /* aic7870+ only */
646 #define RAMPSM 0x00000200ul /* aic7870+ only */
647 #define VOLSENSE 0x00000100ul
648 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
649 #define SCBRAMSEL 0x00000080ul
650 #define MRDCEN 0x00000040ul
651 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
652 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
653 #define BERREN 0x00000008ul
654 #define DACEN 0x00000004ul
655 #define STPWLEVEL 0x00000002ul
656 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
657
658 #define CSIZE_LATTIME 0x0c
659 #define CACHESIZE 0x0000003ful /* only 5 bits */
660 #define LATTIME 0x0000ff00ul
661
662 /* PCI STATUS definitions */
663 #define DPE 0x80
664 #define SSE 0x40
665 #define RMA 0x20
666 #define RTA 0x10
667 #define STA 0x08
668 #define DPR 0x01
669
670 static int ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
671 uint16_t subdevice, uint16_t subvendor);
672 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
673 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
674 int pcheck, int fast, int large);
675 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
676 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
677 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc,
678 struct seeprom_config *sc);
679 static void configure_termination(struct ahc_softc *ahc,
680 struct seeprom_descriptor *sd,
681 u_int adapter_control,
682 u_int *sxfrctl1);
683
684 static void ahc_new_term_detect(struct ahc_softc *ahc,
685 int *enableSEC_low,
686 int *enableSEC_high,
687 int *enablePRI_low,
688 int *enablePRI_high,
689 int *eeprom_present);
690 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
691 int *internal68_present,
692 int *externalcable_present,
693 int *eeprom_present);
694 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
695 int *externalcable_present,
696 int *eeprom_present);
697 static void write_brdctl(struct ahc_softc *ahc, uint8_t value);
698 static uint8_t read_brdctl(struct ahc_softc *ahc);
699 static void ahc_pci_intr(struct ahc_softc *ahc);
700 static int ahc_pci_chip_init(struct ahc_softc *ahc);
701 static int ahc_pci_suspend(struct ahc_softc *ahc);
702 static int ahc_pci_resume(struct ahc_softc *ahc);
703
704 static int
ahc_9005_subdevinfo_valid(uint16_t device,uint16_t vendor,uint16_t subdevice,uint16_t subvendor)705 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
706 uint16_t subdevice, uint16_t subvendor)
707 {
708 int result;
709
710 /* Default to invalid. */
711 result = 0;
712 if (vendor == 0x9005
713 && subvendor == 0x9005
714 && subdevice != device
715 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
716 switch (SUBID_9005_TYPE(subdevice)) {
717 case SUBID_9005_TYPE_MB:
718 break;
719 case SUBID_9005_TYPE_CARD:
720 case SUBID_9005_TYPE_LCCARD:
721 /*
722 * Currently only trust Adaptec cards to
723 * get the sub device info correct.
724 */
725 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
726 result = 1;
727 break;
728 case SUBID_9005_TYPE_RAID:
729 break;
730 default:
731 break;
732 }
733 }
734 return (result);
735 }
736
737 struct ahc_pci_identity *
ahc_find_pci_device(aic_dev_softc_t pci)738 ahc_find_pci_device(aic_dev_softc_t pci)
739 {
740 uint64_t full_id;
741 uint16_t device;
742 uint16_t vendor;
743 uint16_t subdevice;
744 uint16_t subvendor;
745 struct ahc_pci_identity *entry;
746 u_int i;
747
748 vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
749 device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
750 subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
751 subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
752 full_id = ahc_compose_id(device, vendor, subdevice, subvendor);
753
754 /*
755 * If the second function is not hooked up, ignore it.
756 * Unfortunately, not all MB vendors implement the
757 * subdevice ID as per the Adaptec spec, so do our best
758 * to sanity check it prior to accepting the subdevice
759 * ID as valid.
760 */
761 if (aic_get_pci_function(pci) > 0
762 && ahc_9005_subdevinfo_valid(device, vendor, subdevice, subvendor)
763 && SUBID_9005_MFUNCENB(subdevice) == 0)
764 return (NULL);
765
766 for (i = 0; i < ahc_num_pci_devs; i++) {
767 entry = &ahc_pci_ident_table[i];
768 if (entry->full_id == (full_id & entry->id_mask)) {
769 /* Honor exclusion entries. */
770 if (entry->name == NULL)
771 return (NULL);
772 return (entry);
773 }
774 }
775 return (NULL);
776 }
777
778 int
ahc_pci_config(struct ahc_softc * ahc,struct ahc_pci_identity * entry)779 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry)
780 {
781 u_int command;
782 u_int our_id;
783 u_int sxfrctl1;
784 u_int scsiseq;
785 u_int dscommand0;
786 uint32_t devconfig;
787 int error;
788 uint8_t sblkctl;
789
790 our_id = 0;
791 error = entry->setup(ahc);
792 if (error != 0)
793 return (error);
794 ahc->chip |= AHC_PCI;
795 ahc->description = entry->name;
796
797 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
798
799 error = ahc_pci_map_registers(ahc);
800 if (error != 0)
801 return (error);
802
803 /*
804 * Before we continue probing the card, ensure that
805 * its interrupts are *disabled*. We don't want
806 * a misstep to hang the machine in an interrupt
807 * storm.
808 */
809 ahc_intr_enable(ahc, FALSE);
810
811 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
812
813 /*
814 * If we need to support high memory, enable dual
815 * address cycles. This bit must be set to enable
816 * high address bit generation even if we are on a
817 * 64bit bus (PCI64BIT set in devconfig).
818 */
819 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
820 if (bootverbose)
821 printf("%s: Enabling 39Bit Addressing\n",
822 ahc_name(ahc));
823 devconfig |= DACEN;
824 }
825
826 /* Ensure that pci error generation, a test feature, is disabled. */
827 devconfig |= PCIERRGENDIS;
828
829 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
830
831 /* Ensure busmastering is enabled */
832 command = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
833 command |= PCIM_CMD_BUSMASTEREN;
834
835 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
836
837 /* On all PCI adapters, we allow SCB paging */
838 ahc->flags |= AHC_PAGESCBS;
839
840 error = ahc_softc_init(ahc);
841 if (error != 0)
842 return (error);
843
844 /*
845 * Disable PCI parity error checking. Users typically
846 * do this to work around broken PCI chipsets that get
847 * the parity timing wrong and thus generate lots of spurious
848 * errors. The chip only allows us to disable *all* parity
849 * error reporting when doing this, so CIO bus, scb ram, and
850 * scratch ram parity errors will be ignored too.
851 */
852 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0)
853 ahc->seqctl |= FAILDIS;
854
855 ahc->bus_intr = ahc_pci_intr;
856 ahc->bus_chip_init = ahc_pci_chip_init;
857 ahc->bus_suspend = ahc_pci_suspend;
858 ahc->bus_resume = ahc_pci_resume;
859
860 /* Remember how the card was setup in case there is no SEEPROM */
861 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
862 ahc_pause(ahc);
863 if ((ahc->features & AHC_ULTRA2) != 0)
864 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
865 else
866 our_id = ahc_inb(ahc, SCSIID) & OID;
867 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
868 scsiseq = ahc_inb(ahc, SCSISEQ);
869 } else {
870 sxfrctl1 = STPWEN;
871 our_id = 7;
872 scsiseq = 0;
873 }
874
875 error = ahc_reset(ahc, /*reinit*/FALSE);
876 if (error != 0)
877 return (ENXIO);
878
879 if ((ahc->features & AHC_DT) != 0) {
880 u_int sfunct;
881
882 /* Perform ALT-Mode Setup */
883 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
884 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
885 ahc_outb(ahc, OPTIONMODE,
886 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
887 ahc_outb(ahc, SFUNCT, sfunct);
888
889 /* Normal mode setup */
890 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
891 |TARGCRCENDEN);
892 }
893
894 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
895 dscommand0 |= MPARCKEN|CACHETHEN;
896 if ((ahc->features & AHC_ULTRA2) != 0) {
897 /*
898 * DPARCKEN doesn't work correctly on
899 * some MBs so don't use it.
900 */
901 dscommand0 &= ~DPARCKEN;
902 }
903
904 /*
905 * Handle chips that must have cache line
906 * streaming (dis/en)abled.
907 */
908 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
909 dscommand0 |= CACHETHEN;
910
911 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
912 dscommand0 &= ~CACHETHEN;
913
914 ahc_outb(ahc, DSCOMMAND0, dscommand0);
915
916 ahc->pci_cachesize =
917 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME,
918 /*bytes*/1) & CACHESIZE;
919 ahc->pci_cachesize *= 4;
920
921 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
922 && ahc->pci_cachesize == 4) {
923 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
924 0, /*bytes*/1);
925 ahc->pci_cachesize = 0;
926 }
927
928 /*
929 * We cannot perform ULTRA speeds without the presence
930 * of the external precision resistor.
931 */
932 if ((ahc->features & AHC_ULTRA) != 0) {
933 uint32_t devconfig;
934
935 devconfig = aic_pci_read_config(ahc->dev_softc,
936 DEVCONFIG, /*bytes*/4);
937 if ((devconfig & REXTVALID) == 0)
938 ahc->features &= ~AHC_ULTRA;
939 }
940
941 /* See if we have a SEEPROM and perform auto-term */
942 check_extport(ahc, &sxfrctl1);
943
944 /*
945 * Take the LED out of diagnostic mode
946 */
947 sblkctl = ahc_inb(ahc, SBLKCTL);
948 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
949
950 if ((ahc->features & AHC_ULTRA2) != 0) {
951 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
952 } else {
953 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
954 }
955
956 if (ahc->flags & AHC_USEDEFAULTS) {
957 /*
958 * PCI Adapter default setup
959 * Should only be used if the adapter does not have
960 * a SEEPROM.
961 */
962 /* See if someone else set us up already */
963 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
964 && scsiseq != 0) {
965 printf("%s: Using left over BIOS settings\n",
966 ahc_name(ahc));
967 ahc->flags &= ~AHC_USEDEFAULTS;
968 ahc->flags |= AHC_BIOS_ENABLED;
969 } else {
970 /*
971 * Assume only one connector and always turn
972 * on termination.
973 */
974 our_id = 0x07;
975 sxfrctl1 = STPWEN;
976 }
977 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
978
979 ahc->our_id = our_id;
980 }
981
982 /*
983 * Take a look to see if we have external SRAM.
984 * We currently do not attempt to use SRAM that is
985 * shared among multiple controllers.
986 */
987 ahc_probe_ext_scbram(ahc);
988
989 /*
990 * Record our termination setting for the
991 * generic initialization routine.
992 */
993 if ((sxfrctl1 & STPWEN) != 0)
994 ahc->flags |= AHC_TERM_ENB_A;
995
996 /*
997 * Save chip register configuration data for chip resets
998 * that occur during runtime and resume events.
999 */
1000 ahc->bus_softc.pci_softc.devconfig =
1001 aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1002 ahc->bus_softc.pci_softc.command =
1003 aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1);
1004 ahc->bus_softc.pci_softc.csize_lattime =
1005 aic_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1);
1006 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1007 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1008 if ((ahc->features & AHC_DT) != 0) {
1009 u_int sfunct;
1010
1011 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1012 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1013 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1014 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1015 ahc_outb(ahc, SFUNCT, sfunct);
1016 ahc->bus_softc.pci_softc.crccontrol1 =
1017 ahc_inb(ahc, CRCCONTROL1);
1018 }
1019 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1020 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1021
1022 if ((ahc->features & AHC_ULTRA2) != 0)
1023 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1024
1025 /* Core initialization */
1026 error = ahc_init(ahc);
1027 if (error != 0)
1028 return (error);
1029
1030 /*
1031 * Allow interrupts now that we are completely setup.
1032 */
1033 error = ahc_pci_map_int(ahc);
1034 if (error != 0)
1035 return (error);
1036
1037 ahc_lock(ahc);
1038 /*
1039 * Link this softc in with all other ahc instances.
1040 */
1041 ahc_softc_insert(ahc);
1042 ahc_unlock(ahc);
1043 return (0);
1044 }
1045
1046 /*
1047 * Test for the presence of external sram in an
1048 * "unshared" configuration.
1049 */
1050 static int
ahc_ext_scbram_present(struct ahc_softc * ahc)1051 ahc_ext_scbram_present(struct ahc_softc *ahc)
1052 {
1053 u_int chip;
1054 int ramps;
1055 int single_user;
1056 uint32_t devconfig;
1057
1058 chip = ahc->chip & AHC_CHIPID_MASK;
1059 devconfig = aic_pci_read_config(ahc->dev_softc,
1060 DEVCONFIG, /*bytes*/4);
1061 single_user = (devconfig & MPORTMODE) != 0;
1062
1063 if ((ahc->features & AHC_ULTRA2) != 0)
1064 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1065 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1066 /*
1067 * External SCBRAM arbitration is flakey
1068 * on these chips. Unfortunately this means
1069 * we don't use the extra SCB ram space on the
1070 * 3940AUW.
1071 */
1072 ramps = 0;
1073 else if (chip >= AHC_AIC7870)
1074 ramps = (devconfig & RAMPSM) != 0;
1075 else
1076 ramps = 0;
1077
1078 if (ramps && single_user)
1079 return (1);
1080 return (0);
1081 }
1082
1083 /*
1084 * Enable external scbram.
1085 */
1086 static void
ahc_scbram_config(struct ahc_softc * ahc,int enable,int pcheck,int fast,int large)1087 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1088 int fast, int large)
1089 {
1090 uint32_t devconfig;
1091
1092 if (ahc->features & AHC_MULTI_FUNC) {
1093 /*
1094 * Set the SCB Base addr (highest address bit)
1095 * depending on which channel we are.
1096 */
1097 ahc_outb(ahc, SCBBADDR, aic_get_pci_function(ahc->dev_softc));
1098 }
1099
1100 ahc->flags &= ~AHC_LSCBS_ENABLED;
1101 if (large)
1102 ahc->flags |= AHC_LSCBS_ENABLED;
1103 devconfig = aic_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4);
1104 if ((ahc->features & AHC_ULTRA2) != 0) {
1105 u_int dscommand0;
1106
1107 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1108 if (enable)
1109 dscommand0 &= ~INTSCBRAMSEL;
1110 else
1111 dscommand0 |= INTSCBRAMSEL;
1112 if (large)
1113 dscommand0 &= ~USCBSIZE32;
1114 else
1115 dscommand0 |= USCBSIZE32;
1116 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1117 } else {
1118 if (fast)
1119 devconfig &= ~EXTSCBTIME;
1120 else
1121 devconfig |= EXTSCBTIME;
1122 if (enable)
1123 devconfig &= ~SCBRAMSEL;
1124 else
1125 devconfig |= SCBRAMSEL;
1126 if (large)
1127 devconfig &= ~SCBSIZE32;
1128 else
1129 devconfig |= SCBSIZE32;
1130 }
1131 if (pcheck)
1132 devconfig |= EXTSCBPEN;
1133 else
1134 devconfig &= ~EXTSCBPEN;
1135
1136 aic_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
1137 }
1138
1139 /*
1140 * Take a look to see if we have external SRAM.
1141 * We currently do not attempt to use SRAM that is
1142 * shared among multiple controllers.
1143 */
1144 static void
ahc_probe_ext_scbram(struct ahc_softc * ahc)1145 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1146 {
1147 int num_scbs;
1148 int test_num_scbs;
1149 int enable;
1150 int pcheck;
1151 int fast;
1152 int large;
1153
1154 enable = FALSE;
1155 pcheck = FALSE;
1156 fast = FALSE;
1157 large = FALSE;
1158 num_scbs = 0;
1159
1160 if (ahc_ext_scbram_present(ahc) == 0)
1161 goto done;
1162
1163 /*
1164 * Probe for the best parameters to use.
1165 */
1166 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1167 num_scbs = ahc_probe_scbs(ahc);
1168 if (num_scbs == 0) {
1169 /* The SRAM wasn't really present. */
1170 goto done;
1171 }
1172 enable = TRUE;
1173
1174 /*
1175 * Clear any outstanding parity error
1176 * and ensure that parity error reporting
1177 * is enabled.
1178 */
1179 ahc_outb(ahc, SEQCTL, 0);
1180 ahc_outb(ahc, CLRINT, CLRPARERR);
1181 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1182
1183 /* Now see if we can do parity */
1184 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1185 num_scbs = ahc_probe_scbs(ahc);
1186 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1187 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1188 pcheck = TRUE;
1189
1190 /* Clear any resulting parity error */
1191 ahc_outb(ahc, CLRINT, CLRPARERR);
1192 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1193
1194 /* Now see if we can do fast timing */
1195 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1196 test_num_scbs = ahc_probe_scbs(ahc);
1197 if (test_num_scbs == num_scbs
1198 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1199 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1200 fast = TRUE;
1201
1202 /*
1203 * See if we can use large SCBs and still maintain
1204 * the same overall count of SCBs.
1205 */
1206 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1207 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1208 test_num_scbs = ahc_probe_scbs(ahc);
1209 if (test_num_scbs >= num_scbs) {
1210 large = TRUE;
1211 num_scbs = test_num_scbs;
1212 if (num_scbs >= 64) {
1213 /*
1214 * We have enough space to move the
1215 * "busy targets table" into SCB space
1216 * and make it qualify all the way to the
1217 * lun level.
1218 */
1219 ahc->flags |= AHC_SCB_BTT;
1220 }
1221 }
1222 }
1223 done:
1224 /*
1225 * Disable parity error reporting until we
1226 * can load instruction ram.
1227 */
1228 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1229 /* Clear any latched parity error */
1230 ahc_outb(ahc, CLRINT, CLRPARERR);
1231 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1232 if (bootverbose && enable) {
1233 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1234 ahc_name(ahc), fast ? "fast" : "slow",
1235 pcheck ? ", parity checking enabled" : "",
1236 large ? 64 : 32);
1237 }
1238 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1239 }
1240
1241 /*
1242 * Perform some simple tests that should catch situations where
1243 * our registers are invalidly mapped.
1244 */
1245 int
ahc_pci_test_register_access(struct ahc_softc * ahc)1246 ahc_pci_test_register_access(struct ahc_softc *ahc)
1247 {
1248 int error;
1249 u_int status1;
1250 uint32_t cmd;
1251 uint8_t hcntrl;
1252
1253 error = EIO;
1254
1255 /*
1256 * Enable PCI error interrupt status, but suppress NMIs
1257 * generated by SERR raised due to target aborts.
1258 */
1259 cmd = aic_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2);
1260 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
1261 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
1262
1263 /*
1264 * First a simple test to see if any
1265 * registers can be read. Reading
1266 * HCNTRL has no side effects and has
1267 * at least one bit that is guaranteed to
1268 * be zero so it is a good register to
1269 * use for this test.
1270 */
1271 hcntrl = ahc_inb(ahc, HCNTRL);
1272
1273 if (hcntrl == 0xFF)
1274 goto fail;
1275
1276 if ((hcntrl & CHIPRST) != 0) {
1277 /*
1278 * The chip has not been initialized since
1279 * PCI/EISA/VLB bus reset. Don't trust
1280 * "left over BIOS data".
1281 */
1282 ahc->flags |= AHC_NO_BIOS_INIT;
1283 }
1284
1285 /*
1286 * Next create a situation where write combining
1287 * or read prefetching could be initiated by the
1288 * CPU or host bridge. Our device does not support
1289 * either, so look for data corruption and/or flagged
1290 * PCI errors. First pause without causing another
1291 * chip reset.
1292 */
1293 hcntrl &= ~CHIPRST;
1294 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1295 while (ahc_is_paused(ahc) == 0)
1296 ;
1297
1298 /* Clear any PCI errors that occurred before our driver attached. */
1299 status1 = aic_pci_read_config(ahc->dev_softc,
1300 PCIR_STATUS + 1, /*bytes*/1);
1301 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1302 status1, /*bytes*/1);
1303 ahc_outb(ahc, CLRINT, CLRPARERR);
1304
1305 ahc_outb(ahc, SEQCTL, PERRORDIS);
1306 ahc_outb(ahc, SCBPTR, 0);
1307 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1308 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1309 goto fail;
1310
1311 status1 = aic_pci_read_config(ahc->dev_softc,
1312 PCIR_STATUS + 1, /*bytes*/1);
1313 if ((status1 & STA) != 0)
1314 goto fail;
1315
1316 error = 0;
1317
1318 fail:
1319 /* Silently clear any latched errors. */
1320 status1 = aic_pci_read_config(ahc->dev_softc,
1321 PCIR_STATUS + 1, /*bytes*/1);
1322 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1323 status1, /*bytes*/1);
1324 ahc_outb(ahc, CLRINT, CLRPARERR);
1325 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1326 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1327 return (error);
1328 }
1329
1330 /*
1331 * Check the external port logic for a serial eeprom
1332 * and termination/cable detection contrls.
1333 */
1334 static void
check_extport(struct ahc_softc * ahc,u_int * sxfrctl1)1335 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
1336 {
1337 struct seeprom_descriptor sd;
1338 struct seeprom_config *sc;
1339 int have_seeprom;
1340 int have_autoterm;
1341
1342 sd.sd_ahc = ahc;
1343 sd.sd_control_offset = SEECTL;
1344 sd.sd_status_offset = SEECTL;
1345 sd.sd_dataout_offset = SEECTL;
1346 sc = ahc->seep_config;
1347
1348 /*
1349 * For some multi-channel devices, the c46 is simply too
1350 * small to work. For the other controller types, we can
1351 * get our information from either SEEPROM type. Set the
1352 * type to start our probe with accordingly.
1353 */
1354 if (ahc->flags & AHC_LARGE_SEEPROM)
1355 sd.sd_chip = C56_66;
1356 else
1357 sd.sd_chip = C46;
1358
1359 sd.sd_MS = SEEMS;
1360 sd.sd_RDY = SEERDY;
1361 sd.sd_CS = SEECS;
1362 sd.sd_CK = SEECK;
1363 sd.sd_DO = SEEDO;
1364 sd.sd_DI = SEEDI;
1365
1366 have_seeprom = ahc_acquire_seeprom(ahc, &sd);
1367 if (have_seeprom) {
1368 if (bootverbose)
1369 printf("%s: Reading SEEPROM...", ahc_name(ahc));
1370
1371 for (;;) {
1372 u_int start_addr;
1373
1374 start_addr = 32 * (ahc->channel - 'A');
1375
1376 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc,
1377 start_addr,
1378 sizeof(*sc)/2);
1379
1380 if (have_seeprom)
1381 have_seeprom = ahc_verify_cksum(sc);
1382
1383 if (have_seeprom != 0 || sd.sd_chip == C56_66) {
1384 if (bootverbose) {
1385 if (have_seeprom == 0)
1386 printf ("checksum error\n");
1387 else
1388 printf ("done.\n");
1389 }
1390 break;
1391 }
1392 sd.sd_chip = C56_66;
1393 }
1394 ahc_release_seeprom(&sd);
1395
1396 /* Remember the SEEPROM type for later */
1397 if (sd.sd_chip == C56_66)
1398 ahc->flags |= AHC_LARGE_SEEPROM;
1399 }
1400
1401 if (!have_seeprom) {
1402 /*
1403 * Pull scratch ram settings and treat them as
1404 * if they are the contents of an seeprom if
1405 * the 'ADPT' signature is found in SCB2.
1406 * We manually compose the data as 16bit values
1407 * to avoid endian issues.
1408 */
1409 ahc_outb(ahc, SCBPTR, 2);
1410 if (ahc_inb(ahc, SCB_BASE) == 'A'
1411 && ahc_inb(ahc, SCB_BASE + 1) == 'D'
1412 && ahc_inb(ahc, SCB_BASE + 2) == 'P'
1413 && ahc_inb(ahc, SCB_BASE + 3) == 'T') {
1414 uint16_t *sc_data;
1415 int i;
1416
1417 sc_data = (uint16_t *)sc;
1418 for (i = 0; i < 32; i++, sc_data++) {
1419 int j;
1420
1421 j = i * 2;
1422 *sc_data = ahc_inb(ahc, SRAM_BASE + j)
1423 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8;
1424 }
1425 have_seeprom = ahc_verify_cksum(sc);
1426 if (have_seeprom)
1427 ahc->flags |= AHC_SCB_CONFIG_USED;
1428 }
1429 /*
1430 * Clear any SCB parity errors in case this data and
1431 * its associated parity was not initialized by the BIOS
1432 */
1433 ahc_outb(ahc, CLRINT, CLRPARERR);
1434 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1435 }
1436
1437 if (!have_seeprom) {
1438 if (bootverbose)
1439 printf("%s: No SEEPROM available.\n", ahc_name(ahc));
1440 ahc->flags |= AHC_USEDEFAULTS;
1441 free(ahc->seep_config, M_DEVBUF);
1442 ahc->seep_config = NULL;
1443 sc = NULL;
1444 } else {
1445 ahc_parse_pci_eeprom(ahc, sc);
1446 }
1447
1448 /*
1449 * Cards that have the external logic necessary to talk to
1450 * a SEEPROM, are almost certain to have the remaining logic
1451 * necessary for auto-termination control. This assumption
1452 * hasn't failed yet...
1453 */
1454 have_autoterm = have_seeprom;
1455
1456 /*
1457 * Some low-cost chips have SEEPROM and auto-term control built
1458 * in, instead of using a GAL. They can tell us directly
1459 * if the termination logic is enabled.
1460 */
1461 if ((ahc->features & AHC_SPIOCAP) != 0) {
1462 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0)
1463 have_autoterm = FALSE;
1464 }
1465
1466 if (have_autoterm) {
1467 ahc->flags |= AHC_HAS_TERM_LOGIC;
1468 ahc_acquire_seeprom(ahc, &sd);
1469 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1);
1470 ahc_release_seeprom(&sd);
1471 } else if (have_seeprom) {
1472 *sxfrctl1 &= ~STPWEN;
1473 if ((sc->adapter_control & CFSTERM) != 0)
1474 *sxfrctl1 |= STPWEN;
1475 if (bootverbose)
1476 printf("%s: Low byte termination %sabled\n",
1477 ahc_name(ahc),
1478 (*sxfrctl1 & STPWEN) ? "en" : "dis");
1479 }
1480 }
1481
1482 static void
ahc_parse_pci_eeprom(struct ahc_softc * ahc,struct seeprom_config * sc)1483 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc)
1484 {
1485 /*
1486 * Put the data we've collected down into SRAM
1487 * where ahc_init will find it.
1488 */
1489 int i;
1490 int max_targ = sc->max_targets & CFMAXTARG;
1491 u_int scsi_conf;
1492 uint16_t discenable;
1493 uint16_t ultraenb;
1494
1495 discenable = 0;
1496 ultraenb = 0;
1497 if ((sc->adapter_control & CFULTRAEN) != 0) {
1498 /*
1499 * Determine if this adapter has a "newstyle"
1500 * SEEPROM format.
1501 */
1502 for (i = 0; i < max_targ; i++) {
1503 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) {
1504 ahc->flags |= AHC_NEWEEPROM_FMT;
1505 break;
1506 }
1507 }
1508 }
1509
1510 for (i = 0; i < max_targ; i++) {
1511 u_int scsirate;
1512 uint16_t target_mask;
1513
1514 target_mask = 0x01 << i;
1515 if (sc->device_flags[i] & CFDISC)
1516 discenable |= target_mask;
1517 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
1518 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0)
1519 ultraenb |= target_mask;
1520 } else if ((sc->adapter_control & CFULTRAEN) != 0) {
1521 ultraenb |= target_mask;
1522 }
1523 if ((sc->device_flags[i] & CFXFER) == 0x04
1524 && (ultraenb & target_mask) != 0) {
1525 /* Treat 10MHz as a non-ultra speed */
1526 sc->device_flags[i] &= ~CFXFER;
1527 ultraenb &= ~target_mask;
1528 }
1529 if ((ahc->features & AHC_ULTRA2) != 0) {
1530 u_int offset;
1531
1532 if (sc->device_flags[i] & CFSYNCH)
1533 offset = MAX_OFFSET_ULTRA2;
1534 else
1535 offset = 0;
1536 ahc_outb(ahc, TARG_OFFSET + i, offset);
1537
1538 /*
1539 * The ultra enable bits contain the
1540 * high bit of the ultra2 sync rate
1541 * field.
1542 */
1543 scsirate = (sc->device_flags[i] & CFXFER)
1544 | ((ultraenb & target_mask) ? 0x8 : 0x0);
1545 if (sc->device_flags[i] & CFWIDEB)
1546 scsirate |= WIDEXFER;
1547 } else {
1548 scsirate = (sc->device_flags[i] & CFXFER) << 4;
1549 if (sc->device_flags[i] & CFSYNCH)
1550 scsirate |= SOFS;
1551 if (sc->device_flags[i] & CFWIDEB)
1552 scsirate |= WIDEXFER;
1553 }
1554 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
1555 }
1556 ahc->our_id = sc->brtime_id & CFSCSIID;
1557
1558 scsi_conf = (ahc->our_id & 0x7);
1559 if (sc->adapter_control & CFSPARITY)
1560 scsi_conf |= ENSPCHK;
1561 if (sc->adapter_control & CFRESETB)
1562 scsi_conf |= RESET_SCSI;
1563
1564 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT;
1565
1566 if (sc->bios_control & CFEXTEND)
1567 ahc->flags |= AHC_EXTENDED_TRANS_A;
1568
1569 if (sc->bios_control & CFBIOSEN)
1570 ahc->flags |= AHC_BIOS_ENABLED;
1571 if (ahc->features & AHC_ULTRA
1572 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
1573 /* Should we enable Ultra mode? */
1574 if (!(sc->adapter_control & CFULTRAEN))
1575 /* Treat us as a non-ultra card */
1576 ultraenb = 0;
1577 }
1578
1579 if (sc->signature == CFSIGNATURE
1580 || sc->signature == CFSIGNATURE2) {
1581 uint32_t devconfig;
1582
1583 /* Honor the STPWLEVEL settings */
1584 devconfig = aic_pci_read_config(ahc->dev_softc,
1585 DEVCONFIG, /*bytes*/4);
1586 devconfig &= ~STPWLEVEL;
1587 if ((sc->bios_control & CFSTPWLEVEL) != 0)
1588 devconfig |= STPWLEVEL;
1589 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
1590 devconfig, /*bytes*/4);
1591 }
1592 /* Set SCSICONF info */
1593 ahc_outb(ahc, SCSICONF, scsi_conf);
1594 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
1595 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
1596 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
1597 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
1598 }
1599
1600 static void
configure_termination(struct ahc_softc * ahc,struct seeprom_descriptor * sd,u_int adapter_control,u_int * sxfrctl1)1601 configure_termination(struct ahc_softc *ahc,
1602 struct seeprom_descriptor *sd,
1603 u_int adapter_control,
1604 u_int *sxfrctl1)
1605 {
1606 uint8_t brddat;
1607
1608 brddat = 0;
1609
1610 /*
1611 * Update the settings in sxfrctl1 to match the
1612 * termination settings
1613 */
1614 *sxfrctl1 = 0;
1615
1616 /*
1617 * SEECS must be on for the GALS to latch
1618 * the data properly. Be sure to leave MS
1619 * on or we will release the seeprom.
1620 */
1621 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
1622 if ((adapter_control & CFAUTOTERM) != 0
1623 || (ahc->features & AHC_NEW_TERMCTL) != 0) {
1624 int internal50_present;
1625 int internal68_present;
1626 int externalcable_present;
1627 int eeprom_present;
1628 int enableSEC_low;
1629 int enableSEC_high;
1630 int enablePRI_low;
1631 int enablePRI_high;
1632 int sum;
1633
1634 enableSEC_low = 0;
1635 enableSEC_high = 0;
1636 enablePRI_low = 0;
1637 enablePRI_high = 0;
1638 if ((ahc->features & AHC_NEW_TERMCTL) != 0) {
1639 ahc_new_term_detect(ahc, &enableSEC_low,
1640 &enableSEC_high,
1641 &enablePRI_low,
1642 &enablePRI_high,
1643 &eeprom_present);
1644 if ((adapter_control & CFSEAUTOTERM) == 0) {
1645 if (bootverbose)
1646 printf("%s: Manual SE Termination\n",
1647 ahc_name(ahc));
1648 enableSEC_low = (adapter_control & CFSELOWTERM);
1649 enableSEC_high =
1650 (adapter_control & CFSEHIGHTERM);
1651 }
1652 if ((adapter_control & CFAUTOTERM) == 0) {
1653 if (bootverbose)
1654 printf("%s: Manual LVD Termination\n",
1655 ahc_name(ahc));
1656 enablePRI_low = (adapter_control & CFSTERM);
1657 enablePRI_high = (adapter_control & CFWSTERM);
1658 }
1659 /* Make the table calculations below happy */
1660 internal50_present = 0;
1661 internal68_present = 1;
1662 externalcable_present = 1;
1663 } else if ((ahc->features & AHC_SPIOCAP) != 0) {
1664 aic785X_cable_detect(ahc, &internal50_present,
1665 &externalcable_present,
1666 &eeprom_present);
1667 /* Can never support a wide connector. */
1668 internal68_present = 0;
1669 } else {
1670 aic787X_cable_detect(ahc, &internal50_present,
1671 &internal68_present,
1672 &externalcable_present,
1673 &eeprom_present);
1674 }
1675
1676 if ((ahc->features & AHC_WIDE) == 0)
1677 internal68_present = 0;
1678
1679 if (bootverbose
1680 && (ahc->features & AHC_ULTRA2) == 0) {
1681 printf("%s: internal 50 cable %s present",
1682 ahc_name(ahc),
1683 internal50_present ? "is":"not");
1684
1685 if ((ahc->features & AHC_WIDE) != 0)
1686 printf(", internal 68 cable %s present",
1687 internal68_present ? "is":"not");
1688 printf("\n%s: external cable %s present\n",
1689 ahc_name(ahc),
1690 externalcable_present ? "is":"not");
1691 }
1692 if (bootverbose)
1693 printf("%s: BIOS eeprom %s present\n",
1694 ahc_name(ahc), eeprom_present ? "is" : "not");
1695
1696 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) {
1697 /*
1698 * The 50 pin connector is a separate bus,
1699 * so force it to always be terminated.
1700 * In the future, perform current sensing
1701 * to determine if we are in the middle of
1702 * a properly terminated bus.
1703 */
1704 internal50_present = 0;
1705 }
1706
1707 /*
1708 * Now set the termination based on what
1709 * we found.
1710 * Flash Enable = BRDDAT7
1711 * Secondary High Term Enable = BRDDAT6
1712 * Secondary Low Term Enable = BRDDAT5 (7890)
1713 * Primary High Term Enable = BRDDAT4 (7890)
1714 */
1715 if ((ahc->features & AHC_ULTRA2) == 0
1716 && (internal50_present != 0)
1717 && (internal68_present != 0)
1718 && (externalcable_present != 0)) {
1719 printf("%s: Illegal cable configuration!!. "
1720 "Only two connectors on the "
1721 "adapter may be used at a "
1722 "time!\n", ahc_name(ahc));
1723
1724 /*
1725 * Pretend there are no cables in the hope
1726 * that having all of the termination on
1727 * gives us a more stable bus.
1728 */
1729 internal50_present = 0;
1730 internal68_present = 0;
1731 externalcable_present = 0;
1732 }
1733
1734 if ((ahc->features & AHC_WIDE) != 0
1735 && ((externalcable_present == 0)
1736 || (internal68_present == 0)
1737 || (enableSEC_high != 0))) {
1738 brddat |= BRDDAT6;
1739 if (bootverbose) {
1740 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1741 printf("%s: 68 pin termination "
1742 "Enabled\n", ahc_name(ahc));
1743 else
1744 printf("%s: %sHigh byte termination "
1745 "Enabled\n", ahc_name(ahc),
1746 enableSEC_high ? "Secondary "
1747 : "");
1748 }
1749 }
1750
1751 sum = internal50_present + internal68_present
1752 + externalcable_present;
1753 if (sum < 2 || (enableSEC_low != 0)) {
1754 if ((ahc->features & AHC_ULTRA2) != 0)
1755 brddat |= BRDDAT5;
1756 else
1757 *sxfrctl1 |= STPWEN;
1758 if (bootverbose) {
1759 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0)
1760 printf("%s: 50 pin termination "
1761 "Enabled\n", ahc_name(ahc));
1762 else
1763 printf("%s: %sLow byte termination "
1764 "Enabled\n", ahc_name(ahc),
1765 enableSEC_low ? "Secondary "
1766 : "");
1767 }
1768 }
1769
1770 if (enablePRI_low != 0) {
1771 *sxfrctl1 |= STPWEN;
1772 if (bootverbose)
1773 printf("%s: Primary Low Byte termination "
1774 "Enabled\n", ahc_name(ahc));
1775 }
1776
1777 /*
1778 * Setup STPWEN before setting up the rest of
1779 * the termination per the tech note on the U160 cards.
1780 */
1781 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1782
1783 if (enablePRI_high != 0) {
1784 brddat |= BRDDAT4;
1785 if (bootverbose)
1786 printf("%s: Primary High Byte "
1787 "termination Enabled\n",
1788 ahc_name(ahc));
1789 }
1790
1791 write_brdctl(ahc, brddat);
1792
1793 } else {
1794 if ((adapter_control & CFSTERM) != 0) {
1795 *sxfrctl1 |= STPWEN;
1796
1797 if (bootverbose)
1798 printf("%s: %sLow byte termination Enabled\n",
1799 ahc_name(ahc),
1800 (ahc->features & AHC_ULTRA2) ? "Primary "
1801 : "");
1802 }
1803
1804 if ((adapter_control & CFWSTERM) != 0
1805 && (ahc->features & AHC_WIDE) != 0) {
1806 brddat |= BRDDAT6;
1807 if (bootverbose)
1808 printf("%s: %sHigh byte termination Enabled\n",
1809 ahc_name(ahc),
1810 (ahc->features & AHC_ULTRA2)
1811 ? "Secondary " : "");
1812 }
1813
1814 /*
1815 * Setup STPWEN before setting up the rest of
1816 * the termination per the tech note on the U160 cards.
1817 */
1818 ahc_outb(ahc, SXFRCTL1, *sxfrctl1);
1819
1820 if ((ahc->features & AHC_WIDE) != 0)
1821 write_brdctl(ahc, brddat);
1822 }
1823 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
1824 }
1825
1826 static void
ahc_new_term_detect(struct ahc_softc * ahc,int * enableSEC_low,int * enableSEC_high,int * enablePRI_low,int * enablePRI_high,int * eeprom_present)1827 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
1828 int *enableSEC_high, int *enablePRI_low,
1829 int *enablePRI_high, int *eeprom_present)
1830 {
1831 uint8_t brdctl;
1832
1833 /*
1834 * BRDDAT7 = Eeprom
1835 * BRDDAT6 = Enable Secondary High Byte termination
1836 * BRDDAT5 = Enable Secondary Low Byte termination
1837 * BRDDAT4 = Enable Primary high byte termination
1838 * BRDDAT3 = Enable Primary low byte termination
1839 */
1840 brdctl = read_brdctl(ahc);
1841 *eeprom_present = brdctl & BRDDAT7;
1842 *enableSEC_high = (brdctl & BRDDAT6);
1843 *enableSEC_low = (brdctl & BRDDAT5);
1844 *enablePRI_high = (brdctl & BRDDAT4);
1845 *enablePRI_low = (brdctl & BRDDAT3);
1846 }
1847
1848 static void
aic787X_cable_detect(struct ahc_softc * ahc,int * internal50_present,int * internal68_present,int * externalcable_present,int * eeprom_present)1849 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1850 int *internal68_present, int *externalcable_present,
1851 int *eeprom_present)
1852 {
1853 uint8_t brdctl;
1854
1855 /*
1856 * First read the status of our cables.
1857 * Set the rom bank to 0 since the
1858 * bank setting serves as a multiplexor
1859 * for the cable detection logic.
1860 * BRDDAT5 controls the bank switch.
1861 */
1862 write_brdctl(ahc, 0);
1863
1864 /*
1865 * Now read the state of the internal
1866 * connectors. BRDDAT6 is INT50 and
1867 * BRDDAT7 is INT68.
1868 */
1869 brdctl = read_brdctl(ahc);
1870 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1;
1871 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1;
1872
1873 /*
1874 * Set the rom bank to 1 and determine
1875 * the other signals.
1876 */
1877 write_brdctl(ahc, BRDDAT5);
1878
1879 /*
1880 * Now read the state of the external
1881 * connectors. BRDDAT6 is EXT68 and
1882 * BRDDAT7 is EPROMPS.
1883 */
1884 brdctl = read_brdctl(ahc);
1885 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1886 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0;
1887 }
1888
1889 static void
aic785X_cable_detect(struct ahc_softc * ahc,int * internal50_present,int * externalcable_present,int * eeprom_present)1890 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
1891 int *externalcable_present, int *eeprom_present)
1892 {
1893 uint8_t brdctl;
1894 uint8_t spiocap;
1895
1896 spiocap = ahc_inb(ahc, SPIOCAP);
1897 spiocap &= ~SOFTCMDEN;
1898 spiocap |= EXT_BRDCTL;
1899 ahc_outb(ahc, SPIOCAP, spiocap);
1900 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
1901 ahc_flush_device_writes(ahc);
1902 aic_delay(500);
1903 ahc_outb(ahc, BRDCTL, 0);
1904 ahc_flush_device_writes(ahc);
1905 aic_delay(500);
1906 brdctl = ahc_inb(ahc, BRDCTL);
1907 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1;
1908 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1;
1909 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0;
1910 }
1911
1912 int
ahc_acquire_seeprom(struct ahc_softc * ahc,struct seeprom_descriptor * sd)1913 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
1914 {
1915 int wait;
1916
1917 if ((ahc->features & AHC_SPIOCAP) != 0
1918 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
1919 return (0);
1920
1921 /*
1922 * Request access of the memory port. When access is
1923 * granted, SEERDY will go high. We use a 1 second
1924 * timeout which should be near 1 second more than
1925 * is needed. Reason: after the chip reset, there
1926 * should be no contention.
1927 */
1928 SEEPROM_OUTB(sd, sd->sd_MS);
1929 wait = 1000; /* 1 second timeout in msec */
1930 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
1931 aic_delay(1000); /* delay 1 msec */
1932 }
1933 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
1934 SEEPROM_OUTB(sd, 0);
1935 return (0);
1936 }
1937 return(1);
1938 }
1939
1940 void
ahc_release_seeprom(struct seeprom_descriptor * sd)1941 ahc_release_seeprom(struct seeprom_descriptor *sd)
1942 {
1943 /* Release access to the memory port and the serial EEPROM. */
1944 SEEPROM_OUTB(sd, 0);
1945 }
1946
1947 static void
write_brdctl(struct ahc_softc * ahc,uint8_t value)1948 write_brdctl(struct ahc_softc *ahc, uint8_t value)
1949 {
1950 uint8_t brdctl;
1951
1952 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1953 brdctl = BRDSTB;
1954 if (ahc->channel == 'B')
1955 brdctl |= BRDCS;
1956 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1957 brdctl = 0;
1958 } else {
1959 brdctl = BRDSTB|BRDCS;
1960 }
1961 ahc_outb(ahc, BRDCTL, brdctl);
1962 ahc_flush_device_writes(ahc);
1963 brdctl |= value;
1964 ahc_outb(ahc, BRDCTL, brdctl);
1965 ahc_flush_device_writes(ahc);
1966 if ((ahc->features & AHC_ULTRA2) != 0)
1967 brdctl |= BRDSTB_ULTRA2;
1968 else
1969 brdctl &= ~BRDSTB;
1970 ahc_outb(ahc, BRDCTL, brdctl);
1971 ahc_flush_device_writes(ahc);
1972 if ((ahc->features & AHC_ULTRA2) != 0)
1973 brdctl = 0;
1974 else
1975 brdctl &= ~BRDCS;
1976 ahc_outb(ahc, BRDCTL, brdctl);
1977 }
1978
1979 static uint8_t
read_brdctl(struct ahc_softc * ahc)1980 read_brdctl(struct ahc_softc *ahc)
1981 {
1982 uint8_t brdctl;
1983 uint8_t value;
1984
1985 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
1986 brdctl = BRDRW;
1987 if (ahc->channel == 'B')
1988 brdctl |= BRDCS;
1989 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1990 brdctl = BRDRW_ULTRA2;
1991 } else {
1992 brdctl = BRDRW|BRDCS;
1993 }
1994 ahc_outb(ahc, BRDCTL, brdctl);
1995 ahc_flush_device_writes(ahc);
1996 value = ahc_inb(ahc, BRDCTL);
1997 ahc_outb(ahc, BRDCTL, 0);
1998 return (value);
1999 }
2000
2001 static void
ahc_pci_intr(struct ahc_softc * ahc)2002 ahc_pci_intr(struct ahc_softc *ahc)
2003 {
2004 u_int error;
2005 u_int status1;
2006
2007 error = ahc_inb(ahc, ERROR);
2008 if ((error & PCIERRSTAT) == 0)
2009 return;
2010
2011 status1 = aic_pci_read_config(ahc->dev_softc,
2012 PCIR_STATUS + 1, /*bytes*/1);
2013
2014 if ((status1 & ~DPE) != 0
2015 || (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2016 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
2017 ahc_name(ahc),
2018 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
2019 }
2020
2021 if (status1 & DPE
2022 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2023 ahc->pci_target_perr_count++;
2024 printf("%s: Data Parity Error Detected during address "
2025 "or write data phase\n", ahc_name(ahc));
2026 }
2027 if (status1 & SSE) {
2028 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
2029 }
2030 if (status1 & RMA) {
2031 printf("%s: Received a Master Abort\n", ahc_name(ahc));
2032 }
2033 if (status1 & RTA) {
2034 printf("%s: Received a Target Abort\n", ahc_name(ahc));
2035 }
2036 if (status1 & STA) {
2037 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
2038 }
2039 if (status1 & DPR) {
2040 printf("%s: Data Parity Error has been reported via PERR#\n",
2041 ahc_name(ahc));
2042 }
2043
2044 /* Clear latched errors. */
2045 aic_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
2046 status1, /*bytes*/1);
2047
2048 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
2049 printf("%s: Latched PCIERR interrupt with "
2050 "no status bits set\n", ahc_name(ahc));
2051 } else {
2052 ahc_outb(ahc, CLRINT, CLRPARERR);
2053 }
2054
2055 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH
2056 && (ahc->flags & AHC_DISABLE_PCI_PERR) == 0) {
2057 printf(
2058 "%s: WARNING WARNING WARNING WARNING\n"
2059 "%s: Too many PCI parity errors observed as a target.\n"
2060 "%s: Some device on this PCI bus is generating bad parity.\n"
2061 "%s: This is an error *observed by*, not *generated by*, %s.\n"
2062 "%s: PCI parity error checking has been disabled.\n"
2063 "%s: WARNING WARNING WARNING WARNING\n",
2064 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2065 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc),
2066 ahc_name(ahc));
2067 ahc->seqctl |= FAILDIS;
2068 ahc->flags |= AHC_DISABLE_PCI_PERR;
2069 ahc_outb(ahc, SEQCTL, ahc->seqctl);
2070 }
2071 ahc_unpause(ahc);
2072 }
2073
2074 static int
ahc_pci_chip_init(struct ahc_softc * ahc)2075 ahc_pci_chip_init(struct ahc_softc *ahc)
2076 {
2077 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
2078 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
2079 if ((ahc->features & AHC_DT) != 0) {
2080 u_int sfunct;
2081
2082 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
2083 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
2084 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
2085 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
2086 ahc_outb(ahc, SFUNCT, sfunct);
2087 ahc_outb(ahc, CRCCONTROL1,
2088 ahc->bus_softc.pci_softc.crccontrol1);
2089 }
2090 if ((ahc->features & AHC_MULTI_FUNC) != 0)
2091 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
2092
2093 if ((ahc->features & AHC_ULTRA2) != 0)
2094 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
2095
2096 return (ahc_chip_init(ahc));
2097 }
2098
2099 static int
ahc_pci_suspend(struct ahc_softc * ahc)2100 ahc_pci_suspend(struct ahc_softc *ahc)
2101 {
2102 return (ahc_suspend(ahc));
2103 }
2104
2105 static int
ahc_pci_resume(struct ahc_softc * ahc)2106 ahc_pci_resume(struct ahc_softc *ahc)
2107 {
2108
2109 aic_power_state_change(ahc, AIC_POWER_STATE_D0);
2110
2111 /*
2112 * We assume that the OS has restored our register
2113 * mappings, etc. Just update the config space registers
2114 * that the OS doesn't know about and rely on our chip
2115 * reset handler to handle the rest.
2116 */
2117 aic_pci_write_config(ahc->dev_softc, DEVCONFIG,
2118 ahc->bus_softc.pci_softc.devconfig, /*bytes*/4);
2119 aic_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
2120 ahc->bus_softc.pci_softc.command, /*bytes*/1);
2121 aic_pci_write_config(ahc->dev_softc, CSIZE_LATTIME,
2122 ahc->bus_softc.pci_softc.csize_lattime,
2123 /*bytes*/1);
2124 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) {
2125 struct seeprom_descriptor sd;
2126 u_int sxfrctl1;
2127
2128 sd.sd_ahc = ahc;
2129 sd.sd_control_offset = SEECTL;
2130 sd.sd_status_offset = SEECTL;
2131 sd.sd_dataout_offset = SEECTL;
2132
2133 ahc_acquire_seeprom(ahc, &sd);
2134 configure_termination(ahc, &sd,
2135 ahc->seep_config->adapter_control,
2136 &sxfrctl1);
2137 ahc_release_seeprom(&sd);
2138 }
2139 return (ahc_resume(ahc));
2140 }
2141
2142 static int
ahc_aic785X_setup(struct ahc_softc * ahc)2143 ahc_aic785X_setup(struct ahc_softc *ahc)
2144 {
2145 aic_dev_softc_t pci;
2146 uint8_t rev;
2147
2148 pci = ahc->dev_softc;
2149 ahc->channel = 'A';
2150 ahc->chip = AHC_AIC7850;
2151 ahc->features = AHC_AIC7850_FE;
2152 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2153 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2154 if (rev >= 1)
2155 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2156 ahc->instruction_ram_size = 512;
2157 return (0);
2158 }
2159
2160 static int
ahc_aic7860_setup(struct ahc_softc * ahc)2161 ahc_aic7860_setup(struct ahc_softc *ahc)
2162 {
2163 aic_dev_softc_t pci;
2164 uint8_t rev;
2165
2166 pci = ahc->dev_softc;
2167 ahc->channel = 'A';
2168 ahc->chip = AHC_AIC7860;
2169 ahc->features = AHC_AIC7860_FE;
2170 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2171 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2172 if (rev >= 1)
2173 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2174 ahc->instruction_ram_size = 512;
2175 return (0);
2176 }
2177
2178 static int
ahc_apa1480_setup(struct ahc_softc * ahc)2179 ahc_apa1480_setup(struct ahc_softc *ahc)
2180 {
2181 int error;
2182
2183 error = ahc_aic7860_setup(ahc);
2184 if (error != 0)
2185 return (error);
2186 ahc->features |= AHC_REMOVABLE;
2187 return (0);
2188 }
2189
2190 static int
ahc_aic7870_setup(struct ahc_softc * ahc)2191 ahc_aic7870_setup(struct ahc_softc *ahc)
2192 {
2193
2194 ahc->channel = 'A';
2195 ahc->chip = AHC_AIC7870;
2196 ahc->features = AHC_AIC7870_FE;
2197 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2198 ahc->instruction_ram_size = 512;
2199 return (0);
2200 }
2201
2202 static int
ahc_aha394X_setup(struct ahc_softc * ahc)2203 ahc_aha394X_setup(struct ahc_softc *ahc)
2204 {
2205 int error;
2206
2207 error = ahc_aic7870_setup(ahc);
2208 if (error == 0)
2209 error = ahc_aha394XX_setup(ahc);
2210 return (error);
2211 }
2212
2213 static int
ahc_aha398X_setup(struct ahc_softc * ahc)2214 ahc_aha398X_setup(struct ahc_softc *ahc)
2215 {
2216 int error;
2217
2218 error = ahc_aic7870_setup(ahc);
2219 if (error == 0)
2220 error = ahc_aha398XX_setup(ahc);
2221 return (error);
2222 }
2223
2224 static int
ahc_aha494X_setup(struct ahc_softc * ahc)2225 ahc_aha494X_setup(struct ahc_softc *ahc)
2226 {
2227 int error;
2228
2229 error = ahc_aic7870_setup(ahc);
2230 if (error == 0)
2231 error = ahc_aha494XX_setup(ahc);
2232 return (error);
2233 }
2234
2235 static int
ahc_aic7880_setup(struct ahc_softc * ahc)2236 ahc_aic7880_setup(struct ahc_softc *ahc)
2237 {
2238 aic_dev_softc_t pci;
2239 uint8_t rev;
2240
2241 pci = ahc->dev_softc;
2242 ahc->channel = 'A';
2243 ahc->chip = AHC_AIC7880;
2244 ahc->features = AHC_AIC7880_FE;
2245 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
2246 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2247 if (rev >= 1) {
2248 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
2249 } else {
2250 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
2251 }
2252 ahc->instruction_ram_size = 512;
2253 return (0);
2254 }
2255
2256 static int
ahc_aha2940Pro_setup(struct ahc_softc * ahc)2257 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
2258 {
2259
2260 ahc->flags |= AHC_INT50_SPEEDFLEX;
2261 return (ahc_aic7880_setup(ahc));
2262 }
2263
2264 static int
ahc_aha394XU_setup(struct ahc_softc * ahc)2265 ahc_aha394XU_setup(struct ahc_softc *ahc)
2266 {
2267 int error;
2268
2269 error = ahc_aic7880_setup(ahc);
2270 if (error == 0)
2271 error = ahc_aha394XX_setup(ahc);
2272 return (error);
2273 }
2274
2275 static int
ahc_aha398XU_setup(struct ahc_softc * ahc)2276 ahc_aha398XU_setup(struct ahc_softc *ahc)
2277 {
2278 int error;
2279
2280 error = ahc_aic7880_setup(ahc);
2281 if (error == 0)
2282 error = ahc_aha398XX_setup(ahc);
2283 return (error);
2284 }
2285
2286 static int
ahc_aic7890_setup(struct ahc_softc * ahc)2287 ahc_aic7890_setup(struct ahc_softc *ahc)
2288 {
2289 aic_dev_softc_t pci;
2290 uint8_t rev;
2291
2292 pci = ahc->dev_softc;
2293 ahc->channel = 'A';
2294 ahc->chip = AHC_AIC7890;
2295 ahc->features = AHC_AIC7890_FE;
2296 ahc->flags |= AHC_NEWEEPROM_FMT;
2297 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2298 if (rev == 0)
2299 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
2300 ahc->instruction_ram_size = 768;
2301 return (0);
2302 }
2303
2304 static int
ahc_aic7892_setup(struct ahc_softc * ahc)2305 ahc_aic7892_setup(struct ahc_softc *ahc)
2306 {
2307
2308 ahc->channel = 'A';
2309 ahc->chip = AHC_AIC7892;
2310 ahc->features = AHC_AIC7892_FE;
2311 ahc->flags |= AHC_NEWEEPROM_FMT;
2312 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2313 ahc->instruction_ram_size = 1024;
2314 return (0);
2315 }
2316
2317 static int
ahc_aic7895_setup(struct ahc_softc * ahc)2318 ahc_aic7895_setup(struct ahc_softc *ahc)
2319 {
2320 aic_dev_softc_t pci;
2321 uint8_t rev;
2322
2323 pci = ahc->dev_softc;
2324 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2325 /*
2326 * The 'C' revision of the aic7895 has a few additional features.
2327 */
2328 rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
2329 if (rev >= 4) {
2330 ahc->chip = AHC_AIC7895C;
2331 ahc->features = AHC_AIC7895C_FE;
2332 } else {
2333 u_int command;
2334
2335 ahc->chip = AHC_AIC7895;
2336 ahc->features = AHC_AIC7895_FE;
2337
2338 /*
2339 * The BIOS disables the use of MWI transactions
2340 * since it does not have the MWI bug work around
2341 * we have. Disabling MWI reduces performance, so
2342 * turn it on again.
2343 */
2344 command = aic_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1);
2345 command |= PCIM_CMD_MWRICEN;
2346 aic_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1);
2347 ahc->bugs |= AHC_PCI_MWI_BUG;
2348 }
2349 /*
2350 * XXX Does CACHETHEN really not work??? What about PCI retry?
2351 * on C level chips. Need to test, but for now, play it safe.
2352 */
2353 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
2354 | AHC_CACHETHEN_BUG;
2355
2356 #if 0
2357 uint32_t devconfig;
2358
2359 /*
2360 * Cachesize must also be zero due to stray DAC
2361 * problem when sitting behind some bridges.
2362 */
2363 aic_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1);
2364 devconfig = aic_pci_read_config(pci, DEVCONFIG, /*bytes*/1);
2365 devconfig |= MRDCEN;
2366 aic_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1);
2367 #endif
2368 ahc->flags |= AHC_NEWEEPROM_FMT;
2369 ahc->instruction_ram_size = 512;
2370 return (0);
2371 }
2372
2373 static int
ahc_aic7896_setup(struct ahc_softc * ahc)2374 ahc_aic7896_setup(struct ahc_softc *ahc)
2375 {
2376 aic_dev_softc_t pci;
2377
2378 pci = ahc->dev_softc;
2379 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2380 ahc->chip = AHC_AIC7896;
2381 ahc->features = AHC_AIC7896_FE;
2382 ahc->flags |= AHC_NEWEEPROM_FMT;
2383 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
2384 ahc->instruction_ram_size = 768;
2385 return (0);
2386 }
2387
2388 static int
ahc_aic7899_setup(struct ahc_softc * ahc)2389 ahc_aic7899_setup(struct ahc_softc *ahc)
2390 {
2391 aic_dev_softc_t pci;
2392
2393 pci = ahc->dev_softc;
2394 ahc->channel = aic_get_pci_function(pci) == 1 ? 'B' : 'A';
2395 ahc->chip = AHC_AIC7899;
2396 ahc->features = AHC_AIC7899_FE;
2397 ahc->flags |= AHC_NEWEEPROM_FMT;
2398 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
2399 ahc->instruction_ram_size = 1024;
2400 return (0);
2401 }
2402
2403 static int
ahc_aha29160C_setup(struct ahc_softc * ahc)2404 ahc_aha29160C_setup(struct ahc_softc *ahc)
2405 {
2406 int error;
2407
2408 error = ahc_aic7899_setup(ahc);
2409 if (error != 0)
2410 return (error);
2411 ahc->features |= AHC_REMOVABLE;
2412 return (0);
2413 }
2414
2415 static int
ahc_raid_setup(struct ahc_softc * ahc)2416 ahc_raid_setup(struct ahc_softc *ahc)
2417 {
2418 printf("RAID functionality unsupported\n");
2419 return (ENXIO);
2420 }
2421
2422 static int
ahc_aha394XX_setup(struct ahc_softc * ahc)2423 ahc_aha394XX_setup(struct ahc_softc *ahc)
2424 {
2425 aic_dev_softc_t pci;
2426
2427 pci = ahc->dev_softc;
2428 switch (aic_get_pci_slot(pci)) {
2429 case AHC_394X_SLOT_CHANNEL_A:
2430 ahc->channel = 'A';
2431 break;
2432 case AHC_394X_SLOT_CHANNEL_B:
2433 ahc->channel = 'B';
2434 break;
2435 default:
2436 printf("adapter at unexpected slot %d\n"
2437 "unable to map to a channel\n",
2438 aic_get_pci_slot(pci));
2439 ahc->channel = 'A';
2440 }
2441 return (0);
2442 }
2443
2444 static int
ahc_aha398XX_setup(struct ahc_softc * ahc)2445 ahc_aha398XX_setup(struct ahc_softc *ahc)
2446 {
2447 aic_dev_softc_t pci;
2448
2449 pci = ahc->dev_softc;
2450 switch (aic_get_pci_slot(pci)) {
2451 case AHC_398X_SLOT_CHANNEL_A:
2452 ahc->channel = 'A';
2453 break;
2454 case AHC_398X_SLOT_CHANNEL_B:
2455 ahc->channel = 'B';
2456 break;
2457 case AHC_398X_SLOT_CHANNEL_C:
2458 ahc->channel = 'C';
2459 break;
2460 default:
2461 printf("adapter at unexpected slot %d\n"
2462 "unable to map to a channel\n",
2463 aic_get_pci_slot(pci));
2464 ahc->channel = 'A';
2465 break;
2466 }
2467 ahc->flags |= AHC_LARGE_SEEPROM;
2468 return (0);
2469 }
2470
2471 static int
ahc_aha494XX_setup(struct ahc_softc * ahc)2472 ahc_aha494XX_setup(struct ahc_softc *ahc)
2473 {
2474 aic_dev_softc_t pci;
2475
2476 pci = ahc->dev_softc;
2477 switch (aic_get_pci_slot(pci)) {
2478 case AHC_494X_SLOT_CHANNEL_A:
2479 ahc->channel = 'A';
2480 break;
2481 case AHC_494X_SLOT_CHANNEL_B:
2482 ahc->channel = 'B';
2483 break;
2484 case AHC_494X_SLOT_CHANNEL_C:
2485 ahc->channel = 'C';
2486 break;
2487 case AHC_494X_SLOT_CHANNEL_D:
2488 ahc->channel = 'D';
2489 break;
2490 default:
2491 printf("adapter at unexpected slot %d\n"
2492 "unable to map to a channel\n",
2493 aic_get_pci_slot(pci));
2494 ahc->channel = 'A';
2495 }
2496 ahc->flags |= AHC_LARGE_SEEPROM;
2497 return (0);
2498 }
2499