1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/mbuf.h>
39 #include <sys/module.h>
40 #include <sys/rman.h>
41 #include <sys/queue.h>
42 #include <sys/socket.h>
43 #include <sys/sockio.h>
44 #include <sys/sysctl.h>
45 #include <sys/taskqueue.h>
46
47 #include <net/bpf.h>
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_llc.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
57
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
62
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
71
72 #include <dev/ale/if_alereg.h>
73 #include <dev/ale/if_alevar.h>
74
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
77
78 /* For more information about Tx checksum offload issues see ale_encap(). */
79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
80
81 MODULE_DEPEND(ale, pci, 1, 1, 1);
82 MODULE_DEPEND(ale, ether, 1, 1, 1);
83 MODULE_DEPEND(ale, miibus, 1, 1, 1);
84
85 /* Tunables. */
86 static int msi_disable = 0;
87 static int msix_disable = 0;
88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
90
91 /*
92 * Devices supported by this driver.
93 */
94 static const struct ale_dev {
95 uint16_t ale_vendorid;
96 uint16_t ale_deviceid;
97 const char *ale_name;
98 } ale_devs[] = {
99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
101 };
102
103 static int ale_attach(device_t);
104 static int ale_check_boundary(struct ale_softc *);
105 static int ale_detach(device_t);
106 static int ale_dma_alloc(struct ale_softc *);
107 static void ale_dma_free(struct ale_softc *);
108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
109 static int ale_encap(struct ale_softc *, struct mbuf **);
110 static void ale_get_macaddr(struct ale_softc *);
111 static void ale_init(void *);
112 static void ale_init_locked(struct ale_softc *);
113 static void ale_init_rx_pages(struct ale_softc *);
114 static void ale_init_tx_ring(struct ale_softc *);
115 static void ale_int_task(void *, int);
116 static int ale_intr(void *);
117 static int ale_ioctl(if_t, u_long, caddr_t);
118 static void ale_mac_config(struct ale_softc *);
119 static int ale_miibus_readreg(device_t, int, int);
120 static void ale_miibus_statchg(device_t);
121 static int ale_miibus_writereg(device_t, int, int, int);
122 static int ale_mediachange(if_t);
123 static void ale_mediastatus(if_t, struct ifmediareq *);
124 static void ale_phy_reset(struct ale_softc *);
125 static int ale_probe(device_t);
126 static void ale_reset(struct ale_softc *);
127 static int ale_resume(device_t);
128 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
129 uint32_t, uint32_t *);
130 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
131 static int ale_rxeof(struct ale_softc *sc, int);
132 static void ale_rxfilter(struct ale_softc *);
133 static void ale_rxvlan(struct ale_softc *);
134 static void ale_setlinkspeed(struct ale_softc *);
135 static void ale_setwol(struct ale_softc *);
136 static int ale_shutdown(device_t);
137 static void ale_start(if_t);
138 static void ale_start_locked(if_t);
139 static void ale_stats_clear(struct ale_softc *);
140 static void ale_stats_update(struct ale_softc *);
141 static void ale_stop(struct ale_softc *);
142 static void ale_stop_mac(struct ale_softc *);
143 static int ale_suspend(device_t);
144 static void ale_sysctl_node(struct ale_softc *);
145 static void ale_tick(void *);
146 static void ale_txeof(struct ale_softc *);
147 static void ale_watchdog(struct ale_softc *);
148 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
149 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
150 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
151
152 static device_method_t ale_methods[] = {
153 /* Device interface. */
154 DEVMETHOD(device_probe, ale_probe),
155 DEVMETHOD(device_attach, ale_attach),
156 DEVMETHOD(device_detach, ale_detach),
157 DEVMETHOD(device_shutdown, ale_shutdown),
158 DEVMETHOD(device_suspend, ale_suspend),
159 DEVMETHOD(device_resume, ale_resume),
160
161 /* MII interface. */
162 DEVMETHOD(miibus_readreg, ale_miibus_readreg),
163 DEVMETHOD(miibus_writereg, ale_miibus_writereg),
164 DEVMETHOD(miibus_statchg, ale_miibus_statchg),
165
166 DEVMETHOD_END
167 };
168
169 static driver_t ale_driver = {
170 "ale",
171 ale_methods,
172 sizeof(struct ale_softc)
173 };
174
175 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL);
176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs,
177 nitems(ale_devs));
178 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL);
179
180 static struct resource_spec ale_res_spec_mem[] = {
181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
182 { -1, 0, 0 }
183 };
184
185 static struct resource_spec ale_irq_spec_legacy[] = {
186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
187 { -1, 0, 0 }
188 };
189
190 static struct resource_spec ale_irq_spec_msi[] = {
191 { SYS_RES_IRQ, 1, RF_ACTIVE },
192 { -1, 0, 0 }
193 };
194
195 static struct resource_spec ale_irq_spec_msix[] = {
196 { SYS_RES_IRQ, 1, RF_ACTIVE },
197 { -1, 0, 0 }
198 };
199
200 static int
ale_miibus_readreg(device_t dev,int phy,int reg)201 ale_miibus_readreg(device_t dev, int phy, int reg)
202 {
203 struct ale_softc *sc;
204 uint32_t v;
205 int i;
206
207 sc = device_get_softc(dev);
208
209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
212 DELAY(5);
213 v = CSR_READ_4(sc, ALE_MDIO);
214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
215 break;
216 }
217
218 if (i == 0) {
219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
220 return (0);
221 }
222
223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
224 }
225
226 static int
ale_miibus_writereg(device_t dev,int phy,int reg,int val)227 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
228 {
229 struct ale_softc *sc;
230 uint32_t v;
231 int i;
232
233 sc = device_get_softc(dev);
234
235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
239 DELAY(5);
240 v = CSR_READ_4(sc, ALE_MDIO);
241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
242 break;
243 }
244
245 if (i == 0)
246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
247
248 return (0);
249 }
250
251 static void
ale_miibus_statchg(device_t dev)252 ale_miibus_statchg(device_t dev)
253 {
254 struct ale_softc *sc;
255 struct mii_data *mii;
256 if_t ifp;
257 uint32_t reg;
258
259 sc = device_get_softc(dev);
260 mii = device_get_softc(sc->ale_miibus);
261 ifp = sc->ale_ifp;
262 if (mii == NULL || ifp == NULL ||
263 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
264 return;
265
266 sc->ale_flags &= ~ALE_FLAG_LINK;
267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
268 (IFM_ACTIVE | IFM_AVALID)) {
269 switch (IFM_SUBTYPE(mii->mii_media_active)) {
270 case IFM_10_T:
271 case IFM_100_TX:
272 sc->ale_flags |= ALE_FLAG_LINK;
273 break;
274 case IFM_1000_T:
275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
276 sc->ale_flags |= ALE_FLAG_LINK;
277 break;
278 default:
279 break;
280 }
281 }
282
283 /* Stop Rx/Tx MACs. */
284 ale_stop_mac(sc);
285
286 /* Program MACs with resolved speed/duplex/flow-control. */
287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
288 ale_mac_config(sc);
289 /* Reenable Tx/Rx MACs. */
290 reg = CSR_READ_4(sc, ALE_MAC_CFG);
291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
293 }
294 }
295
296 static void
ale_mediastatus(if_t ifp,struct ifmediareq * ifmr)297 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr)
298 {
299 struct ale_softc *sc;
300 struct mii_data *mii;
301
302 sc = if_getsoftc(ifp);
303 ALE_LOCK(sc);
304 if ((if_getflags(ifp) & IFF_UP) == 0) {
305 ALE_UNLOCK(sc);
306 return;
307 }
308 mii = device_get_softc(sc->ale_miibus);
309
310 mii_pollstat(mii);
311 ifmr->ifm_status = mii->mii_media_status;
312 ifmr->ifm_active = mii->mii_media_active;
313 ALE_UNLOCK(sc);
314 }
315
316 static int
ale_mediachange(if_t ifp)317 ale_mediachange(if_t ifp)
318 {
319 struct ale_softc *sc;
320 struct mii_data *mii;
321 struct mii_softc *miisc;
322 int error;
323
324 sc = if_getsoftc(ifp);
325 ALE_LOCK(sc);
326 mii = device_get_softc(sc->ale_miibus);
327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
328 PHY_RESET(miisc);
329 error = mii_mediachg(mii);
330 ALE_UNLOCK(sc);
331
332 return (error);
333 }
334
335 static int
ale_probe(device_t dev)336 ale_probe(device_t dev)
337 {
338 const struct ale_dev *sp;
339 int i;
340 uint16_t vendor, devid;
341
342 vendor = pci_get_vendor(dev);
343 devid = pci_get_device(dev);
344 sp = ale_devs;
345 for (i = 0; i < nitems(ale_devs); i++) {
346 if (vendor == sp->ale_vendorid &&
347 devid == sp->ale_deviceid) {
348 device_set_desc(dev, sp->ale_name);
349 return (BUS_PROBE_DEFAULT);
350 }
351 sp++;
352 }
353
354 return (ENXIO);
355 }
356
357 static void
ale_get_macaddr(struct ale_softc * sc)358 ale_get_macaddr(struct ale_softc *sc)
359 {
360 uint32_t ea[2], reg;
361 int i, vpdc;
362
363 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
364 if ((reg & SPI_VPD_ENB) != 0) {
365 reg &= ~SPI_VPD_ENB;
366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
367 }
368
369 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
370 /*
371 * PCI VPD capability found, let TWSI reload EEPROM.
372 * This will set ethernet address of controller.
373 */
374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
375 TWSI_CTRL_SW_LD_START);
376 for (i = 100; i > 0; i--) {
377 DELAY(1000);
378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
379 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
380 break;
381 }
382 if (i == 0)
383 device_printf(sc->ale_dev,
384 "reloading EEPROM timeout!\n");
385 } else {
386 if (bootverbose)
387 device_printf(sc->ale_dev,
388 "PCI VPD capability not found!\n");
389 }
390
391 ea[0] = CSR_READ_4(sc, ALE_PAR0);
392 ea[1] = CSR_READ_4(sc, ALE_PAR1);
393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
399 }
400
401 static void
ale_phy_reset(struct ale_softc * sc)402 ale_phy_reset(struct ale_softc *sc)
403 {
404
405 /* Reset magic from Linux. */
406 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
408 GPHY_CTRL_PHY_PLL_ON);
409 DELAY(1000);
410 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
413 DELAY(1000);
414
415 #define ATPHY_DBG_ADDR 0x1D
416 #define ATPHY_DBG_DATA 0x1E
417
418 /* Enable hibernation mode. */
419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
420 ATPHY_DBG_ADDR, 0x0B);
421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
422 ATPHY_DBG_DATA, 0xBC00);
423 /* Set Class A/B for all modes. */
424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
425 ATPHY_DBG_ADDR, 0x00);
426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
427 ATPHY_DBG_DATA, 0x02EF);
428 /* Enable 10BT power saving. */
429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
430 ATPHY_DBG_ADDR, 0x12);
431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
432 ATPHY_DBG_DATA, 0x4C04);
433 /* Adjust 1000T power. */
434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
435 ATPHY_DBG_ADDR, 0x04);
436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
437 ATPHY_DBG_ADDR, 0x8BBB);
438 /* 10BT center tap voltage. */
439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
440 ATPHY_DBG_ADDR, 0x05);
441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
442 ATPHY_DBG_ADDR, 0x2C46);
443
444 #undef ATPHY_DBG_ADDR
445 #undef ATPHY_DBG_DATA
446 DELAY(1000);
447 }
448
449 static int
ale_attach(device_t dev)450 ale_attach(device_t dev)
451 {
452 struct ale_softc *sc;
453 if_t ifp;
454 uint16_t burst;
455 int error, i, msic, msixc, pmc;
456 uint32_t rxf_len, txf_len;
457
458 error = 0;
459 sc = device_get_softc(dev);
460 sc->ale_dev = dev;
461
462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
463 MTX_DEF);
464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
465 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
466
467 /* Map the device. */
468 pci_enable_busmaster(dev);
469 sc->ale_res_spec = ale_res_spec_mem;
470 sc->ale_irq_spec = ale_irq_spec_legacy;
471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
472 if (error != 0) {
473 device_printf(dev, "cannot allocate memory resources.\n");
474 goto fail;
475 }
476
477 /* Set PHY address. */
478 sc->ale_phyaddr = ALE_PHY_ADDR;
479
480 /* Reset PHY. */
481 ale_phy_reset(sc);
482
483 /* Reset the ethernet controller. */
484 ale_reset(sc);
485
486 /* Get PCI and chip id/revision. */
487 sc->ale_rev = pci_get_revid(dev);
488 if (sc->ale_rev >= 0xF0) {
489 /* L2E Rev. B. AR8114 */
490 sc->ale_flags |= ALE_FLAG_FASTETHER;
491 } else {
492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
493 /* L1E AR8121 */
494 sc->ale_flags |= ALE_FLAG_JUMBO;
495 } else {
496 /* L2E Rev. A. AR8113 */
497 sc->ale_flags |= ALE_FLAG_FASTETHER;
498 }
499 }
500 /*
501 * All known controllers seems to require 4 bytes alignment
502 * of Tx buffers to make Tx checksum offload with custom
503 * checksum generation method work.
504 */
505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
506 /*
507 * All known controllers seems to have issues on Rx checksum
508 * offload for fragmented IP datagrams.
509 */
510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
511 /*
512 * Don't use Tx CMB. It is known to cause RRS update failure
513 * under certain circumstances. Typical phenomenon of the
514 * issue would be unexpected sequence number encountered in
515 * Rx handler.
516 */
517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
519 MASTER_CHIP_REV_SHIFT;
520 if (bootverbose) {
521 device_printf(dev, "PCI device revision : 0x%04x\n",
522 sc->ale_rev);
523 device_printf(dev, "Chip id/revision : 0x%04x\n",
524 sc->ale_chip_rev);
525 }
526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
528 /*
529 * Uninitialized hardware returns an invalid chip id/revision
530 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
531 */
532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
533 rxf_len == 0xFFFFFFF) {
534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
536 txf_len, rxf_len);
537 error = ENXIO;
538 goto fail;
539 }
540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
541
542 /* Allocate IRQ resources. */
543 msixc = pci_msix_count(dev);
544 msic = pci_msi_count(dev);
545 if (bootverbose) {
546 device_printf(dev, "MSIX count : %d\n", msixc);
547 device_printf(dev, "MSI count : %d\n", msic);
548 }
549
550 /* Prefer MSIX over MSI. */
551 if (msix_disable == 0 || msi_disable == 0) {
552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
553 pci_alloc_msix(dev, &msixc) == 0) {
554 if (msixc == ALE_MSIX_MESSAGES) {
555 device_printf(dev, "Using %d MSIX messages.\n",
556 msixc);
557 sc->ale_flags |= ALE_FLAG_MSIX;
558 sc->ale_irq_spec = ale_irq_spec_msix;
559 } else
560 pci_release_msi(dev);
561 }
562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
563 msic == ALE_MSI_MESSAGES &&
564 pci_alloc_msi(dev, &msic) == 0) {
565 if (msic == ALE_MSI_MESSAGES) {
566 device_printf(dev, "Using %d MSI messages.\n",
567 msic);
568 sc->ale_flags |= ALE_FLAG_MSI;
569 sc->ale_irq_spec = ale_irq_spec_msi;
570 } else
571 pci_release_msi(dev);
572 }
573 }
574
575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
576 if (error != 0) {
577 device_printf(dev, "cannot allocate IRQ resources.\n");
578 goto fail;
579 }
580
581 /* Get DMA parameters from PCIe device control register. */
582 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
583 sc->ale_flags |= ALE_FLAG_PCIE;
584 burst = pci_read_config(dev, i + 0x08, 2);
585 /* Max read request size. */
586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
587 DMA_CFG_RD_BURST_SHIFT;
588 /* Max payload size. */
589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
590 DMA_CFG_WR_BURST_SHIFT;
591 if (bootverbose) {
592 device_printf(dev, "Read request size : %d bytes.\n",
593 128 << ((burst >> 12) & 0x07));
594 device_printf(dev, "TLP payload size : %d bytes.\n",
595 128 << ((burst >> 5) & 0x07));
596 }
597 } else {
598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
600 }
601
602 /* Create device sysctl node. */
603 ale_sysctl_node(sc);
604
605 if ((error = ale_dma_alloc(sc)) != 0)
606 goto fail;
607
608 /* Load station address. */
609 ale_get_macaddr(sc);
610
611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
612 if (ifp == NULL) {
613 device_printf(dev, "cannot allocate ifnet structure.\n");
614 error = ENXIO;
615 goto fail;
616 }
617
618 if_setsoftc(ifp, sc);
619 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
620 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
621 if_setioctlfn(ifp, ale_ioctl);
622 if_setstartfn(ifp, ale_start);
623 if_setinitfn(ifp, ale_init);
624 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1);
625 if_setsendqready(ifp);
626 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4);
627 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO);
628 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
629 sc->ale_flags |= ALE_FLAG_PMCAP;
630 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0);
631 }
632 if_setcapenable(ifp, if_getcapabilities(ifp));
633
634 /* Set up MII bus. */
635 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
636 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
637 MIIF_DOPAUSE);
638 if (error != 0) {
639 device_printf(dev, "attaching PHYs failed\n");
640 goto fail;
641 }
642
643 ether_ifattach(ifp, sc->ale_eaddr);
644
645 /* VLAN capability setup. */
646 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
647 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0);
648 if_setcapenable(ifp, if_getcapabilities(ifp));
649 /*
650 * Even though controllers supported by ale(3) have Rx checksum
651 * offload bug the workaround for fragmented frames seemed to
652 * work so far. However it seems Rx checksum offload does not
653 * work under certain conditions. So disable Rx checksum offload
654 * until I find more clue about it but allow users to override it.
655 */
656 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM);
657
658 /* Tell the upper layer(s) we support long frames. */
659 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
660
661 /* Create local taskq. */
662 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
663 taskqueue_thread_enqueue, &sc->ale_tq);
664 if (sc->ale_tq == NULL) {
665 device_printf(dev, "could not create taskqueue.\n");
666 ether_ifdetach(ifp);
667 error = ENXIO;
668 goto fail;
669 }
670 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
671 device_get_nameunit(sc->ale_dev));
672
673 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
674 msic = ALE_MSIX_MESSAGES;
675 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
676 msic = ALE_MSI_MESSAGES;
677 else
678 msic = 1;
679 for (i = 0; i < msic; i++) {
680 error = bus_setup_intr(dev, sc->ale_irq[i],
681 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
682 &sc->ale_intrhand[i]);
683 if (error != 0)
684 break;
685 }
686 if (error != 0) {
687 device_printf(dev, "could not set up interrupt handler.\n");
688 taskqueue_free(sc->ale_tq);
689 sc->ale_tq = NULL;
690 ether_ifdetach(ifp);
691 goto fail;
692 }
693
694 fail:
695 if (error != 0)
696 ale_detach(dev);
697
698 return (error);
699 }
700
701 static int
ale_detach(device_t dev)702 ale_detach(device_t dev)
703 {
704 struct ale_softc *sc;
705 if_t ifp;
706 int i, msic;
707
708 sc = device_get_softc(dev);
709
710 ifp = sc->ale_ifp;
711 if (device_is_attached(dev)) {
712 ether_ifdetach(ifp);
713 ALE_LOCK(sc);
714 ale_stop(sc);
715 ALE_UNLOCK(sc);
716 callout_drain(&sc->ale_tick_ch);
717 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
718 }
719
720 if (sc->ale_tq != NULL) {
721 taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
722 taskqueue_free(sc->ale_tq);
723 sc->ale_tq = NULL;
724 }
725
726 if (sc->ale_miibus != NULL) {
727 device_delete_child(dev, sc->ale_miibus);
728 sc->ale_miibus = NULL;
729 }
730 bus_generic_detach(dev);
731 ale_dma_free(sc);
732
733 if (ifp != NULL) {
734 if_free(ifp);
735 sc->ale_ifp = NULL;
736 }
737
738 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
739 msic = ALE_MSIX_MESSAGES;
740 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
741 msic = ALE_MSI_MESSAGES;
742 else
743 msic = 1;
744 for (i = 0; i < msic; i++) {
745 if (sc->ale_intrhand[i] != NULL) {
746 bus_teardown_intr(dev, sc->ale_irq[i],
747 sc->ale_intrhand[i]);
748 sc->ale_intrhand[i] = NULL;
749 }
750 }
751
752 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
753 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
754 pci_release_msi(dev);
755 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
756 mtx_destroy(&sc->ale_mtx);
757
758 return (0);
759 }
760
761 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \
762 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
763
764 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \
765 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
766
767 static void
ale_sysctl_node(struct ale_softc * sc)768 ale_sysctl_node(struct ale_softc *sc)
769 {
770 struct sysctl_ctx_list *ctx;
771 struct sysctl_oid_list *child, *parent;
772 struct sysctl_oid *tree;
773 struct ale_hw_stats *stats;
774 int error;
775
776 stats = &sc->ale_stats;
777 ctx = device_get_sysctl_ctx(sc->ale_dev);
778 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
779
780 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
781 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod,
782 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
783 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
784 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod,
785 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
786 /* Pull in device tunables. */
787 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
788 error = resource_int_value(device_get_name(sc->ale_dev),
789 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
790 if (error == 0) {
791 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
792 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
793 device_printf(sc->ale_dev, "int_rx_mod value out of "
794 "range; using default: %d\n",
795 ALE_IM_RX_TIMER_DEFAULT);
796 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
797 }
798 }
799 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
800 error = resource_int_value(device_get_name(sc->ale_dev),
801 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
802 if (error == 0) {
803 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
804 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
805 device_printf(sc->ale_dev, "int_tx_mod value out of "
806 "range; using default: %d\n",
807 ALE_IM_TX_TIMER_DEFAULT);
808 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
809 }
810 }
811 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
812 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
813 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I",
814 "max number of Rx events to process");
815 /* Pull in device tunables. */
816 sc->ale_process_limit = ALE_PROC_DEFAULT;
817 error = resource_int_value(device_get_name(sc->ale_dev),
818 device_get_unit(sc->ale_dev), "process_limit",
819 &sc->ale_process_limit);
820 if (error == 0) {
821 if (sc->ale_process_limit < ALE_PROC_MIN ||
822 sc->ale_process_limit > ALE_PROC_MAX) {
823 device_printf(sc->ale_dev,
824 "process_limit value out of range; "
825 "using default: %d\n", ALE_PROC_DEFAULT);
826 sc->ale_process_limit = ALE_PROC_DEFAULT;
827 }
828 }
829
830 /* Misc statistics. */
831 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
832 &stats->reset_brk_seq,
833 "Controller resets due to broken Rx sequnce number");
834
835 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
836 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics");
837 parent = SYSCTL_CHILDREN(tree);
838
839 /* Rx statistics. */
840 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
841 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
842 child = SYSCTL_CHILDREN(tree);
843 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
844 &stats->rx_frames, "Good frames");
845 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
846 &stats->rx_bcast_frames, "Good broadcast frames");
847 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
848 &stats->rx_mcast_frames, "Good multicast frames");
849 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
850 &stats->rx_pause_frames, "Pause control frames");
851 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
852 &stats->rx_control_frames, "Control frames");
853 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
854 &stats->rx_crcerrs, "CRC errors");
855 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
856 &stats->rx_lenerrs, "Frames with length mismatched");
857 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
858 &stats->rx_bytes, "Good octets");
859 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
860 &stats->rx_bcast_bytes, "Good broadcast octets");
861 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
862 &stats->rx_mcast_bytes, "Good multicast octets");
863 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
864 &stats->rx_runts, "Too short frames");
865 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
866 &stats->rx_fragments, "Fragmented frames");
867 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
868 &stats->rx_pkts_64, "64 bytes frames");
869 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
870 &stats->rx_pkts_65_127, "65 to 127 bytes frames");
871 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
872 &stats->rx_pkts_128_255, "128 to 255 bytes frames");
873 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
874 &stats->rx_pkts_256_511, "256 to 511 bytes frames");
875 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
876 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
877 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
878 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
880 &stats->rx_pkts_1519_max, "1519 to max frames");
881 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
882 &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
883 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
884 &stats->rx_fifo_oflows, "FIFO overflows");
885 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
886 &stats->rx_rrs_errs, "Return status write-back errors");
887 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
888 &stats->rx_alignerrs, "Alignment errors");
889 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
890 &stats->rx_pkts_filtered,
891 "Frames dropped due to address filtering");
892
893 /* Tx statistics. */
894 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
895 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
896 child = SYSCTL_CHILDREN(tree);
897 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
898 &stats->tx_frames, "Good frames");
899 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
900 &stats->tx_bcast_frames, "Good broadcast frames");
901 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
902 &stats->tx_mcast_frames, "Good multicast frames");
903 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
904 &stats->tx_pause_frames, "Pause control frames");
905 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
906 &stats->tx_control_frames, "Control frames");
907 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
908 &stats->tx_excess_defer, "Frames with excessive derferrals");
909 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
910 &stats->tx_excess_defer, "Frames with derferrals");
911 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
912 &stats->tx_bytes, "Good octets");
913 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
914 &stats->tx_bcast_bytes, "Good broadcast octets");
915 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
916 &stats->tx_mcast_bytes, "Good multicast octets");
917 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
918 &stats->tx_pkts_64, "64 bytes frames");
919 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
920 &stats->tx_pkts_65_127, "65 to 127 bytes frames");
921 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
922 &stats->tx_pkts_128_255, "128 to 255 bytes frames");
923 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
924 &stats->tx_pkts_256_511, "256 to 511 bytes frames");
925 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
926 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
927 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
928 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
930 &stats->tx_pkts_1519_max, "1519 to max frames");
931 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
932 &stats->tx_single_colls, "Single collisions");
933 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
934 &stats->tx_multi_colls, "Multiple collisions");
935 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
936 &stats->tx_late_colls, "Late collisions");
937 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
938 &stats->tx_excess_colls, "Excessive collisions");
939 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
940 &stats->tx_underrun, "FIFO underruns");
941 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
942 &stats->tx_desc_underrun, "Descriptor write-back errors");
943 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
944 &stats->tx_lenerrs, "Frames with length mismatched");
945 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
946 &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
947 }
948
949 #undef ALE_SYSCTL_STAT_ADD32
950 #undef ALE_SYSCTL_STAT_ADD64
951
952 struct ale_dmamap_arg {
953 bus_addr_t ale_busaddr;
954 };
955
956 static void
ale_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nsegs,int error)957 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
958 {
959 struct ale_dmamap_arg *ctx;
960
961 if (error != 0)
962 return;
963
964 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
965
966 ctx = (struct ale_dmamap_arg *)arg;
967 ctx->ale_busaddr = segs[0].ds_addr;
968 }
969
970 /*
971 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
972 * which specifies high address region of DMA blocks. Therefore these
973 * blocks should have the same high address of given 4GB address
974 * space(i.e. crossing 4GB boundary is not allowed).
975 */
976 static int
ale_check_boundary(struct ale_softc * sc)977 ale_check_boundary(struct ale_softc *sc)
978 {
979 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
980 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
981
982 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
983 sc->ale_pagesize;
984 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
985 sc->ale_pagesize;
986 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
987 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
988 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
989 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
990
991 if ((ALE_ADDR_HI(tx_ring_end) !=
992 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
993 (ALE_ADDR_HI(rx_page_end[0]) !=
994 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
995 (ALE_ADDR_HI(rx_page_end[1]) !=
996 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
997 (ALE_ADDR_HI(tx_cmb_end) !=
998 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
999 (ALE_ADDR_HI(rx_cmb_end[0]) !=
1000 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
1001 (ALE_ADDR_HI(rx_cmb_end[1]) !=
1002 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
1003 return (EFBIG);
1004
1005 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
1006 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
1007 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
1008 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
1009 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
1010 return (EFBIG);
1011
1012 return (0);
1013 }
1014
1015 static int
ale_dma_alloc(struct ale_softc * sc)1016 ale_dma_alloc(struct ale_softc *sc)
1017 {
1018 struct ale_txdesc *txd;
1019 bus_addr_t lowaddr;
1020 struct ale_dmamap_arg ctx;
1021 int error, guard_size, i;
1022
1023 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1024 guard_size = ALE_JUMBO_FRAMELEN;
1025 else
1026 guard_size = ALE_MAX_FRAMELEN;
1027 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1028 ALE_RX_PAGE_ALIGN);
1029 lowaddr = BUS_SPACE_MAXADDR;
1030 again:
1031 /* Create parent DMA tag. */
1032 error = bus_dma_tag_create(
1033 bus_get_dma_tag(sc->ale_dev), /* parent */
1034 1, 0, /* alignment, boundary */
1035 lowaddr, /* lowaddr */
1036 BUS_SPACE_MAXADDR, /* highaddr */
1037 NULL, NULL, /* filter, filterarg */
1038 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1039 0, /* nsegments */
1040 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1041 0, /* flags */
1042 NULL, NULL, /* lockfunc, lockarg */
1043 &sc->ale_cdata.ale_parent_tag);
1044 if (error != 0) {
1045 device_printf(sc->ale_dev,
1046 "could not create parent DMA tag.\n");
1047 goto fail;
1048 }
1049
1050 /* Create DMA tag for Tx descriptor ring. */
1051 error = bus_dma_tag_create(
1052 sc->ale_cdata.ale_parent_tag, /* parent */
1053 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */
1054 BUS_SPACE_MAXADDR, /* lowaddr */
1055 BUS_SPACE_MAXADDR, /* highaddr */
1056 NULL, NULL, /* filter, filterarg */
1057 ALE_TX_RING_SZ, /* maxsize */
1058 1, /* nsegments */
1059 ALE_TX_RING_SZ, /* maxsegsize */
1060 0, /* flags */
1061 NULL, NULL, /* lockfunc, lockarg */
1062 &sc->ale_cdata.ale_tx_ring_tag);
1063 if (error != 0) {
1064 device_printf(sc->ale_dev,
1065 "could not create Tx ring DMA tag.\n");
1066 goto fail;
1067 }
1068
1069 /* Create DMA tag for Rx pages. */
1070 for (i = 0; i < ALE_RX_PAGES; i++) {
1071 error = bus_dma_tag_create(
1072 sc->ale_cdata.ale_parent_tag, /* parent */
1073 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */
1074 BUS_SPACE_MAXADDR, /* lowaddr */
1075 BUS_SPACE_MAXADDR, /* highaddr */
1076 NULL, NULL, /* filter, filterarg */
1077 sc->ale_pagesize, /* maxsize */
1078 1, /* nsegments */
1079 sc->ale_pagesize, /* maxsegsize */
1080 0, /* flags */
1081 NULL, NULL, /* lockfunc, lockarg */
1082 &sc->ale_cdata.ale_rx_page[i].page_tag);
1083 if (error != 0) {
1084 device_printf(sc->ale_dev,
1085 "could not create Rx page %d DMA tag.\n", i);
1086 goto fail;
1087 }
1088 }
1089
1090 /* Create DMA tag for Tx coalescing message block. */
1091 error = bus_dma_tag_create(
1092 sc->ale_cdata.ale_parent_tag, /* parent */
1093 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1094 BUS_SPACE_MAXADDR, /* lowaddr */
1095 BUS_SPACE_MAXADDR, /* highaddr */
1096 NULL, NULL, /* filter, filterarg */
1097 ALE_TX_CMB_SZ, /* maxsize */
1098 1, /* nsegments */
1099 ALE_TX_CMB_SZ, /* maxsegsize */
1100 0, /* flags */
1101 NULL, NULL, /* lockfunc, lockarg */
1102 &sc->ale_cdata.ale_tx_cmb_tag);
1103 if (error != 0) {
1104 device_printf(sc->ale_dev,
1105 "could not create Tx CMB DMA tag.\n");
1106 goto fail;
1107 }
1108
1109 /* Create DMA tag for Rx coalescing message block. */
1110 for (i = 0; i < ALE_RX_PAGES; i++) {
1111 error = bus_dma_tag_create(
1112 sc->ale_cdata.ale_parent_tag, /* parent */
1113 ALE_CMB_ALIGN, 0, /* alignment, boundary */
1114 BUS_SPACE_MAXADDR, /* lowaddr */
1115 BUS_SPACE_MAXADDR, /* highaddr */
1116 NULL, NULL, /* filter, filterarg */
1117 ALE_RX_CMB_SZ, /* maxsize */
1118 1, /* nsegments */
1119 ALE_RX_CMB_SZ, /* maxsegsize */
1120 0, /* flags */
1121 NULL, NULL, /* lockfunc, lockarg */
1122 &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1123 if (error != 0) {
1124 device_printf(sc->ale_dev,
1125 "could not create Rx page %d CMB DMA tag.\n", i);
1126 goto fail;
1127 }
1128 }
1129
1130 /* Allocate DMA'able memory and load the DMA map for Tx ring. */
1131 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1132 (void **)&sc->ale_cdata.ale_tx_ring,
1133 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1134 &sc->ale_cdata.ale_tx_ring_map);
1135 if (error != 0) {
1136 device_printf(sc->ale_dev,
1137 "could not allocate DMA'able memory for Tx ring.\n");
1138 goto fail;
1139 }
1140 ctx.ale_busaddr = 0;
1141 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1142 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1143 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1144 if (error != 0 || ctx.ale_busaddr == 0) {
1145 device_printf(sc->ale_dev,
1146 "could not load DMA'able memory for Tx ring.\n");
1147 goto fail;
1148 }
1149 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1150
1151 /* Rx pages. */
1152 for (i = 0; i < ALE_RX_PAGES; i++) {
1153 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1154 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1155 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1156 &sc->ale_cdata.ale_rx_page[i].page_map);
1157 if (error != 0) {
1158 device_printf(sc->ale_dev,
1159 "could not allocate DMA'able memory for "
1160 "Rx page %d.\n", i);
1161 goto fail;
1162 }
1163 ctx.ale_busaddr = 0;
1164 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1165 sc->ale_cdata.ale_rx_page[i].page_map,
1166 sc->ale_cdata.ale_rx_page[i].page_addr,
1167 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1168 if (error != 0 || ctx.ale_busaddr == 0) {
1169 device_printf(sc->ale_dev,
1170 "could not load DMA'able memory for "
1171 "Rx page %d.\n", i);
1172 goto fail;
1173 }
1174 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1175 }
1176
1177 /* Tx CMB. */
1178 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1179 (void **)&sc->ale_cdata.ale_tx_cmb,
1180 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1181 &sc->ale_cdata.ale_tx_cmb_map);
1182 if (error != 0) {
1183 device_printf(sc->ale_dev,
1184 "could not allocate DMA'able memory for Tx CMB.\n");
1185 goto fail;
1186 }
1187 ctx.ale_busaddr = 0;
1188 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1189 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1190 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1191 if (error != 0 || ctx.ale_busaddr == 0) {
1192 device_printf(sc->ale_dev,
1193 "could not load DMA'able memory for Tx CMB.\n");
1194 goto fail;
1195 }
1196 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1197
1198 /* Rx CMB. */
1199 for (i = 0; i < ALE_RX_PAGES; i++) {
1200 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1201 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1202 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1203 &sc->ale_cdata.ale_rx_page[i].cmb_map);
1204 if (error != 0) {
1205 device_printf(sc->ale_dev, "could not allocate "
1206 "DMA'able memory for Rx page %d CMB.\n", i);
1207 goto fail;
1208 }
1209 ctx.ale_busaddr = 0;
1210 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1211 sc->ale_cdata.ale_rx_page[i].cmb_map,
1212 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1213 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1214 if (error != 0 || ctx.ale_busaddr == 0) {
1215 device_printf(sc->ale_dev, "could not load DMA'able "
1216 "memory for Rx page %d CMB.\n", i);
1217 goto fail;
1218 }
1219 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1220 }
1221
1222 /*
1223 * Tx descriptors/RXF0/CMB DMA blocks share the same
1224 * high address region of 64bit DMA address space.
1225 */
1226 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1227 (error = ale_check_boundary(sc)) != 0) {
1228 device_printf(sc->ale_dev, "4GB boundary crossed, "
1229 "switching to 32bit DMA addressing mode.\n");
1230 ale_dma_free(sc);
1231 /*
1232 * Limit max allowable DMA address space to 32bit
1233 * and try again.
1234 */
1235 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1236 goto again;
1237 }
1238
1239 /*
1240 * Create Tx buffer parent tag.
1241 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1242 * needs separate parent DMA tag as parent DMA address space
1243 * could be restricted to be within 32bit address space by
1244 * 4GB boundary crossing.
1245 */
1246 error = bus_dma_tag_create(
1247 bus_get_dma_tag(sc->ale_dev), /* parent */
1248 1, 0, /* alignment, boundary */
1249 BUS_SPACE_MAXADDR, /* lowaddr */
1250 BUS_SPACE_MAXADDR, /* highaddr */
1251 NULL, NULL, /* filter, filterarg */
1252 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1253 0, /* nsegments */
1254 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1255 0, /* flags */
1256 NULL, NULL, /* lockfunc, lockarg */
1257 &sc->ale_cdata.ale_buffer_tag);
1258 if (error != 0) {
1259 device_printf(sc->ale_dev,
1260 "could not create parent buffer DMA tag.\n");
1261 goto fail;
1262 }
1263
1264 /* Create DMA tag for Tx buffers. */
1265 error = bus_dma_tag_create(
1266 sc->ale_cdata.ale_buffer_tag, /* parent */
1267 1, 0, /* alignment, boundary */
1268 BUS_SPACE_MAXADDR, /* lowaddr */
1269 BUS_SPACE_MAXADDR, /* highaddr */
1270 NULL, NULL, /* filter, filterarg */
1271 ALE_TSO_MAXSIZE, /* maxsize */
1272 ALE_MAXTXSEGS, /* nsegments */
1273 ALE_TSO_MAXSEGSIZE, /* maxsegsize */
1274 0, /* flags */
1275 NULL, NULL, /* lockfunc, lockarg */
1276 &sc->ale_cdata.ale_tx_tag);
1277 if (error != 0) {
1278 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1279 goto fail;
1280 }
1281
1282 /* Create DMA maps for Tx buffers. */
1283 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1284 txd = &sc->ale_cdata.ale_txdesc[i];
1285 txd->tx_m = NULL;
1286 txd->tx_dmamap = NULL;
1287 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1288 &txd->tx_dmamap);
1289 if (error != 0) {
1290 device_printf(sc->ale_dev,
1291 "could not create Tx dmamap.\n");
1292 goto fail;
1293 }
1294 }
1295
1296 fail:
1297 return (error);
1298 }
1299
1300 static void
ale_dma_free(struct ale_softc * sc)1301 ale_dma_free(struct ale_softc *sc)
1302 {
1303 struct ale_txdesc *txd;
1304 int i;
1305
1306 /* Tx buffers. */
1307 if (sc->ale_cdata.ale_tx_tag != NULL) {
1308 for (i = 0; i < ALE_TX_RING_CNT; i++) {
1309 txd = &sc->ale_cdata.ale_txdesc[i];
1310 if (txd->tx_dmamap != NULL) {
1311 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1312 txd->tx_dmamap);
1313 txd->tx_dmamap = NULL;
1314 }
1315 }
1316 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1317 sc->ale_cdata.ale_tx_tag = NULL;
1318 }
1319 /* Tx descriptor ring. */
1320 if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1321 if (sc->ale_cdata.ale_tx_ring_paddr != 0)
1322 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1323 sc->ale_cdata.ale_tx_ring_map);
1324 if (sc->ale_cdata.ale_tx_ring != NULL)
1325 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1326 sc->ale_cdata.ale_tx_ring,
1327 sc->ale_cdata.ale_tx_ring_map);
1328 sc->ale_cdata.ale_tx_ring_paddr = 0;
1329 sc->ale_cdata.ale_tx_ring = NULL;
1330 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1331 sc->ale_cdata.ale_tx_ring_tag = NULL;
1332 }
1333 /* Rx page block. */
1334 for (i = 0; i < ALE_RX_PAGES; i++) {
1335 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1336 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0)
1337 bus_dmamap_unload(
1338 sc->ale_cdata.ale_rx_page[i].page_tag,
1339 sc->ale_cdata.ale_rx_page[i].page_map);
1340 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1341 bus_dmamem_free(
1342 sc->ale_cdata.ale_rx_page[i].page_tag,
1343 sc->ale_cdata.ale_rx_page[i].page_addr,
1344 sc->ale_cdata.ale_rx_page[i].page_map);
1345 sc->ale_cdata.ale_rx_page[i].page_paddr = 0;
1346 sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1347 bus_dma_tag_destroy(
1348 sc->ale_cdata.ale_rx_page[i].page_tag);
1349 sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1350 }
1351 }
1352 /* Rx CMB. */
1353 for (i = 0; i < ALE_RX_PAGES; i++) {
1354 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1355 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0)
1356 bus_dmamap_unload(
1357 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1358 sc->ale_cdata.ale_rx_page[i].cmb_map);
1359 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1360 bus_dmamem_free(
1361 sc->ale_cdata.ale_rx_page[i].cmb_tag,
1362 sc->ale_cdata.ale_rx_page[i].cmb_addr,
1363 sc->ale_cdata.ale_rx_page[i].cmb_map);
1364 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0;
1365 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1366 bus_dma_tag_destroy(
1367 sc->ale_cdata.ale_rx_page[i].cmb_tag);
1368 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1369 }
1370 }
1371 /* Tx CMB. */
1372 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1373 if (sc->ale_cdata.ale_tx_cmb_paddr != 0)
1374 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1375 sc->ale_cdata.ale_tx_cmb_map);
1376 if (sc->ale_cdata.ale_tx_cmb != NULL)
1377 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1378 sc->ale_cdata.ale_tx_cmb,
1379 sc->ale_cdata.ale_tx_cmb_map);
1380 sc->ale_cdata.ale_tx_cmb_paddr = 0;
1381 sc->ale_cdata.ale_tx_cmb = NULL;
1382 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1383 sc->ale_cdata.ale_tx_cmb_tag = NULL;
1384 }
1385 if (sc->ale_cdata.ale_buffer_tag != NULL) {
1386 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1387 sc->ale_cdata.ale_buffer_tag = NULL;
1388 }
1389 if (sc->ale_cdata.ale_parent_tag != NULL) {
1390 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1391 sc->ale_cdata.ale_parent_tag = NULL;
1392 }
1393 }
1394
1395 static int
ale_shutdown(device_t dev)1396 ale_shutdown(device_t dev)
1397 {
1398
1399 return (ale_suspend(dev));
1400 }
1401
1402 /*
1403 * Note, this driver resets the link speed to 10/100Mbps by
1404 * restarting auto-negotiation in suspend/shutdown phase but we
1405 * don't know whether that auto-negotiation would succeed or not
1406 * as driver has no control after powering off/suspend operation.
1407 * If the renegotiation fail WOL may not work. Running at 1Gbps
1408 * will draw more power than 375mA at 3.3V which is specified in
1409 * PCI specification and that would result in complete
1410 * shutdowning power to ethernet controller.
1411 *
1412 * TODO
1413 * Save current negotiated media speed/duplex/flow-control to
1414 * softc and restore the same link again after resuming. PHY
1415 * handling such as power down/resetting to 100Mbps may be better
1416 * handled in suspend method in phy driver.
1417 */
1418 static void
ale_setlinkspeed(struct ale_softc * sc)1419 ale_setlinkspeed(struct ale_softc *sc)
1420 {
1421 struct mii_data *mii;
1422 int aneg, i;
1423
1424 mii = device_get_softc(sc->ale_miibus);
1425 mii_pollstat(mii);
1426 aneg = 0;
1427 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1428 (IFM_ACTIVE | IFM_AVALID)) {
1429 switch IFM_SUBTYPE(mii->mii_media_active) {
1430 case IFM_10_T:
1431 case IFM_100_TX:
1432 return;
1433 case IFM_1000_T:
1434 aneg++;
1435 break;
1436 default:
1437 break;
1438 }
1439 }
1440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1442 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1443 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1444 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1445 DELAY(1000);
1446 if (aneg != 0) {
1447 /*
1448 * Poll link state until ale(4) get a 10/100Mbps link.
1449 */
1450 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1451 mii_pollstat(mii);
1452 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1453 == (IFM_ACTIVE | IFM_AVALID)) {
1454 switch (IFM_SUBTYPE(
1455 mii->mii_media_active)) {
1456 case IFM_10_T:
1457 case IFM_100_TX:
1458 ale_mac_config(sc);
1459 return;
1460 default:
1461 break;
1462 }
1463 }
1464 ALE_UNLOCK(sc);
1465 pause("alelnk", hz);
1466 ALE_LOCK(sc);
1467 }
1468 if (i == MII_ANEGTICKS_GIGE)
1469 device_printf(sc->ale_dev,
1470 "establishing a link failed, WOL may not work!");
1471 }
1472 /*
1473 * No link, force MAC to have 100Mbps, full-duplex link.
1474 * This is the last resort and may/may not work.
1475 */
1476 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1477 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1478 ale_mac_config(sc);
1479 }
1480
1481 static void
ale_setwol(struct ale_softc * sc)1482 ale_setwol(struct ale_softc *sc)
1483 {
1484 if_t ifp;
1485 uint32_t reg, pmcs;
1486 uint16_t pmstat;
1487 int pmc;
1488
1489 ALE_LOCK_ASSERT(sc);
1490
1491 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1492 /* Disable WOL. */
1493 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1494 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1495 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1496 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1497 /* Force PHY power down. */
1498 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1499 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1500 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1501 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1502 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1503 return;
1504 }
1505
1506 ifp = sc->ale_ifp;
1507 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
1508 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1509 ale_setlinkspeed(sc);
1510 }
1511
1512 pmcs = 0;
1513 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
1514 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1515 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1516 reg = CSR_READ_4(sc, ALE_MAC_CFG);
1517 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1518 MAC_CFG_BCAST);
1519 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0)
1520 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1521 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1522 reg |= MAC_CFG_RX_ENB;
1523 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1524
1525 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) {
1526 /* WOL disabled, PHY power down. */
1527 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1528 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1529 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1530 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1531 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1532 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1533 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1534 GPHY_CTRL_PWDOWN_HW);
1535 }
1536 /* Request PME. */
1537 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1538 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1539 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
1540 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1541 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1542 }
1543
1544 static int
ale_suspend(device_t dev)1545 ale_suspend(device_t dev)
1546 {
1547 struct ale_softc *sc;
1548
1549 sc = device_get_softc(dev);
1550
1551 ALE_LOCK(sc);
1552 ale_stop(sc);
1553 ale_setwol(sc);
1554 ALE_UNLOCK(sc);
1555
1556 return (0);
1557 }
1558
1559 static int
ale_resume(device_t dev)1560 ale_resume(device_t dev)
1561 {
1562 struct ale_softc *sc;
1563 if_t ifp;
1564 int pmc;
1565 uint16_t pmstat;
1566
1567 sc = device_get_softc(dev);
1568
1569 ALE_LOCK(sc);
1570 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1571 /* Disable PME and clear PME status. */
1572 pmstat = pci_read_config(sc->ale_dev,
1573 pmc + PCIR_POWER_STATUS, 2);
1574 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1575 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1576 pci_write_config(sc->ale_dev,
1577 pmc + PCIR_POWER_STATUS, pmstat, 2);
1578 }
1579 }
1580 /* Reset PHY. */
1581 ale_phy_reset(sc);
1582 ifp = sc->ale_ifp;
1583 if ((if_getflags(ifp) & IFF_UP) != 0) {
1584 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1585 ale_init_locked(sc);
1586 }
1587 ALE_UNLOCK(sc);
1588
1589 return (0);
1590 }
1591
1592 static int
ale_encap(struct ale_softc * sc,struct mbuf ** m_head)1593 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1594 {
1595 struct ale_txdesc *txd, *txd_last;
1596 struct tx_desc *desc;
1597 struct mbuf *m;
1598 struct ip *ip;
1599 struct tcphdr *tcp;
1600 bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1601 bus_dmamap_t map;
1602 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1603 int error, i, nsegs, prod, si;
1604
1605 ALE_LOCK_ASSERT(sc);
1606
1607 M_ASSERTPKTHDR((*m_head));
1608
1609 m = *m_head;
1610 ip = NULL;
1611 tcp = NULL;
1612 cflags = vtag = 0;
1613 ip_off = poff = 0;
1614 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1615 /*
1616 * AR81xx requires offset of TCP/UDP payload in its Tx
1617 * descriptor to perform hardware Tx checksum offload.
1618 * Additionally, TSO requires IP/TCP header size and
1619 * modification of IP/TCP header in order to make TSO
1620 * engine work. This kind of operation takes many CPU
1621 * cycles on FreeBSD so fast host CPU is required to
1622 * get smooth TSO performance.
1623 */
1624 struct ether_header *eh;
1625
1626 if (M_WRITABLE(m) == 0) {
1627 /* Get a writable copy. */
1628 m = m_dup(*m_head, M_NOWAIT);
1629 /* Release original mbufs. */
1630 m_freem(*m_head);
1631 if (m == NULL) {
1632 *m_head = NULL;
1633 return (ENOBUFS);
1634 }
1635 *m_head = m;
1636 }
1637
1638 /*
1639 * Buggy-controller requires 4 byte aligned Tx buffer
1640 * to make custom checksum offload work.
1641 */
1642 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1643 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1644 (mtod(m, intptr_t) & 3) != 0) {
1645 m = m_defrag(*m_head, M_NOWAIT);
1646 if (m == NULL) {
1647 m_freem(*m_head);
1648 *m_head = NULL;
1649 return (ENOBUFS);
1650 }
1651 *m_head = m;
1652 }
1653
1654 ip_off = sizeof(struct ether_header);
1655 m = m_pullup(m, ip_off);
1656 if (m == NULL) {
1657 *m_head = NULL;
1658 return (ENOBUFS);
1659 }
1660 eh = mtod(m, struct ether_header *);
1661 /*
1662 * Check if hardware VLAN insertion is off.
1663 * Additional check for LLC/SNAP frame?
1664 */
1665 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1666 ip_off = sizeof(struct ether_vlan_header);
1667 m = m_pullup(m, ip_off);
1668 if (m == NULL) {
1669 *m_head = NULL;
1670 return (ENOBUFS);
1671 }
1672 }
1673 m = m_pullup(m, ip_off + sizeof(struct ip));
1674 if (m == NULL) {
1675 *m_head = NULL;
1676 return (ENOBUFS);
1677 }
1678 ip = (struct ip *)(mtod(m, char *) + ip_off);
1679 poff = ip_off + (ip->ip_hl << 2);
1680 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1681 /*
1682 * XXX
1683 * AR81xx requires the first descriptor should
1684 * not include any TCP playload for TSO case.
1685 * (i.e. ethernet header + IP + TCP header only)
1686 * m_pullup(9) above will ensure this too.
1687 * However it's not correct if the first mbuf
1688 * of the chain does not use cluster.
1689 */
1690 m = m_pullup(m, poff + sizeof(struct tcphdr));
1691 if (m == NULL) {
1692 *m_head = NULL;
1693 return (ENOBUFS);
1694 }
1695 ip = (struct ip *)(mtod(m, char *) + ip_off);
1696 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1697 m = m_pullup(m, poff + (tcp->th_off << 2));
1698 if (m == NULL) {
1699 *m_head = NULL;
1700 return (ENOBUFS);
1701 }
1702 /*
1703 * AR81xx requires IP/TCP header size and offset as
1704 * well as TCP pseudo checksum which complicates
1705 * TSO configuration. I guess this comes from the
1706 * adherence to Microsoft NDIS Large Send
1707 * specification which requires insertion of
1708 * pseudo checksum by upper stack. The pseudo
1709 * checksum that NDIS refers to doesn't include
1710 * TCP payload length so ale(4) should recompute
1711 * the pseudo checksum here. Hopefully this wouldn't
1712 * be much burden on modern CPUs.
1713 * Reset IP checksum and recompute TCP pseudo
1714 * checksum as NDIS specification said.
1715 */
1716 ip->ip_sum = 0;
1717 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1718 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1719 }
1720 *m_head = m;
1721 }
1722
1723 si = prod = sc->ale_cdata.ale_tx_prod;
1724 txd = &sc->ale_cdata.ale_txdesc[prod];
1725 txd_last = txd;
1726 map = txd->tx_dmamap;
1727
1728 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1729 *m_head, txsegs, &nsegs, 0);
1730 if (error == EFBIG) {
1731 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS);
1732 if (m == NULL) {
1733 m_freem(*m_head);
1734 *m_head = NULL;
1735 return (ENOMEM);
1736 }
1737 *m_head = m;
1738 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1739 *m_head, txsegs, &nsegs, 0);
1740 if (error != 0) {
1741 m_freem(*m_head);
1742 *m_head = NULL;
1743 return (error);
1744 }
1745 } else if (error != 0)
1746 return (error);
1747 if (nsegs == 0) {
1748 m_freem(*m_head);
1749 *m_head = NULL;
1750 return (EIO);
1751 }
1752
1753 /* Check descriptor overrun. */
1754 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1755 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1756 return (ENOBUFS);
1757 }
1758 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1759
1760 m = *m_head;
1761 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1762 /* Request TSO and set MSS. */
1763 cflags |= ALE_TD_TSO;
1764 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1765 /* Set IP/TCP header size. */
1766 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1767 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1768 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1769 /*
1770 * AR81xx supports Tx custom checksum offload feature
1771 * that offloads single 16bit checksum computation.
1772 * So you can choose one among IP, TCP and UDP.
1773 * Normally driver sets checksum start/insertion
1774 * position from the information of TCP/UDP frame as
1775 * TCP/UDP checksum takes more time than that of IP.
1776 * However it seems that custom checksum offload
1777 * requires 4 bytes aligned Tx buffers due to hardware
1778 * bug.
1779 * AR81xx also supports explicit Tx checksum computation
1780 * if it is told that the size of IP header and TCP
1781 * header(for UDP, the header size does not matter
1782 * because it's fixed length). However with this scheme
1783 * TSO does not work so you have to choose one either
1784 * TSO or explicit Tx checksum offload. I chosen TSO
1785 * plus custom checksum offload with work-around which
1786 * will cover most common usage for this consumer
1787 * ethernet controller. The work-around takes a lot of
1788 * CPU cycles if Tx buffer is not aligned on 4 bytes
1789 * boundary, though.
1790 */
1791 cflags |= ALE_TD_CXSUM;
1792 /* Set checksum start offset. */
1793 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1794 /* Set checksum insertion position of TCP/UDP. */
1795 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1796 ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1797 }
1798
1799 /* Configure VLAN hardware tag insertion. */
1800 if ((m->m_flags & M_VLANTAG) != 0) {
1801 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1802 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1803 cflags |= ALE_TD_INSERT_VLAN_TAG;
1804 }
1805
1806 i = 0;
1807 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1808 /*
1809 * Make sure the first fragment contains
1810 * only ethernet and IP/TCP header with options.
1811 */
1812 hdrlen = poff + (tcp->th_off << 2);
1813 desc = &sc->ale_cdata.ale_tx_ring[prod];
1814 desc->addr = htole64(txsegs[i].ds_addr);
1815 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1816 desc->flags = htole32(cflags);
1817 sc->ale_cdata.ale_tx_cnt++;
1818 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1819 if (m->m_len - hdrlen > 0) {
1820 /* Handle remaining payload of the first fragment. */
1821 desc = &sc->ale_cdata.ale_tx_ring[prod];
1822 desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1823 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1824 vtag);
1825 desc->flags = htole32(cflags);
1826 sc->ale_cdata.ale_tx_cnt++;
1827 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1828 }
1829 i = 1;
1830 }
1831 for (; i < nsegs; i++) {
1832 desc = &sc->ale_cdata.ale_tx_ring[prod];
1833 desc->addr = htole64(txsegs[i].ds_addr);
1834 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1835 desc->flags = htole32(cflags);
1836 sc->ale_cdata.ale_tx_cnt++;
1837 ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1838 }
1839 /* Update producer index. */
1840 sc->ale_cdata.ale_tx_prod = prod;
1841 /* Set TSO header on the first descriptor. */
1842 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1843 desc = &sc->ale_cdata.ale_tx_ring[si];
1844 desc->flags |= htole32(ALE_TD_TSO_HDR);
1845 }
1846
1847 /* Finally set EOP on the last descriptor. */
1848 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1849 desc = &sc->ale_cdata.ale_tx_ring[prod];
1850 desc->flags |= htole32(ALE_TD_EOP);
1851
1852 /* Swap dmamap of the first and the last. */
1853 txd = &sc->ale_cdata.ale_txdesc[prod];
1854 map = txd_last->tx_dmamap;
1855 txd_last->tx_dmamap = txd->tx_dmamap;
1856 txd->tx_dmamap = map;
1857 txd->tx_m = m;
1858
1859 /* Sync descriptors. */
1860 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1861 sc->ale_cdata.ale_tx_ring_map,
1862 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1863
1864 return (0);
1865 }
1866
1867 static void
ale_start(if_t ifp)1868 ale_start(if_t ifp)
1869 {
1870 struct ale_softc *sc;
1871
1872 sc = if_getsoftc(ifp);
1873 ALE_LOCK(sc);
1874 ale_start_locked(ifp);
1875 ALE_UNLOCK(sc);
1876 }
1877
1878 static void
ale_start_locked(if_t ifp)1879 ale_start_locked(if_t ifp)
1880 {
1881 struct ale_softc *sc;
1882 struct mbuf *m_head;
1883 int enq;
1884
1885 sc = if_getsoftc(ifp);
1886
1887 ALE_LOCK_ASSERT(sc);
1888
1889 /* Reclaim transmitted frames. */
1890 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1891 ale_txeof(sc);
1892
1893 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1894 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1895 return;
1896
1897 for (enq = 0; !if_sendq_empty(ifp); ) {
1898 m_head = if_dequeue(ifp);
1899 if (m_head == NULL)
1900 break;
1901 /*
1902 * Pack the data into the transmit ring. If we
1903 * don't have room, set the OACTIVE flag and wait
1904 * for the NIC to drain the ring.
1905 */
1906 if (ale_encap(sc, &m_head)) {
1907 if (m_head == NULL)
1908 break;
1909 if_sendq_prepend(ifp, m_head);
1910 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1911 break;
1912 }
1913
1914 enq++;
1915 /*
1916 * If there's a BPF listener, bounce a copy of this frame
1917 * to him.
1918 */
1919 ETHER_BPF_MTAP(ifp, m_head);
1920 }
1921
1922 if (enq > 0) {
1923 /* Kick. */
1924 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1925 sc->ale_cdata.ale_tx_prod);
1926 /* Set a timeout in case the chip goes out to lunch. */
1927 sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1928 }
1929 }
1930
1931 static void
ale_watchdog(struct ale_softc * sc)1932 ale_watchdog(struct ale_softc *sc)
1933 {
1934 if_t ifp;
1935
1936 ALE_LOCK_ASSERT(sc);
1937
1938 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1939 return;
1940
1941 ifp = sc->ale_ifp;
1942 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1943 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1944 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1945 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1946 ale_init_locked(sc);
1947 return;
1948 }
1949 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1950 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1951 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1952 ale_init_locked(sc);
1953 if (!if_sendq_empty(ifp))
1954 ale_start_locked(ifp);
1955 }
1956
1957 static int
ale_ioctl(if_t ifp,u_long cmd,caddr_t data)1958 ale_ioctl(if_t ifp, u_long cmd, caddr_t data)
1959 {
1960 struct ale_softc *sc;
1961 struct ifreq *ifr;
1962 struct mii_data *mii;
1963 int error, mask;
1964
1965 sc = if_getsoftc(ifp);
1966 ifr = (struct ifreq *)data;
1967 error = 0;
1968 switch (cmd) {
1969 case SIOCSIFMTU:
1970 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1971 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1972 ifr->ifr_mtu > ETHERMTU))
1973 error = EINVAL;
1974 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1975 ALE_LOCK(sc);
1976 if_setmtu(ifp, ifr->ifr_mtu);
1977 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1978 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1979 ale_init_locked(sc);
1980 }
1981 ALE_UNLOCK(sc);
1982 }
1983 break;
1984 case SIOCSIFFLAGS:
1985 ALE_LOCK(sc);
1986 if ((if_getflags(ifp) & IFF_UP) != 0) {
1987 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1988 if (((if_getflags(ifp) ^ sc->ale_if_flags)
1989 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1990 ale_rxfilter(sc);
1991 } else {
1992 ale_init_locked(sc);
1993 }
1994 } else {
1995 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1996 ale_stop(sc);
1997 }
1998 sc->ale_if_flags = if_getflags(ifp);
1999 ALE_UNLOCK(sc);
2000 break;
2001 case SIOCADDMULTI:
2002 case SIOCDELMULTI:
2003 ALE_LOCK(sc);
2004 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2005 ale_rxfilter(sc);
2006 ALE_UNLOCK(sc);
2007 break;
2008 case SIOCSIFMEDIA:
2009 case SIOCGIFMEDIA:
2010 mii = device_get_softc(sc->ale_miibus);
2011 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2012 break;
2013 case SIOCSIFCAP:
2014 ALE_LOCK(sc);
2015 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
2016 if ((mask & IFCAP_TXCSUM) != 0 &&
2017 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
2018 if_togglecapenable(ifp, IFCAP_TXCSUM);
2019 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
2020 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0);
2021 else
2022 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES);
2023 }
2024 if ((mask & IFCAP_RXCSUM) != 0 &&
2025 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
2026 if_togglecapenable(ifp, IFCAP_RXCSUM);
2027 if ((mask & IFCAP_TSO4) != 0 &&
2028 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
2029 if_togglecapenable(ifp, IFCAP_TSO4);
2030 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
2031 if_sethwassistbits(ifp, CSUM_TSO, 0);
2032 else
2033 if_sethwassistbits(ifp, 0, CSUM_TSO);
2034 }
2035
2036 if ((mask & IFCAP_WOL_MCAST) != 0 &&
2037 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0)
2038 if_togglecapenable(ifp, IFCAP_WOL_MCAST);
2039 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2040 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
2041 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
2042 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2043 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0)
2044 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM);
2045 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2046 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
2047 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
2048 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2049 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
2050 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
2051 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
2052 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
2053 ale_rxvlan(sc);
2054 }
2055 ALE_UNLOCK(sc);
2056 VLAN_CAPABILITIES(ifp);
2057 break;
2058 default:
2059 error = ether_ioctl(ifp, cmd, data);
2060 break;
2061 }
2062
2063 return (error);
2064 }
2065
2066 static void
ale_mac_config(struct ale_softc * sc)2067 ale_mac_config(struct ale_softc *sc)
2068 {
2069 struct mii_data *mii;
2070 uint32_t reg;
2071
2072 ALE_LOCK_ASSERT(sc);
2073
2074 mii = device_get_softc(sc->ale_miibus);
2075 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2076 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2077 MAC_CFG_SPEED_MASK);
2078 /* Reprogram MAC with resolved speed/duplex. */
2079 switch (IFM_SUBTYPE(mii->mii_media_active)) {
2080 case IFM_10_T:
2081 case IFM_100_TX:
2082 reg |= MAC_CFG_SPEED_10_100;
2083 break;
2084 case IFM_1000_T:
2085 reg |= MAC_CFG_SPEED_1000;
2086 break;
2087 }
2088 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2089 reg |= MAC_CFG_FULL_DUPLEX;
2090 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2091 reg |= MAC_CFG_TX_FC;
2092 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2093 reg |= MAC_CFG_RX_FC;
2094 }
2095 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2096 }
2097
2098 static void
ale_stats_clear(struct ale_softc * sc)2099 ale_stats_clear(struct ale_softc *sc)
2100 {
2101 struct smb sb;
2102 uint32_t *reg;
2103 int i;
2104
2105 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2106 CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2107 i += sizeof(uint32_t);
2108 }
2109 /* Read Tx statistics. */
2110 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2111 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2112 i += sizeof(uint32_t);
2113 }
2114 }
2115
2116 static void
ale_stats_update(struct ale_softc * sc)2117 ale_stats_update(struct ale_softc *sc)
2118 {
2119 struct ale_hw_stats *stat;
2120 struct smb sb, *smb;
2121 if_t ifp;
2122 uint32_t *reg;
2123 int i;
2124
2125 ALE_LOCK_ASSERT(sc);
2126
2127 ifp = sc->ale_ifp;
2128 stat = &sc->ale_stats;
2129 smb = &sb;
2130
2131 /* Read Rx statistics. */
2132 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2133 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2134 i += sizeof(uint32_t);
2135 }
2136 /* Read Tx statistics. */
2137 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2138 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2139 i += sizeof(uint32_t);
2140 }
2141
2142 /* Rx stats. */
2143 stat->rx_frames += smb->rx_frames;
2144 stat->rx_bcast_frames += smb->rx_bcast_frames;
2145 stat->rx_mcast_frames += smb->rx_mcast_frames;
2146 stat->rx_pause_frames += smb->rx_pause_frames;
2147 stat->rx_control_frames += smb->rx_control_frames;
2148 stat->rx_crcerrs += smb->rx_crcerrs;
2149 stat->rx_lenerrs += smb->rx_lenerrs;
2150 stat->rx_bytes += smb->rx_bytes;
2151 stat->rx_runts += smb->rx_runts;
2152 stat->rx_fragments += smb->rx_fragments;
2153 stat->rx_pkts_64 += smb->rx_pkts_64;
2154 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2155 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2156 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2157 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2158 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2159 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2160 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2161 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2162 stat->rx_rrs_errs += smb->rx_rrs_errs;
2163 stat->rx_alignerrs += smb->rx_alignerrs;
2164 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2165 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2166 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2167
2168 /* Tx stats. */
2169 stat->tx_frames += smb->tx_frames;
2170 stat->tx_bcast_frames += smb->tx_bcast_frames;
2171 stat->tx_mcast_frames += smb->tx_mcast_frames;
2172 stat->tx_pause_frames += smb->tx_pause_frames;
2173 stat->tx_excess_defer += smb->tx_excess_defer;
2174 stat->tx_control_frames += smb->tx_control_frames;
2175 stat->tx_deferred += smb->tx_deferred;
2176 stat->tx_bytes += smb->tx_bytes;
2177 stat->tx_pkts_64 += smb->tx_pkts_64;
2178 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2179 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2180 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2181 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2182 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2183 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2184 stat->tx_single_colls += smb->tx_single_colls;
2185 stat->tx_multi_colls += smb->tx_multi_colls;
2186 stat->tx_late_colls += smb->tx_late_colls;
2187 stat->tx_excess_colls += smb->tx_excess_colls;
2188 stat->tx_underrun += smb->tx_underrun;
2189 stat->tx_desc_underrun += smb->tx_desc_underrun;
2190 stat->tx_lenerrs += smb->tx_lenerrs;
2191 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2192 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2193 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2194
2195 /* Update counters in ifnet. */
2196 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2197
2198 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2199 smb->tx_multi_colls * 2 + smb->tx_late_colls +
2200 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2201
2202 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls +
2203 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated);
2204
2205 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2206
2207 if_inc_counter(ifp, IFCOUNTER_IERRORS,
2208 smb->rx_crcerrs + smb->rx_lenerrs +
2209 smb->rx_runts + smb->rx_pkts_truncated +
2210 smb->rx_fifo_oflows + smb->rx_rrs_errs +
2211 smb->rx_alignerrs);
2212 }
2213
2214 static int
ale_intr(void * arg)2215 ale_intr(void *arg)
2216 {
2217 struct ale_softc *sc;
2218 uint32_t status;
2219
2220 sc = (struct ale_softc *)arg;
2221
2222 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2223 if ((status & ALE_INTRS) == 0)
2224 return (FILTER_STRAY);
2225 /* Disable interrupts. */
2226 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2227 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2228
2229 return (FILTER_HANDLED);
2230 }
2231
2232 static void
ale_int_task(void * arg,int pending)2233 ale_int_task(void *arg, int pending)
2234 {
2235 struct ale_softc *sc;
2236 if_t ifp;
2237 uint32_t status;
2238 int more;
2239
2240 sc = (struct ale_softc *)arg;
2241
2242 status = CSR_READ_4(sc, ALE_INTR_STATUS);
2243 ALE_LOCK(sc);
2244 if (sc->ale_morework != 0)
2245 status |= INTR_RX_PKT;
2246 if ((status & ALE_INTRS) == 0)
2247 goto done;
2248
2249 /* Acknowledge interrupts but still disable interrupts. */
2250 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2251
2252 ifp = sc->ale_ifp;
2253 more = 0;
2254 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
2255 more = ale_rxeof(sc, sc->ale_process_limit);
2256 if (more == EAGAIN)
2257 sc->ale_morework = 1;
2258 else if (more == EIO) {
2259 sc->ale_stats.reset_brk_seq++;
2260 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2261 ale_init_locked(sc);
2262 ALE_UNLOCK(sc);
2263 return;
2264 }
2265
2266 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2267 if ((status & INTR_DMA_RD_TO_RST) != 0)
2268 device_printf(sc->ale_dev,
2269 "DMA read error! -- resetting\n");
2270 if ((status & INTR_DMA_WR_TO_RST) != 0)
2271 device_printf(sc->ale_dev,
2272 "DMA write error! -- resetting\n");
2273 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
2274 ale_init_locked(sc);
2275 ALE_UNLOCK(sc);
2276 return;
2277 }
2278 if (!if_sendq_empty(ifp))
2279 ale_start_locked(ifp);
2280 }
2281
2282 if (more == EAGAIN ||
2283 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2284 ALE_UNLOCK(sc);
2285 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2286 return;
2287 }
2288
2289 done:
2290 ALE_UNLOCK(sc);
2291
2292 /* Re-enable interrupts. */
2293 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2294 }
2295
2296 static void
ale_txeof(struct ale_softc * sc)2297 ale_txeof(struct ale_softc *sc)
2298 {
2299 if_t ifp;
2300 struct ale_txdesc *txd;
2301 uint32_t cons, prod;
2302 int prog;
2303
2304 ALE_LOCK_ASSERT(sc);
2305
2306 ifp = sc->ale_ifp;
2307
2308 if (sc->ale_cdata.ale_tx_cnt == 0)
2309 return;
2310
2311 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2312 sc->ale_cdata.ale_tx_ring_map,
2313 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2314 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2315 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2316 sc->ale_cdata.ale_tx_cmb_map,
2317 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2318 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2319 } else
2320 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2321 cons = sc->ale_cdata.ale_tx_cons;
2322 /*
2323 * Go through our Tx list and free mbufs for those
2324 * frames which have been transmitted.
2325 */
2326 for (prog = 0; cons != prod; prog++,
2327 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2328 if (sc->ale_cdata.ale_tx_cnt <= 0)
2329 break;
2330 prog++;
2331 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2332 sc->ale_cdata.ale_tx_cnt--;
2333 txd = &sc->ale_cdata.ale_txdesc[cons];
2334 if (txd->tx_m != NULL) {
2335 /* Reclaim transmitted mbufs. */
2336 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2337 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2338 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2339 txd->tx_dmamap);
2340 m_freem(txd->tx_m);
2341 txd->tx_m = NULL;
2342 }
2343 }
2344
2345 if (prog > 0) {
2346 sc->ale_cdata.ale_tx_cons = cons;
2347 /*
2348 * Unarm watchdog timer only when there is no pending
2349 * Tx descriptors in queue.
2350 */
2351 if (sc->ale_cdata.ale_tx_cnt == 0)
2352 sc->ale_watchdog_timer = 0;
2353 }
2354 }
2355
2356 static void
ale_rx_update_page(struct ale_softc * sc,struct ale_rx_page ** page,uint32_t length,uint32_t * prod)2357 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2358 uint32_t length, uint32_t *prod)
2359 {
2360 struct ale_rx_page *rx_page;
2361
2362 rx_page = *page;
2363 /* Update consumer position. */
2364 rx_page->cons += roundup(length + sizeof(struct rx_rs),
2365 ALE_RX_PAGE_ALIGN);
2366 if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2367 /*
2368 * End of Rx page reached, let hardware reuse
2369 * this page.
2370 */
2371 rx_page->cons = 0;
2372 *rx_page->cmb_addr = 0;
2373 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2374 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2375 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2376 RXF_VALID);
2377 /* Switch to alternate Rx page. */
2378 sc->ale_cdata.ale_rx_curp ^= 1;
2379 rx_page = *page =
2380 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2381 /* Page flipped, sync CMB and Rx page. */
2382 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2383 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2384 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2385 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2386 /* Sync completed, cache updated producer index. */
2387 *prod = *rx_page->cmb_addr;
2388 }
2389 }
2390
2391 /*
2392 * It seems that AR81xx controller can compute partial checksum.
2393 * The partial checksum value can be used to accelerate checksum
2394 * computation for fragmented TCP/UDP packets. Upper network stack
2395 * already takes advantage of the partial checksum value in IP
2396 * reassembly stage. But I'm not sure the correctness of the
2397 * partial hardware checksum assistance due to lack of data sheet.
2398 * In addition, the Rx feature of controller that requires copying
2399 * for every frames effectively nullifies one of most nice offload
2400 * capability of controller.
2401 */
2402 static void
ale_rxcsum(struct ale_softc * sc,struct mbuf * m,uint32_t status)2403 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2404 {
2405 if_t ifp;
2406 struct ip *ip;
2407 char *p;
2408
2409 ifp = sc->ale_ifp;
2410 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2411 if ((status & ALE_RD_IPCSUM_NOK) == 0)
2412 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2413
2414 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2415 if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2416 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2417 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2418 m->m_pkthdr.csum_flags |=
2419 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2420 m->m_pkthdr.csum_data = 0xffff;
2421 }
2422 } else {
2423 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2424 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2425 p = mtod(m, char *);
2426 p += ETHER_HDR_LEN;
2427 if ((status & ALE_RD_802_3) != 0)
2428 p += LLC_SNAPFRAMELEN;
2429 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 &&
2430 (status & ALE_RD_VLAN) != 0)
2431 p += ETHER_VLAN_ENCAP_LEN;
2432 ip = (struct ip *)p;
2433 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2434 return;
2435 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2436 CSUM_PSEUDO_HDR;
2437 m->m_pkthdr.csum_data = 0xffff;
2438 }
2439 }
2440 /*
2441 * Don't mark bad checksum for TCP/UDP frames
2442 * as fragmented frames may always have set
2443 * bad checksummed bit of frame status.
2444 */
2445 }
2446
2447 /* Process received frames. */
2448 static int
ale_rxeof(struct ale_softc * sc,int count)2449 ale_rxeof(struct ale_softc *sc, int count)
2450 {
2451 struct ale_rx_page *rx_page;
2452 struct rx_rs *rs;
2453 if_t ifp;
2454 struct mbuf *m;
2455 uint32_t length, prod, seqno, status, vtags;
2456 int prog;
2457
2458 ifp = sc->ale_ifp;
2459 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2460 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2461 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2462 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2463 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2464 /*
2465 * Don't directly access producer index as hardware may
2466 * update it while Rx handler is in progress. It would
2467 * be even better if there is a way to let hardware
2468 * know how far driver processed its received frames.
2469 * Alternatively, hardware could provide a way to disable
2470 * CMB updates until driver acknowledges the end of CMB
2471 * access.
2472 */
2473 prod = *rx_page->cmb_addr;
2474 for (prog = 0; prog < count; prog++) {
2475 if (rx_page->cons >= prod)
2476 break;
2477 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2478 seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2479 if (sc->ale_cdata.ale_rx_seqno != seqno) {
2480 /*
2481 * Normally I believe this should not happen unless
2482 * severe driver bug or corrupted memory. However
2483 * it seems to happen under certain conditions which
2484 * is triggered by abrupt Rx events such as initiation
2485 * of bulk transfer of remote host. It's not easy to
2486 * reproduce this and I doubt it could be related
2487 * with FIFO overflow of hardware or activity of Tx
2488 * CMB updates. I also remember similar behaviour
2489 * seen on RealTek 8139 which uses resembling Rx
2490 * scheme.
2491 */
2492 if (bootverbose)
2493 device_printf(sc->ale_dev,
2494 "garbled seq: %u, expected: %u -- "
2495 "resetting!\n", seqno,
2496 sc->ale_cdata.ale_rx_seqno);
2497 return (EIO);
2498 }
2499 /* Frame received. */
2500 sc->ale_cdata.ale_rx_seqno++;
2501 length = ALE_RX_BYTES(le32toh(rs->length));
2502 status = le32toh(rs->flags);
2503 if ((status & ALE_RD_ERROR) != 0) {
2504 /*
2505 * We want to pass the following frames to upper
2506 * layer regardless of error status of Rx return
2507 * status.
2508 *
2509 * o IP/TCP/UDP checksum is bad.
2510 * o frame length and protocol specific length
2511 * does not match.
2512 */
2513 if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2514 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2515 ALE_RD_TRUNC)) != 0) {
2516 ale_rx_update_page(sc, &rx_page, length, &prod);
2517 continue;
2518 }
2519 }
2520 /*
2521 * m_devget(9) is major bottle-neck of ale(4)(It comes
2522 * from hardware limitation). For jumbo frames we could
2523 * get a slightly better performance if driver use
2524 * m_getjcl(9) with proper buffer size argument. However
2525 * that would make code more complicated and I don't
2526 * think users would expect good Rx performance numbers
2527 * on these low-end consumer ethernet controller.
2528 */
2529 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2530 ETHER_ALIGN, ifp, NULL);
2531 if (m == NULL) {
2532 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2533 ale_rx_update_page(sc, &rx_page, length, &prod);
2534 continue;
2535 }
2536 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 &&
2537 (status & ALE_RD_IPV4) != 0)
2538 ale_rxcsum(sc, m, status);
2539 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 &&
2540 (status & ALE_RD_VLAN) != 0) {
2541 vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2542 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2543 m->m_flags |= M_VLANTAG;
2544 }
2545
2546 /* Pass it to upper layer. */
2547 ALE_UNLOCK(sc);
2548 if_input(ifp, m);
2549 ALE_LOCK(sc);
2550
2551 ale_rx_update_page(sc, &rx_page, length, &prod);
2552 }
2553
2554 return (count > 0 ? 0 : EAGAIN);
2555 }
2556
2557 static void
ale_tick(void * arg)2558 ale_tick(void *arg)
2559 {
2560 struct ale_softc *sc;
2561 struct mii_data *mii;
2562
2563 sc = (struct ale_softc *)arg;
2564
2565 ALE_LOCK_ASSERT(sc);
2566
2567 mii = device_get_softc(sc->ale_miibus);
2568 mii_tick(mii);
2569 ale_stats_update(sc);
2570 /*
2571 * Reclaim Tx buffers that have been transferred. It's not
2572 * needed here but it would release allocated mbuf chains
2573 * faster and limit the maximum delay to a hz.
2574 */
2575 ale_txeof(sc);
2576 ale_watchdog(sc);
2577 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2578 }
2579
2580 static void
ale_reset(struct ale_softc * sc)2581 ale_reset(struct ale_softc *sc)
2582 {
2583 uint32_t reg;
2584 int i;
2585
2586 /* Initialize PCIe module. From Linux. */
2587 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2588
2589 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2590 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2591 DELAY(10);
2592 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2593 break;
2594 }
2595 if (i == 0)
2596 device_printf(sc->ale_dev, "master reset timeout!\n");
2597
2598 for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2599 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2600 break;
2601 DELAY(10);
2602 }
2603
2604 if (i == 0)
2605 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2606 }
2607
2608 static void
ale_init(void * xsc)2609 ale_init(void *xsc)
2610 {
2611 struct ale_softc *sc;
2612
2613 sc = (struct ale_softc *)xsc;
2614 ALE_LOCK(sc);
2615 ale_init_locked(sc);
2616 ALE_UNLOCK(sc);
2617 }
2618
2619 static void
ale_init_locked(struct ale_softc * sc)2620 ale_init_locked(struct ale_softc *sc)
2621 {
2622 if_t ifp;
2623 struct mii_data *mii;
2624 uint8_t eaddr[ETHER_ADDR_LEN];
2625 bus_addr_t paddr;
2626 uint32_t reg, rxf_hi, rxf_lo;
2627
2628 ALE_LOCK_ASSERT(sc);
2629
2630 ifp = sc->ale_ifp;
2631 mii = device_get_softc(sc->ale_miibus);
2632
2633 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
2634 return;
2635 /*
2636 * Cancel any pending I/O.
2637 */
2638 ale_stop(sc);
2639 /*
2640 * Reset the chip to a known state.
2641 */
2642 ale_reset(sc);
2643 /* Initialize Tx descriptors, DMA memory blocks. */
2644 ale_init_rx_pages(sc);
2645 ale_init_tx_ring(sc);
2646
2647 /* Reprogram the station address. */
2648 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
2649 CSR_WRITE_4(sc, ALE_PAR0,
2650 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2651 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2652 /*
2653 * Clear WOL status and disable all WOL feature as WOL
2654 * would interfere Rx operation under normal environments.
2655 */
2656 CSR_READ_4(sc, ALE_WOL_CFG);
2657 CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2658 /*
2659 * Set Tx descriptor/RXF0/CMB base addresses. They share
2660 * the same high address part of DMAable region.
2661 */
2662 paddr = sc->ale_cdata.ale_tx_ring_paddr;
2663 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2664 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2665 CSR_WRITE_4(sc, ALE_TPD_CNT,
2666 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2667 /* Set Rx page base address, note we use single queue. */
2668 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2669 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2670 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2671 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2672 /* Set Tx/Rx CMB addresses. */
2673 paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2674 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2675 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2676 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2677 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2678 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2679 /* Mark RXF0 is valid. */
2680 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2681 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2682 /*
2683 * No need to initialize RFX1/RXF2/RXF3. We don't use
2684 * multi-queue yet.
2685 */
2686
2687 /* Set Rx page size, excluding guard frame size. */
2688 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2689 /* Tell hardware that we're ready to load DMA blocks. */
2690 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2691
2692 /* Set Rx/Tx interrupt trigger threshold. */
2693 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2694 (4 << INT_TRIG_TX_THRESH_SHIFT));
2695 /*
2696 * XXX
2697 * Set interrupt trigger timer, its purpose and relation
2698 * with interrupt moderation mechanism is not clear yet.
2699 */
2700 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2701 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2702 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2703
2704 /* Configure interrupt moderation timer. */
2705 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2706 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2707 CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2708 reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2709 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2710 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2711 if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2712 reg |= MASTER_IM_RX_TIMER_ENB;
2713 if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2714 reg |= MASTER_IM_TX_TIMER_ENB;
2715 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2716 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2717
2718 /* Set Maximum frame size of controller. */
2719 if (if_getmtu(ifp) < ETHERMTU)
2720 sc->ale_max_frame_size = ETHERMTU;
2721 else
2722 sc->ale_max_frame_size = if_getmtu(ifp);
2723 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2724 ETHER_CRC_LEN;
2725 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2726 /* Configure IPG/IFG parameters. */
2727 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2728 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2729 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2730 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2731 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2732 /* Set parameters for half-duplex media. */
2733 CSR_WRITE_4(sc, ALE_HDPX_CFG,
2734 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2735 HDPX_CFG_LCOL_MASK) |
2736 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2737 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2738 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2739 HDPX_CFG_ABEBT_MASK) |
2740 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2741 HDPX_CFG_JAMIPG_MASK));
2742
2743 /* Configure Tx jumbo frame parameters. */
2744 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2745 if (if_getmtu(ifp) < ETHERMTU)
2746 reg = sc->ale_max_frame_size;
2747 else if (if_getmtu(ifp) < 6 * 1024)
2748 reg = (sc->ale_max_frame_size * 2) / 3;
2749 else
2750 reg = sc->ale_max_frame_size / 2;
2751 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2752 roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2753 TX_JUMBO_THRESH_UNIT_SHIFT);
2754 }
2755 /* Configure TxQ. */
2756 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2757 << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2758 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2759 TXQ_CFG_TPD_BURST_MASK;
2760 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2761
2762 /* Configure Rx jumbo frame & flow control parameters. */
2763 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2764 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2765 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2766 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2767 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2768 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2769 RX_JUMBO_LKAH_MASK));
2770 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2771 rxf_hi = (reg * 7) / 10;
2772 rxf_lo = (reg * 3)/ 10;
2773 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2774 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2775 RX_FIFO_PAUSE_THRESH_LO_MASK) |
2776 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2777 RX_FIFO_PAUSE_THRESH_HI_MASK));
2778 }
2779
2780 /* Disable RSS. */
2781 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2782 CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2783
2784 /* Configure RxQ. */
2785 CSR_WRITE_4(sc, ALE_RXQ_CFG,
2786 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2787
2788 /* Configure DMA parameters. */
2789 reg = 0;
2790 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2791 reg |= DMA_CFG_TXCMB_ENB;
2792 CSR_WRITE_4(sc, ALE_DMA_CFG,
2793 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2794 sc->ale_dma_rd_burst | reg |
2795 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2796 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2797 DMA_CFG_RD_DELAY_CNT_MASK) |
2798 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2799 DMA_CFG_WR_DELAY_CNT_MASK));
2800
2801 /*
2802 * Hardware can be configured to issue SMB interrupt based
2803 * on programmed interval. Since there is a callout that is
2804 * invoked for every hz in driver we use that instead of
2805 * relying on periodic SMB interrupt.
2806 */
2807 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2808 /* Clear MAC statistics. */
2809 ale_stats_clear(sc);
2810
2811 /*
2812 * Configure Tx/Rx MACs.
2813 * - Auto-padding for short frames.
2814 * - Enable CRC generation.
2815 * Actual reconfiguration of MAC for resolved speed/duplex
2816 * is followed after detection of link establishment.
2817 * AR81xx always does checksum computation regardless of
2818 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2819 * cause Rx handling issue for fragmented IP datagrams due
2820 * to silicon bug.
2821 */
2822 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2823 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2824 MAC_CFG_PREAMBLE_MASK);
2825 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2826 reg |= MAC_CFG_SPEED_10_100;
2827 else
2828 reg |= MAC_CFG_SPEED_1000;
2829 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2830
2831 /* Set up the receive filter. */
2832 ale_rxfilter(sc);
2833 ale_rxvlan(sc);
2834
2835 /* Acknowledge all pending interrupts and clear it. */
2836 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2837 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2838 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2839
2840 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2841 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2842
2843 sc->ale_flags &= ~ALE_FLAG_LINK;
2844 /* Switch to the current media. */
2845 mii_mediachg(mii);
2846
2847 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2848 }
2849
2850 static void
ale_stop(struct ale_softc * sc)2851 ale_stop(struct ale_softc *sc)
2852 {
2853 if_t ifp;
2854 struct ale_txdesc *txd;
2855 uint32_t reg;
2856 int i;
2857
2858 ALE_LOCK_ASSERT(sc);
2859 /*
2860 * Mark the interface down and cancel the watchdog timer.
2861 */
2862 ifp = sc->ale_ifp;
2863 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2864 sc->ale_flags &= ~ALE_FLAG_LINK;
2865 callout_stop(&sc->ale_tick_ch);
2866 sc->ale_watchdog_timer = 0;
2867 ale_stats_update(sc);
2868 /* Disable interrupts. */
2869 CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2870 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2871 /* Disable queue processing and DMA. */
2872 reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2873 reg &= ~TXQ_CFG_ENB;
2874 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2875 reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2876 reg &= ~RXQ_CFG_ENB;
2877 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2878 reg = CSR_READ_4(sc, ALE_DMA_CFG);
2879 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2880 CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2881 DELAY(1000);
2882 /* Stop Rx/Tx MACs. */
2883 ale_stop_mac(sc);
2884 /* Disable interrupts which might be touched in taskq handler. */
2885 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2886
2887 /*
2888 * Free TX mbufs still in the queues.
2889 */
2890 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2891 txd = &sc->ale_cdata.ale_txdesc[i];
2892 if (txd->tx_m != NULL) {
2893 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2894 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2895 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2896 txd->tx_dmamap);
2897 m_freem(txd->tx_m);
2898 txd->tx_m = NULL;
2899 }
2900 }
2901 }
2902
2903 static void
ale_stop_mac(struct ale_softc * sc)2904 ale_stop_mac(struct ale_softc *sc)
2905 {
2906 uint32_t reg;
2907 int i;
2908
2909 ALE_LOCK_ASSERT(sc);
2910
2911 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2912 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2913 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2914 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2915 }
2916
2917 for (i = ALE_TIMEOUT; i > 0; i--) {
2918 reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2919 if (reg == 0)
2920 break;
2921 DELAY(10);
2922 }
2923 if (i == 0)
2924 device_printf(sc->ale_dev,
2925 "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2926 }
2927
2928 static void
ale_init_tx_ring(struct ale_softc * sc)2929 ale_init_tx_ring(struct ale_softc *sc)
2930 {
2931 struct ale_txdesc *txd;
2932 int i;
2933
2934 ALE_LOCK_ASSERT(sc);
2935
2936 sc->ale_cdata.ale_tx_prod = 0;
2937 sc->ale_cdata.ale_tx_cons = 0;
2938 sc->ale_cdata.ale_tx_cnt = 0;
2939
2940 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2941 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2942 for (i = 0; i < ALE_TX_RING_CNT; i++) {
2943 txd = &sc->ale_cdata.ale_txdesc[i];
2944 txd->tx_m = NULL;
2945 }
2946 *sc->ale_cdata.ale_tx_cmb = 0;
2947 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2948 sc->ale_cdata.ale_tx_cmb_map,
2949 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2950 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2951 sc->ale_cdata.ale_tx_ring_map,
2952 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2953 }
2954
2955 static void
ale_init_rx_pages(struct ale_softc * sc)2956 ale_init_rx_pages(struct ale_softc *sc)
2957 {
2958 struct ale_rx_page *rx_page;
2959 int i;
2960
2961 ALE_LOCK_ASSERT(sc);
2962
2963 sc->ale_morework = 0;
2964 sc->ale_cdata.ale_rx_seqno = 0;
2965 sc->ale_cdata.ale_rx_curp = 0;
2966
2967 for (i = 0; i < ALE_RX_PAGES; i++) {
2968 rx_page = &sc->ale_cdata.ale_rx_page[i];
2969 bzero(rx_page->page_addr, sc->ale_pagesize);
2970 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2971 rx_page->cons = 0;
2972 *rx_page->cmb_addr = 0;
2973 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2974 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2975 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2977 }
2978 }
2979
2980 static void
ale_rxvlan(struct ale_softc * sc)2981 ale_rxvlan(struct ale_softc *sc)
2982 {
2983 if_t ifp;
2984 uint32_t reg;
2985
2986 ALE_LOCK_ASSERT(sc);
2987
2988 ifp = sc->ale_ifp;
2989 reg = CSR_READ_4(sc, ALE_MAC_CFG);
2990 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2991 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
2992 reg |= MAC_CFG_VLAN_TAG_STRIP;
2993 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2994 }
2995
2996 static u_int
ale_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2997 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2998 {
2999 uint32_t crc, *mchash = arg;
3000
3001 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
3002 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3003
3004 return (1);
3005 }
3006
3007 static void
ale_rxfilter(struct ale_softc * sc)3008 ale_rxfilter(struct ale_softc *sc)
3009 {
3010 if_t ifp;
3011 uint32_t mchash[2];
3012 uint32_t rxcfg;
3013
3014 ALE_LOCK_ASSERT(sc);
3015
3016 ifp = sc->ale_ifp;
3017
3018 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3019 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3020 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
3021 rxcfg |= MAC_CFG_BCAST;
3022 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3023 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
3024 rxcfg |= MAC_CFG_PROMISC;
3025 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
3026 rxcfg |= MAC_CFG_ALLMULTI;
3027 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3028 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3029 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3030 return;
3031 }
3032
3033 /* Program new filter. */
3034 bzero(mchash, sizeof(mchash));
3035 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash);
3036
3037 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3038 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3039 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3040 }
3041
3042 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)3043 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3044 {
3045 int error, value;
3046
3047 if (arg1 == NULL)
3048 return (EINVAL);
3049 value = *(int *)arg1;
3050 error = sysctl_handle_int(oidp, &value, 0, req);
3051 if (error || req->newptr == NULL)
3052 return (error);
3053 if (value < low || value > high)
3054 return (EINVAL);
3055 *(int *)arg1 = value;
3056
3057 return (0);
3058 }
3059
3060 static int
sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)3061 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3062 {
3063 return (sysctl_int_range(oidp, arg1, arg2, req,
3064 ALE_PROC_MIN, ALE_PROC_MAX));
3065 }
3066
3067 static int
sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)3068 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3069 {
3070
3071 return (sysctl_int_range(oidp, arg1, arg2, req,
3072 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
3073 }
3074