1 /* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: Alex Deucher <alexander.deucher@amd.com> 24 * 25 */ 26 27 #ifndef __EVERGREEN_STATE_H__ 28 #define __EVERGREEN_STATE_H__ 29 30 typedef int bool_t; 31 32 #define CLEAR(x) memset (&x, 0, sizeof(x)) 33 34 /* Sequencer / thread handling */ 35 typedef struct { 36 int ps_prio; 37 int vs_prio; 38 int gs_prio; 39 int es_prio; 40 int hs_prio; 41 int ls_prio; 42 int cs_prio; 43 int num_ps_gprs; 44 int num_vs_gprs; 45 int num_gs_gprs; 46 int num_es_gprs; 47 int num_hs_gprs; 48 int num_ls_gprs; 49 int num_cs_gprs; 50 int num_temp_gprs; 51 int num_ps_threads; 52 int num_vs_threads; 53 int num_gs_threads; 54 int num_es_threads; 55 int num_hs_threads; 56 int num_ls_threads; 57 int num_ps_stack_entries; 58 int num_vs_stack_entries; 59 int num_gs_stack_entries; 60 int num_es_stack_entries; 61 int num_hs_stack_entries; 62 int num_ls_stack_entries; 63 } sq_config_t; 64 65 /* Color buffer / render target */ 66 typedef struct { 67 int id; 68 int w; 69 int h; 70 uint64_t base; 71 int format; 72 int endian; 73 int array_mode; // tiling 74 int non_disp_tiling; 75 int number_type; 76 int read_size; 77 int comp_swap; 78 int tile_mode; 79 int blend_clamp; 80 int clear_color; 81 int blend_bypass; 82 int simple_float; 83 int round_mode; 84 int tile_compact; 85 int source_format; 86 int resource_type; 87 int fast_clear; 88 int compression; 89 int rat; 90 /* 2D related CB state */ 91 uint32_t pmask; 92 int rop; 93 int blend_enable; 94 uint32_t blendcntl; 95 struct radeon_bo *bo; 96 struct radeon_surface *surface; 97 } cb_config_t; 98 99 /* Shader */ 100 typedef struct { 101 uint64_t shader_addr; 102 uint32_t shader_size; 103 int num_gprs; 104 int stack_size; 105 int dx10_clamp; 106 int clamp_consts; 107 int export_mode; 108 int uncached_first_inst; 109 int single_round; 110 int double_round; 111 int allow_sdi; 112 int allow_sd0; 113 int allow_ddi; 114 int allow_ddo; 115 struct radeon_bo *bo; 116 } shader_config_t; 117 118 /* Shader consts */ 119 typedef struct { 120 int type; 121 int size_bytes; 122 uint64_t const_addr; 123 struct radeon_bo *bo; 124 uint32_t *cpu_ptr; 125 } const_config_t; 126 127 /* Vertex buffer / vtx resource */ 128 typedef struct { 129 int id; 130 uint64_t vb_addr; 131 uint32_t vtx_num_entries; 132 uint32_t vtx_size_dw; 133 int clamp_x; 134 int format; 135 int num_format_all; 136 int format_comp_all; 137 int srf_mode_all; 138 int endian; 139 int mem_req_size; 140 int dst_sel_x; 141 int dst_sel_y; 142 int dst_sel_z; 143 int dst_sel_w; 144 int uncached; 145 struct radeon_bo *bo; 146 } vtx_resource_t; 147 148 /* Texture resource */ 149 typedef struct { 150 int id; 151 int w; 152 int h; 153 int pitch; 154 int depth; 155 int dim; 156 int array_mode; 157 int tile_type; 158 int format; 159 uint64_t base; 160 uint64_t mip_base; 161 uint32_t size; 162 int format_comp_x; 163 int format_comp_y; 164 int format_comp_z; 165 int format_comp_w; 166 int num_format_all; 167 int srf_mode_all; 168 int force_degamma; 169 int endian; 170 int dst_sel_x; 171 int dst_sel_y; 172 int dst_sel_z; 173 int dst_sel_w; 174 int base_level; 175 int last_level; 176 int base_array; 177 int last_array; 178 int perf_modulation; 179 int interlaced; 180 int min_lod; 181 struct radeon_bo *bo; 182 struct radeon_bo *mip_bo; 183 struct radeon_surface *surface; 184 } tex_resource_t; 185 186 /* Texture sampler */ 187 typedef struct { 188 int id; 189 /* Clamping */ 190 int clamp_x, clamp_y, clamp_z; 191 int border_color; 192 /* Filtering */ 193 int xy_mag_filter, xy_min_filter; 194 int z_filter; 195 int mip_filter; 196 bool_t high_precision_filter; /* ? */ 197 int perf_mip; /* ? 0-7 */ 198 int perf_z; /* ? 3 */ 199 /* LoD selection */ 200 int min_lod, max_lod; /* 0-0x3ff */ 201 int lod_bias; /* 0-0xfff (signed?) */ 202 int lod_bias2; /* ? 0-0xfff (signed?) */ 203 bool_t lod_uses_minor_axis; /* ? */ 204 /* Other stuff */ 205 bool_t point_sampling_clamp; /* ? */ 206 bool_t tex_array_override; /* ? */ 207 bool_t mc_coord_truncate; /* ? */ 208 bool_t force_degamma; /* ? */ 209 bool_t fetch_4; /* ? */ 210 bool_t sample_is_pcf; /* ? */ 211 bool_t type; /* ? */ 212 int depth_compare; /* only depth textures? */ 213 int chroma_key; 214 int truncate_coord; 215 bool_t disable_cube_wrap; 216 } tex_sampler_t; 217 218 /* Draw command */ 219 typedef struct { 220 uint32_t prim_type; 221 uint32_t vgt_draw_initiator; 222 uint32_t index_type; 223 uint32_t num_instances; 224 uint32_t num_indices; 225 } draw_config_t; 226 227 #define BEGIN_BATCH(n) \ 228 do { \ 229 radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__); \ 230 } while(0) 231 #define END_BATCH() \ 232 do { \ 233 radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); \ 234 } while(0) 235 #define RELOC_BATCH(bo, rd, wd) \ 236 do { \ 237 int _ret; \ 238 _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0); \ 239 if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \ 240 } while(0) 241 #define E32(dword) \ 242 do { \ 243 radeon_cs_write_dword(info->cs, (dword)); \ 244 } while (0) 245 246 #define EFLOAT(val) \ 247 do { \ 248 union { float f; uint32_t d; } a; \ 249 a.f = (val); \ 250 E32(a.d); \ 251 } while (0) 252 253 #define PACK3(cmd, num) \ 254 do { \ 255 E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \ 256 } while (0) 257 258 /* write num registers, start at reg */ 259 /* If register falls in a special area, special commands are issued */ 260 #define PACK0(reg, num) \ 261 do { \ 262 if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) { \ 263 PACK3(IT_SET_CONFIG_REG, (num) + 1); \ 264 E32(((reg) - SET_CONFIG_REG_offset) >> 2); \ 265 } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \ 266 PACK3(IT_SET_CONTEXT_REG, (num) + 1); \ 267 E32(((reg) - SET_CONTEXT_REG_offset) >> 2); \ 268 } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \ 269 PACK3(IT_SET_RESOURCE, num + 1); \ 270 E32(((reg) - SET_RESOURCE_offset) >> 2); \ 271 } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \ 272 PACK3(IT_SET_SAMPLER, (num) + 1); \ 273 E32((reg - SET_SAMPLER_offset) >> 2); \ 274 } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \ 275 PACK3(IT_SET_CTL_CONST, (num) + 1); \ 276 E32(((reg) - SET_CTL_CONST_offset) >> 2); \ 277 } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \ 278 PACK3(IT_SET_LOOP_CONST, (num) + 1); \ 279 E32(((reg) - SET_LOOP_CONST_offset) >> 2); \ 280 } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \ 281 PACK3(IT_SET_BOOL_CONST, (num) + 1); \ 282 E32(((reg) - SET_BOOL_CONST_offset) >> 2); \ 283 } else { \ 284 E32(CP_PACKET0 ((reg), (num) - 1)); \ 285 } \ 286 } while (0) 287 288 /* write a single register */ 289 #define EREG(reg, val) \ 290 do { \ 291 PACK0((reg), 1); \ 292 E32((val)); \ 293 } while (0) 294 295 void 296 evergreen_start_3d(ScrnInfoPtr pScrn); 297 void 298 evergreen_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain); 299 void 300 evergreen_set_blend_color(ScrnInfoPtr pScrn, float *color); 301 void 302 evergreen_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop); 303 void 304 evergreen_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp); 305 void 306 evergreen_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain); 307 void 308 evergreen_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain); 309 void 310 evergreen_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain); 311 void 312 evergreen_set_alu_consts(ScrnInfoPtr pScrn, const_config_t *const_conf, uint32_t domain); 313 void 314 evergreen_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val); 315 void 316 evergreen_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain); 317 void 318 evergreen_set_tex_sampler(ScrnInfoPtr pScrn, tex_sampler_t *s); 319 void 320 evergreen_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); 321 void 322 evergreen_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); 323 void 324 evergreen_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); 325 void 326 evergreen_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2); 327 void 328 evergreen_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2); 329 void 330 evergreen_set_default_state(ScrnInfoPtr pScrn); 331 void 332 cayman_set_default_state(ScrnInfoPtr pScrn); 333 void 334 evergreen_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf); 335 336 void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size); 337 338 extern Bool 339 R600SetAccelState(ScrnInfoPtr pScrn, 340 struct r600_accel_object *src0, 341 struct r600_accel_object *src1, 342 struct r600_accel_object *dst, 343 uint32_t vs_offset, uint32_t ps_offset, 344 int rop, Pixel planemask); 345 346 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index); 347 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index); 348 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height, 349 int depth, int usage_hint, int bitsPerPixel, 350 int *new_pitch); 351 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv); 352 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix); 353 extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p); 354 extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle); 355 356 #endif 357