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/dports/cad/yosys/yosys-yosys-0.12/tests/simple/
H A Dimplicit_ports.v7 module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); port
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-ams/ashenden/compliant/aliases/
H A Dcontroller_system.vhd52 alu_result : std_logic_vector(0 to alu_data_width - 1); signal
/dports/cad/ghdl/ghdl-1.0.0/testsuite/vests/vhdl-93/ashenden/compliant/
H A Dch_09_fg_09_01.vhd59 alu_result : std_logic_vector(0 to alu_data_width - 1); signal
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue30/
H A Dtb-alu.vhdl135 signal alu_result: std_logic_vector(7 downto 0); signal