1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27
28 #include <linux/file.h>
29 #include <linux/pagemap.h>
30 #include <linux/sync_file.h>
31 #include <linux/dma-buf.h>
32
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_syncobj.h>
35 #include <drm/ttm/ttm_tt.h>
36
37 #include "amdgpu_cs.h"
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 #include "amdgpu_gmc.h"
41 #include "amdgpu_gem.h"
42 #include "amdgpu_ras.h"
43
amdgpu_cs_parser_init(struct amdgpu_cs_parser * p,struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_cs * cs)44 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p,
45 struct amdgpu_device *adev,
46 struct drm_file *filp,
47 union drm_amdgpu_cs *cs)
48 {
49 struct amdgpu_fpriv *fpriv = filp->driver_priv;
50
51 if (cs->in.num_chunks == 0)
52 return -EINVAL;
53
54 memset(p, 0, sizeof(*p));
55 p->adev = adev;
56 p->filp = filp;
57
58 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
59 if (!p->ctx)
60 return -EINVAL;
61
62 if (atomic_read(&p->ctx->guilty)) {
63 amdgpu_ctx_put(p->ctx);
64 return -ECANCELED;
65 }
66
67 amdgpu_sync_create(&p->sync);
68 drm_exec_init(&p->exec, DRM_EXEC_INTERRUPTIBLE_WAIT |
69 DRM_EXEC_IGNORE_DUPLICATES);
70 return 0;
71 }
72
amdgpu_cs_job_idx(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_ib * chunk_ib)73 static int amdgpu_cs_job_idx(struct amdgpu_cs_parser *p,
74 struct drm_amdgpu_cs_chunk_ib *chunk_ib)
75 {
76 struct drm_sched_entity *entity;
77 unsigned int i;
78 int r;
79
80 r = amdgpu_ctx_get_entity(p->ctx, chunk_ib->ip_type,
81 chunk_ib->ip_instance,
82 chunk_ib->ring, &entity);
83 if (r)
84 return r;
85
86 /*
87 * Abort if there is no run queue associated with this entity.
88 * Possibly because of disabled HW IP.
89 */
90 if (entity->rq == NULL)
91 return -EINVAL;
92
93 /* Check if we can add this IB to some existing job */
94 for (i = 0; i < p->gang_size; ++i)
95 if (p->entities[i] == entity)
96 return i;
97
98 /* If not increase the gang size if possible */
99 if (i == AMDGPU_CS_GANG_SIZE)
100 return -EINVAL;
101
102 p->entities[i] = entity;
103 p->gang_size = i + 1;
104 return i;
105 }
106
amdgpu_cs_p1_ib(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_ib * chunk_ib,unsigned int * num_ibs)107 static int amdgpu_cs_p1_ib(struct amdgpu_cs_parser *p,
108 struct drm_amdgpu_cs_chunk_ib *chunk_ib,
109 unsigned int *num_ibs)
110 {
111 int r;
112
113 r = amdgpu_cs_job_idx(p, chunk_ib);
114 if (r < 0)
115 return r;
116
117 if (num_ibs[r] >= amdgpu_ring_max_ibs(chunk_ib->ip_type))
118 return -EINVAL;
119
120 ++(num_ibs[r]);
121 p->gang_leader_idx = r;
122 return 0;
123 }
124
amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser * p,struct drm_amdgpu_cs_chunk_fence * data,uint32_t * offset)125 static int amdgpu_cs_p1_user_fence(struct amdgpu_cs_parser *p,
126 struct drm_amdgpu_cs_chunk_fence *data,
127 uint32_t *offset)
128 {
129 struct drm_gem_object *gobj;
130 unsigned long size;
131
132 gobj = drm_gem_object_lookup(p->filp, data->handle);
133 if (gobj == NULL)
134 return -EINVAL;
135
136 p->uf_bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
137 drm_gem_object_put(gobj);
138
139 size = amdgpu_bo_size(p->uf_bo);
140 if (size != PAGE_SIZE || data->offset > (size - 8))
141 return -EINVAL;
142
143 if (amdgpu_ttm_tt_get_usermm(p->uf_bo->tbo.ttm))
144 return -EINVAL;
145
146 *offset = data->offset;
147 return 0;
148 }
149
amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser * p,struct drm_amdgpu_bo_list_in * data)150 static int amdgpu_cs_p1_bo_handles(struct amdgpu_cs_parser *p,
151 struct drm_amdgpu_bo_list_in *data)
152 {
153 struct drm_amdgpu_bo_list_entry *info;
154 int r;
155
156 r = amdgpu_bo_create_list_entry_array(data, &info);
157 if (r)
158 return r;
159
160 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
161 &p->bo_list);
162 if (r)
163 goto error_free;
164
165 kvfree(info);
166 return 0;
167
168 error_free:
169 kvfree(info);
170
171 return r;
172 }
173
174 /* Copy the data from userspace and go over it the first time */
amdgpu_cs_pass1(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)175 static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
176 union drm_amdgpu_cs *cs)
177 {
178 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
179 unsigned int num_ibs[AMDGPU_CS_GANG_SIZE] = { };
180 struct amdgpu_vm *vm = &fpriv->vm;
181 uint64_t *chunk_array_user;
182 uint64_t *chunk_array;
183 uint32_t uf_offset = 0;
184 size_t size;
185 int ret;
186 int i;
187
188 chunk_array = kvmalloc_array(cs->in.num_chunks, sizeof(uint64_t),
189 GFP_KERNEL);
190 if (!chunk_array)
191 return -ENOMEM;
192
193 /* get chunks */
194 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
195 if (copy_from_user(chunk_array, chunk_array_user,
196 sizeof(uint64_t)*cs->in.num_chunks)) {
197 ret = -EFAULT;
198 goto free_chunk;
199 }
200
201 p->nchunks = cs->in.num_chunks;
202 p->chunks = kvmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
203 GFP_KERNEL);
204 if (!p->chunks) {
205 ret = -ENOMEM;
206 goto free_chunk;
207 }
208
209 for (i = 0; i < p->nchunks; i++) {
210 struct drm_amdgpu_cs_chunk __user *chunk_ptr = NULL;
211 struct drm_amdgpu_cs_chunk user_chunk;
212 uint32_t __user *cdata;
213
214 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
215 if (copy_from_user(&user_chunk, chunk_ptr,
216 sizeof(struct drm_amdgpu_cs_chunk))) {
217 ret = -EFAULT;
218 i--;
219 goto free_partial_kdata;
220 }
221 p->chunks[i].chunk_id = user_chunk.chunk_id;
222 p->chunks[i].length_dw = user_chunk.length_dw;
223
224 size = p->chunks[i].length_dw;
225 cdata = u64_to_user_ptr(user_chunk.chunk_data);
226
227 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t),
228 GFP_KERNEL);
229 if (p->chunks[i].kdata == NULL) {
230 ret = -ENOMEM;
231 i--;
232 goto free_partial_kdata;
233 }
234 size *= sizeof(uint32_t);
235 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
236 ret = -EFAULT;
237 goto free_partial_kdata;
238 }
239
240 /* Assume the worst on the following checks */
241 ret = -EINVAL;
242 switch (p->chunks[i].chunk_id) {
243 case AMDGPU_CHUNK_ID_IB:
244 if (size < sizeof(struct drm_amdgpu_cs_chunk_ib))
245 goto free_partial_kdata;
246
247 ret = amdgpu_cs_p1_ib(p, p->chunks[i].kdata, num_ibs);
248 if (ret)
249 goto free_partial_kdata;
250 break;
251
252 case AMDGPU_CHUNK_ID_FENCE:
253 if (size < sizeof(struct drm_amdgpu_cs_chunk_fence))
254 goto free_partial_kdata;
255
256 ret = amdgpu_cs_p1_user_fence(p, p->chunks[i].kdata,
257 &uf_offset);
258 if (ret)
259 goto free_partial_kdata;
260 break;
261
262 case AMDGPU_CHUNK_ID_BO_HANDLES:
263 if (size < sizeof(struct drm_amdgpu_bo_list_in))
264 goto free_partial_kdata;
265
266 /* Only a single BO list is allowed to simplify handling. */
267 if (p->bo_list)
268 goto free_partial_kdata;
269
270 ret = amdgpu_cs_p1_bo_handles(p, p->chunks[i].kdata);
271 if (ret)
272 goto free_partial_kdata;
273 break;
274
275 case AMDGPU_CHUNK_ID_DEPENDENCIES:
276 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
277 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
278 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
279 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
280 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
281 case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
282 break;
283
284 default:
285 goto free_partial_kdata;
286 }
287 }
288
289 if (!p->gang_size) {
290 ret = -EINVAL;
291 goto free_all_kdata;
292 }
293
294 for (i = 0; i < p->gang_size; ++i) {
295 ret = amdgpu_job_alloc(p->adev, vm, p->entities[i], vm,
296 num_ibs[i], &p->jobs[i]);
297 if (ret)
298 goto free_all_kdata;
299 }
300 p->gang_leader = p->jobs[p->gang_leader_idx];
301
302 if (p->ctx->generation != p->gang_leader->generation) {
303 ret = -ECANCELED;
304 goto free_all_kdata;
305 }
306
307 if (p->uf_bo)
308 p->gang_leader->uf_addr = uf_offset;
309 kvfree(chunk_array);
310
311 /* Use this opportunity to fill in task info for the vm */
312 amdgpu_vm_set_task_info(vm);
313
314 return 0;
315
316 free_all_kdata:
317 i = p->nchunks - 1;
318 free_partial_kdata:
319 for (; i >= 0; i--)
320 kvfree(p->chunks[i].kdata);
321 kvfree(p->chunks);
322 p->chunks = NULL;
323 p->nchunks = 0;
324 free_chunk:
325 kvfree(chunk_array);
326
327 return ret;
328 }
329
amdgpu_cs_p2_ib(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk,unsigned int * ce_preempt,unsigned int * de_preempt)330 static int amdgpu_cs_p2_ib(struct amdgpu_cs_parser *p,
331 struct amdgpu_cs_chunk *chunk,
332 unsigned int *ce_preempt,
333 unsigned int *de_preempt)
334 {
335 struct drm_amdgpu_cs_chunk_ib *chunk_ib = chunk->kdata;
336 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
337 struct amdgpu_vm *vm = &fpriv->vm;
338 struct amdgpu_ring *ring;
339 struct amdgpu_job *job;
340 struct amdgpu_ib *ib;
341 int r;
342
343 r = amdgpu_cs_job_idx(p, chunk_ib);
344 if (r < 0)
345 return r;
346
347 job = p->jobs[r];
348 ring = amdgpu_job_ring(job);
349 ib = &job->ibs[job->num_ibs++];
350
351 /* MM engine doesn't support user fences */
352 if (p->uf_bo && ring->funcs->no_user_fence)
353 return -EINVAL;
354
355 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX &&
356 chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
357 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
358 (*ce_preempt)++;
359 else
360 (*de_preempt)++;
361
362 /* Each GFX command submit allows only 1 IB max
363 * preemptible for CE & DE */
364 if (*ce_preempt > 1 || *de_preempt > 1)
365 return -EINVAL;
366 }
367
368 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
369 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
370
371 r = amdgpu_ib_get(p->adev, vm, ring->funcs->parse_cs ?
372 chunk_ib->ib_bytes : 0,
373 AMDGPU_IB_POOL_DELAYED, ib);
374 if (r) {
375 DRM_ERROR("Failed to get ib !\n");
376 return r;
377 }
378
379 ib->gpu_addr = chunk_ib->va_start;
380 ib->length_dw = chunk_ib->ib_bytes / 4;
381 ib->flags = chunk_ib->flags;
382 return 0;
383 }
384
amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)385 static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p,
386 struct amdgpu_cs_chunk *chunk)
387 {
388 struct drm_amdgpu_cs_chunk_dep *deps = chunk->kdata;
389 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
390 unsigned int num_deps;
391 int i, r;
392
393 num_deps = chunk->length_dw * 4 /
394 sizeof(struct drm_amdgpu_cs_chunk_dep);
395
396 for (i = 0; i < num_deps; ++i) {
397 struct amdgpu_ctx *ctx;
398 struct drm_sched_entity *entity;
399 struct dma_fence *fence;
400
401 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
402 if (ctx == NULL)
403 return -EINVAL;
404
405 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
406 deps[i].ip_instance,
407 deps[i].ring, &entity);
408 if (r) {
409 amdgpu_ctx_put(ctx);
410 return r;
411 }
412
413 fence = amdgpu_ctx_get_fence(ctx, entity, deps[i].handle);
414 amdgpu_ctx_put(ctx);
415
416 if (IS_ERR(fence))
417 return PTR_ERR(fence);
418 else if (!fence)
419 continue;
420
421 if (chunk->chunk_id == AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) {
422 struct drm_sched_fence *s_fence;
423 struct dma_fence *old = fence;
424
425 s_fence = to_drm_sched_fence(fence);
426 fence = dma_fence_get(&s_fence->scheduled);
427 dma_fence_put(old);
428 }
429
430 r = amdgpu_sync_fence(&p->sync, fence);
431 dma_fence_put(fence);
432 if (r)
433 return r;
434 }
435 return 0;
436 }
437
amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser * p,uint32_t handle,u64 point,u64 flags)438 static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p,
439 uint32_t handle, u64 point,
440 u64 flags)
441 {
442 struct dma_fence *fence;
443 int r;
444
445 r = drm_syncobj_find_fence(p->filp, handle, point, flags, &fence);
446 if (r) {
447 DRM_ERROR("syncobj %u failed to find fence @ %llu (%d)!\n",
448 handle, point, r);
449 return r;
450 }
451
452 r = amdgpu_sync_fence(&p->sync, fence);
453 dma_fence_put(fence);
454 return r;
455 }
456
amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)457 static int amdgpu_cs_p2_syncobj_in(struct amdgpu_cs_parser *p,
458 struct amdgpu_cs_chunk *chunk)
459 {
460 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
461 unsigned int num_deps;
462 int i, r;
463
464 num_deps = chunk->length_dw * 4 /
465 sizeof(struct drm_amdgpu_cs_chunk_sem);
466 for (i = 0; i < num_deps; ++i) {
467 r = amdgpu_syncobj_lookup_and_add(p, deps[i].handle, 0, 0);
468 if (r)
469 return r;
470 }
471
472 return 0;
473 }
474
amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)475 static int amdgpu_cs_p2_syncobj_timeline_wait(struct amdgpu_cs_parser *p,
476 struct amdgpu_cs_chunk *chunk)
477 {
478 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
479 unsigned int num_deps;
480 int i, r;
481
482 num_deps = chunk->length_dw * 4 /
483 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
484 for (i = 0; i < num_deps; ++i) {
485 r = amdgpu_syncobj_lookup_and_add(p, syncobj_deps[i].handle,
486 syncobj_deps[i].point,
487 syncobj_deps[i].flags);
488 if (r)
489 return r;
490 }
491
492 return 0;
493 }
494
amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)495 static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p,
496 struct amdgpu_cs_chunk *chunk)
497 {
498 struct drm_amdgpu_cs_chunk_sem *deps = chunk->kdata;
499 unsigned int num_deps;
500 int i;
501
502 num_deps = chunk->length_dw * 4 /
503 sizeof(struct drm_amdgpu_cs_chunk_sem);
504
505 if (p->post_deps)
506 return -EINVAL;
507
508 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
509 GFP_KERNEL);
510 p->num_post_deps = 0;
511
512 if (!p->post_deps)
513 return -ENOMEM;
514
515
516 for (i = 0; i < num_deps; ++i) {
517 p->post_deps[i].syncobj =
518 drm_syncobj_find(p->filp, deps[i].handle);
519 if (!p->post_deps[i].syncobj)
520 return -EINVAL;
521 p->post_deps[i].chain = NULL;
522 p->post_deps[i].point = 0;
523 p->num_post_deps++;
524 }
525
526 return 0;
527 }
528
amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)529 static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p,
530 struct amdgpu_cs_chunk *chunk)
531 {
532 struct drm_amdgpu_cs_chunk_syncobj *syncobj_deps = chunk->kdata;
533 unsigned int num_deps;
534 int i;
535
536 num_deps = chunk->length_dw * 4 /
537 sizeof(struct drm_amdgpu_cs_chunk_syncobj);
538
539 if (p->post_deps)
540 return -EINVAL;
541
542 p->post_deps = kmalloc_array(num_deps, sizeof(*p->post_deps),
543 GFP_KERNEL);
544 p->num_post_deps = 0;
545
546 if (!p->post_deps)
547 return -ENOMEM;
548
549 for (i = 0; i < num_deps; ++i) {
550 struct amdgpu_cs_post_dep *dep = &p->post_deps[i];
551
552 dep->chain = NULL;
553 if (syncobj_deps[i].point) {
554 dep->chain = dma_fence_chain_alloc();
555 if (!dep->chain)
556 return -ENOMEM;
557 }
558
559 dep->syncobj = drm_syncobj_find(p->filp,
560 syncobj_deps[i].handle);
561 if (!dep->syncobj) {
562 dma_fence_chain_free(dep->chain);
563 return -EINVAL;
564 }
565 dep->point = syncobj_deps[i].point;
566 p->num_post_deps++;
567 }
568
569 return 0;
570 }
571
amdgpu_cs_p2_shadow(struct amdgpu_cs_parser * p,struct amdgpu_cs_chunk * chunk)572 static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p,
573 struct amdgpu_cs_chunk *chunk)
574 {
575 struct drm_amdgpu_cs_chunk_cp_gfx_shadow *shadow = chunk->kdata;
576 int i;
577
578 if (shadow->flags & ~AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW)
579 return -EINVAL;
580
581 for (i = 0; i < p->gang_size; ++i) {
582 p->jobs[i]->shadow_va = shadow->shadow_va;
583 p->jobs[i]->csa_va = shadow->csa_va;
584 p->jobs[i]->gds_va = shadow->gds_va;
585 p->jobs[i]->init_shadow =
586 shadow->flags & AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW;
587 }
588
589 return 0;
590 }
591
amdgpu_cs_pass2(struct amdgpu_cs_parser * p)592 static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p)
593 {
594 unsigned int ce_preempt = 0, de_preempt = 0;
595 int i, r;
596
597 for (i = 0; i < p->nchunks; ++i) {
598 struct amdgpu_cs_chunk *chunk;
599
600 chunk = &p->chunks[i];
601
602 switch (chunk->chunk_id) {
603 case AMDGPU_CHUNK_ID_IB:
604 r = amdgpu_cs_p2_ib(p, chunk, &ce_preempt, &de_preempt);
605 if (r)
606 return r;
607 break;
608 case AMDGPU_CHUNK_ID_DEPENDENCIES:
609 case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES:
610 r = amdgpu_cs_p2_dependencies(p, chunk);
611 if (r)
612 return r;
613 break;
614 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
615 r = amdgpu_cs_p2_syncobj_in(p, chunk);
616 if (r)
617 return r;
618 break;
619 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
620 r = amdgpu_cs_p2_syncobj_out(p, chunk);
621 if (r)
622 return r;
623 break;
624 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT:
625 r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk);
626 if (r)
627 return r;
628 break;
629 case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL:
630 r = amdgpu_cs_p2_syncobj_timeline_signal(p, chunk);
631 if (r)
632 return r;
633 break;
634 case AMDGPU_CHUNK_ID_CP_GFX_SHADOW:
635 r = amdgpu_cs_p2_shadow(p, chunk);
636 if (r)
637 return r;
638 break;
639 }
640 }
641
642 return 0;
643 }
644
645 /* Convert microseconds to bytes. */
us_to_bytes(struct amdgpu_device * adev,s64 us)646 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
647 {
648 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
649 return 0;
650
651 /* Since accum_us is incremented by a million per second, just
652 * multiply it by the number of MB/s to get the number of bytes.
653 */
654 return us << adev->mm_stats.log2_max_MBps;
655 }
656
bytes_to_us(struct amdgpu_device * adev,u64 bytes)657 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
658 {
659 if (!adev->mm_stats.log2_max_MBps)
660 return 0;
661
662 return bytes >> adev->mm_stats.log2_max_MBps;
663 }
664
665 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
666 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
667 * which means it can go over the threshold once. If that happens, the driver
668 * will be in debt and no other buffer migrations can be done until that debt
669 * is repaid.
670 *
671 * This approach allows moving a buffer of any size (it's important to allow
672 * that).
673 *
674 * The currency is simply time in microseconds and it increases as the clock
675 * ticks. The accumulated microseconds (us) are converted to bytes and
676 * returned.
677 */
amdgpu_cs_get_threshold_for_moves(struct amdgpu_device * adev,u64 * max_bytes,u64 * max_vis_bytes)678 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
679 u64 *max_bytes,
680 u64 *max_vis_bytes)
681 {
682 s64 time_us, increment_us;
683 u64 free_vram, total_vram, used_vram;
684 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
685 * throttling.
686 *
687 * It means that in order to get full max MBps, at least 5 IBs per
688 * second must be submitted and not more than 200ms apart from each
689 * other.
690 */
691 const s64 us_upper_bound = 200000;
692
693 if (!adev->mm_stats.log2_max_MBps) {
694 *max_bytes = 0;
695 *max_vis_bytes = 0;
696 return;
697 }
698
699 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
700 used_vram = ttm_resource_manager_usage(&adev->mman.vram_mgr.manager);
701 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
702
703 spin_lock(&adev->mm_stats.lock);
704
705 /* Increase the amount of accumulated us. */
706 time_us = ktime_to_us(ktime_get());
707 increment_us = time_us - adev->mm_stats.last_update_us;
708 adev->mm_stats.last_update_us = time_us;
709 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
710 us_upper_bound);
711
712 /* This prevents the short period of low performance when the VRAM
713 * usage is low and the driver is in debt or doesn't have enough
714 * accumulated us to fill VRAM quickly.
715 *
716 * The situation can occur in these cases:
717 * - a lot of VRAM is freed by userspace
718 * - the presence of a big buffer causes a lot of evictions
719 * (solution: split buffers into smaller ones)
720 *
721 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
722 * accum_us to a positive number.
723 */
724 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
725 s64 min_us;
726
727 /* Be more aggressive on dGPUs. Try to fill a portion of free
728 * VRAM now.
729 */
730 if (!(adev->flags & AMD_IS_APU))
731 min_us = bytes_to_us(adev, free_vram / 4);
732 else
733 min_us = 0; /* Reset accum_us on APUs. */
734
735 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
736 }
737
738 /* This is set to 0 if the driver is in debt to disallow (optional)
739 * buffer moves.
740 */
741 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
742
743 /* Do the same for visible VRAM if half of it is free */
744 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
745 u64 total_vis_vram = adev->gmc.visible_vram_size;
746 u64 used_vis_vram =
747 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr);
748
749 if (used_vis_vram < total_vis_vram) {
750 u64 free_vis_vram = total_vis_vram - used_vis_vram;
751
752 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
753 increment_us, us_upper_bound);
754
755 if (free_vis_vram >= total_vis_vram / 2)
756 adev->mm_stats.accum_us_vis =
757 max(bytes_to_us(adev, free_vis_vram / 2),
758 adev->mm_stats.accum_us_vis);
759 }
760
761 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
762 } else {
763 *max_vis_bytes = 0;
764 }
765
766 spin_unlock(&adev->mm_stats.lock);
767 }
768
769 /* Report how many bytes have really been moved for the last command
770 * submission. This can result in a debt that can stop buffer migrations
771 * temporarily.
772 */
amdgpu_cs_report_moved_bytes(struct amdgpu_device * adev,u64 num_bytes,u64 num_vis_bytes)773 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
774 u64 num_vis_bytes)
775 {
776 spin_lock(&adev->mm_stats.lock);
777 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
778 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
779 spin_unlock(&adev->mm_stats.lock);
780 }
781
amdgpu_cs_bo_validate(void * param,struct amdgpu_bo * bo)782 static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo)
783 {
784 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
785 struct amdgpu_cs_parser *p = param;
786 struct ttm_operation_ctx ctx = {
787 .interruptible = true,
788 .no_wait_gpu = false,
789 .resv = bo->tbo.base.resv
790 };
791 uint32_t domain;
792 int r;
793
794 if (bo->tbo.pin_count)
795 return 0;
796
797 /* Don't move this buffer if we have depleted our allowance
798 * to move it. Don't move anything if the threshold is zero.
799 */
800 if (p->bytes_moved < p->bytes_moved_threshold &&
801 (!bo->tbo.base.dma_buf ||
802 list_empty(&bo->tbo.base.dma_buf->attachments))) {
803 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
804 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
805 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
806 * visible VRAM if we've depleted our allowance to do
807 * that.
808 */
809 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
810 domain = bo->preferred_domains;
811 else
812 domain = bo->allowed_domains;
813 } else {
814 domain = bo->preferred_domains;
815 }
816 } else {
817 domain = bo->allowed_domains;
818 }
819
820 retry:
821 amdgpu_bo_placement_from_domain(bo, domain);
822 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
823
824 p->bytes_moved += ctx.bytes_moved;
825 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
826 amdgpu_res_cpu_visible(adev, bo->tbo.resource))
827 p->bytes_moved_vis += ctx.bytes_moved;
828
829 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
830 domain = bo->allowed_domains;
831 goto retry;
832 }
833
834 return r;
835 }
836
amdgpu_cs_parser_bos(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)837 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
838 union drm_amdgpu_cs *cs)
839 {
840 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
841 struct ttm_operation_ctx ctx = { true, false };
842 struct amdgpu_vm *vm = &fpriv->vm;
843 struct amdgpu_bo_list_entry *e;
844 struct drm_gem_object *obj;
845 unsigned long index;
846 unsigned int i;
847 int r;
848
849 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
850 if (cs->in.bo_list_handle) {
851 if (p->bo_list)
852 return -EINVAL;
853
854 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
855 &p->bo_list);
856 if (r)
857 return r;
858 } else if (!p->bo_list) {
859 /* Create a empty bo_list when no handle is provided */
860 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
861 &p->bo_list);
862 if (r)
863 return r;
864 }
865
866 mutex_lock(&p->bo_list->bo_list_mutex);
867
868 /* Get userptr backing pages. If pages are updated after registered
869 * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do
870 * amdgpu_ttm_backend_bind() to flush and invalidate new pages
871 */
872 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
873 bool userpage_invalidated = false;
874 struct amdgpu_bo *bo = e->bo;
875 int i;
876
877 e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages,
878 sizeof(struct vm_page *),
879 GFP_KERNEL | __GFP_ZERO);
880 if (!e->user_pages) {
881 DRM_ERROR("kvmalloc_array failure\n");
882 r = -ENOMEM;
883 goto out_free_user_pages;
884 }
885
886 r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, &e->range);
887 if (r) {
888 kvfree(e->user_pages);
889 e->user_pages = NULL;
890 goto out_free_user_pages;
891 }
892
893 for (i = 0; i < bo->tbo.ttm->num_pages; i++) {
894 if (bo->tbo.ttm->pages[i] != e->user_pages[i]) {
895 userpage_invalidated = true;
896 break;
897 }
898 }
899 e->user_invalidated = userpage_invalidated;
900 }
901
902 drm_exec_until_all_locked(&p->exec) {
903 r = amdgpu_vm_lock_pd(&fpriv->vm, &p->exec, 1 + p->gang_size);
904 drm_exec_retry_on_contention(&p->exec);
905 if (unlikely(r))
906 goto out_free_user_pages;
907
908 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
909 /* One fence for TTM and one for each CS job */
910 r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base,
911 1 + p->gang_size);
912 drm_exec_retry_on_contention(&p->exec);
913 if (unlikely(r))
914 goto out_free_user_pages;
915
916 e->bo_va = amdgpu_vm_bo_find(vm, e->bo);
917 }
918
919 if (p->uf_bo) {
920 r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base,
921 1 + p->gang_size);
922 drm_exec_retry_on_contention(&p->exec);
923 if (unlikely(r))
924 goto out_free_user_pages;
925 }
926 }
927
928 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
929 #ifdef notyet
930 struct mm_struct *usermm;
931
932 usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm);
933 if (usermm && usermm != current->mm) {
934 r = -EPERM;
935 goto out_free_user_pages;
936 }
937 #endif
938
939 if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) &&
940 e->user_invalidated && e->user_pages) {
941 amdgpu_bo_placement_from_domain(e->bo,
942 AMDGPU_GEM_DOMAIN_CPU);
943 r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement,
944 &ctx);
945 if (r)
946 goto out_free_user_pages;
947
948 amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm,
949 e->user_pages);
950 }
951
952 kvfree(e->user_pages);
953 e->user_pages = NULL;
954 }
955
956 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
957 &p->bytes_moved_vis_threshold);
958 p->bytes_moved = 0;
959 p->bytes_moved_vis = 0;
960
961 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
962 amdgpu_cs_bo_validate, p);
963 if (r) {
964 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
965 goto out_free_user_pages;
966 }
967
968 drm_exec_for_each_locked_object(&p->exec, index, obj) {
969 r = amdgpu_cs_bo_validate(p, gem_to_amdgpu_bo(obj));
970 if (unlikely(r))
971 goto out_free_user_pages;
972 }
973
974 if (p->uf_bo) {
975 r = amdgpu_ttm_alloc_gart(&p->uf_bo->tbo);
976 if (unlikely(r))
977 goto out_free_user_pages;
978
979 p->gang_leader->uf_addr += amdgpu_bo_gpu_offset(p->uf_bo);
980 }
981
982 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
983 p->bytes_moved_vis);
984
985 for (i = 0; i < p->gang_size; ++i)
986 amdgpu_job_set_resources(p->jobs[i], p->bo_list->gds_obj,
987 p->bo_list->gws_obj,
988 p->bo_list->oa_obj);
989 return 0;
990
991 out_free_user_pages:
992 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
993 struct amdgpu_bo *bo = e->bo;
994
995 if (!e->user_pages)
996 continue;
997 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, e->range);
998 kvfree(e->user_pages);
999 e->user_pages = NULL;
1000 e->range = NULL;
1001 }
1002 mutex_unlock(&p->bo_list->bo_list_mutex);
1003 return r;
1004 }
1005
trace_amdgpu_cs_ibs(struct amdgpu_cs_parser * p)1006 static void trace_amdgpu_cs_ibs(struct amdgpu_cs_parser *p)
1007 {
1008 int i, j;
1009
1010 if (!trace_amdgpu_cs_enabled())
1011 return;
1012
1013 for (i = 0; i < p->gang_size; ++i) {
1014 struct amdgpu_job *job = p->jobs[i];
1015
1016 for (j = 0; j < job->num_ibs; ++j)
1017 trace_amdgpu_cs(p, job, &job->ibs[j]);
1018 }
1019 }
1020
amdgpu_cs_patch_ibs(struct amdgpu_cs_parser * p,struct amdgpu_job * job)1021 static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p,
1022 struct amdgpu_job *job)
1023 {
1024 struct amdgpu_ring *ring = amdgpu_job_ring(job);
1025 unsigned int i;
1026 int r;
1027
1028 /* Only for UVD/VCE VM emulation */
1029 if (!ring->funcs->parse_cs && !ring->funcs->patch_cs_in_place)
1030 return 0;
1031
1032 for (i = 0; i < job->num_ibs; ++i) {
1033 struct amdgpu_ib *ib = &job->ibs[i];
1034 struct amdgpu_bo_va_mapping *m;
1035 struct amdgpu_bo *aobj;
1036 uint64_t va_start;
1037 uint8_t *kptr;
1038
1039 va_start = ib->gpu_addr & AMDGPU_GMC_HOLE_MASK;
1040 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
1041 if (r) {
1042 DRM_ERROR("IB va_start is invalid\n");
1043 return r;
1044 }
1045
1046 if ((va_start + ib->length_dw * 4) >
1047 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
1048 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
1049 return -EINVAL;
1050 }
1051
1052 /* the IB should be reserved at this point */
1053 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
1054 if (r)
1055 return r;
1056
1057 kptr += va_start - (m->start * AMDGPU_GPU_PAGE_SIZE);
1058
1059 if (ring->funcs->parse_cs) {
1060 memcpy(ib->ptr, kptr, ib->length_dw * 4);
1061 amdgpu_bo_kunmap(aobj);
1062
1063 r = amdgpu_ring_parse_cs(ring, p, job, ib);
1064 if (r)
1065 return r;
1066
1067 if (ib->sa_bo)
1068 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
1069 } else {
1070 ib->ptr = (uint32_t *)kptr;
1071 r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);
1072 amdgpu_bo_kunmap(aobj);
1073 if (r)
1074 return r;
1075 }
1076 }
1077
1078 return 0;
1079 }
1080
amdgpu_cs_patch_jobs(struct amdgpu_cs_parser * p)1081 static int amdgpu_cs_patch_jobs(struct amdgpu_cs_parser *p)
1082 {
1083 unsigned int i;
1084 int r;
1085
1086 for (i = 0; i < p->gang_size; ++i) {
1087 r = amdgpu_cs_patch_ibs(p, p->jobs[i]);
1088 if (r)
1089 return r;
1090 }
1091 return 0;
1092 }
1093
amdgpu_cs_vm_handling(struct amdgpu_cs_parser * p)1094 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
1095 {
1096 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1097 struct amdgpu_job *job = p->gang_leader;
1098 struct amdgpu_device *adev = p->adev;
1099 struct amdgpu_vm *vm = &fpriv->vm;
1100 struct amdgpu_bo_list_entry *e;
1101 struct amdgpu_bo_va *bo_va;
1102 unsigned int i;
1103 int r;
1104
1105 /*
1106 * We can't use gang submit on with reserved VMIDs when the VM changes
1107 * can't be invalidated by more than one engine at the same time.
1108 */
1109 if (p->gang_size > 1 && !p->adev->vm_manager.concurrent_flush) {
1110 for (i = 0; i < p->gang_size; ++i) {
1111 struct drm_sched_entity *entity = p->entities[i];
1112 struct drm_gpu_scheduler *sched = entity->rq->sched;
1113 struct amdgpu_ring *ring = to_amdgpu_ring(sched);
1114
1115 if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub))
1116 return -EINVAL;
1117 }
1118 }
1119
1120 r = amdgpu_vm_clear_freed(adev, vm, NULL);
1121 if (r)
1122 return r;
1123
1124 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
1125 if (r)
1126 return r;
1127
1128 r = amdgpu_sync_fence(&p->sync, fpriv->prt_va->last_pt_update);
1129 if (r)
1130 return r;
1131
1132 if (fpriv->csa_va) {
1133 bo_va = fpriv->csa_va;
1134 BUG_ON(!bo_va);
1135 r = amdgpu_vm_bo_update(adev, bo_va, false);
1136 if (r)
1137 return r;
1138
1139 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1140 if (r)
1141 return r;
1142 }
1143
1144 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1145 bo_va = e->bo_va;
1146 if (bo_va == NULL)
1147 continue;
1148
1149 r = amdgpu_vm_bo_update(adev, bo_va, false);
1150 if (r)
1151 return r;
1152
1153 r = amdgpu_sync_fence(&p->sync, bo_va->last_pt_update);
1154 if (r)
1155 return r;
1156 }
1157
1158 r = amdgpu_vm_handle_moved(adev, vm);
1159 if (r)
1160 return r;
1161
1162 r = amdgpu_vm_update_pdes(adev, vm, false);
1163 if (r)
1164 return r;
1165
1166 r = amdgpu_sync_fence(&p->sync, vm->last_update);
1167 if (r)
1168 return r;
1169
1170 for (i = 0; i < p->gang_size; ++i) {
1171 job = p->jobs[i];
1172
1173 if (!job->vm)
1174 continue;
1175
1176 job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.bo);
1177 }
1178
1179 if (amdgpu_vm_debug) {
1180 /* Invalidate all BOs to test for userspace bugs */
1181 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
1182 struct amdgpu_bo *bo = e->bo;
1183
1184 /* ignore duplicates */
1185 if (!bo)
1186 continue;
1187
1188 amdgpu_vm_bo_invalidate(adev, bo, false);
1189 }
1190 }
1191
1192 return 0;
1193 }
1194
amdgpu_cs_sync_rings(struct amdgpu_cs_parser * p)1195 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
1196 {
1197 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1198 struct drm_gpu_scheduler *sched;
1199 struct drm_gem_object *obj;
1200 struct dma_fence *fence;
1201 unsigned long index;
1202 unsigned int i;
1203 int r;
1204
1205 r = amdgpu_ctx_wait_prev_fence(p->ctx, p->entities[p->gang_leader_idx]);
1206 if (r) {
1207 if (r != -ERESTARTSYS)
1208 DRM_ERROR("amdgpu_ctx_wait_prev_fence failed.\n");
1209 return r;
1210 }
1211
1212 drm_exec_for_each_locked_object(&p->exec, index, obj) {
1213 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
1214
1215 struct dma_resv *resv = bo->tbo.base.resv;
1216 enum amdgpu_sync_mode sync_mode;
1217
1218 sync_mode = amdgpu_bo_explicit_sync(bo) ?
1219 AMDGPU_SYNC_EXPLICIT : AMDGPU_SYNC_NE_OWNER;
1220 r = amdgpu_sync_resv(p->adev, &p->sync, resv, sync_mode,
1221 &fpriv->vm);
1222 if (r)
1223 return r;
1224 }
1225
1226 for (i = 0; i < p->gang_size; ++i) {
1227 r = amdgpu_sync_push_to_job(&p->sync, p->jobs[i]);
1228 if (r)
1229 return r;
1230 }
1231
1232 sched = p->gang_leader->base.entity->rq->sched;
1233 while ((fence = amdgpu_sync_get_fence(&p->sync))) {
1234 struct drm_sched_fence *s_fence = to_drm_sched_fence(fence);
1235
1236 /*
1237 * When we have an dependency it might be necessary to insert a
1238 * pipeline sync to make sure that all caches etc are flushed and the
1239 * next job actually sees the results from the previous one
1240 * before we start executing on the same scheduler ring.
1241 */
1242 if (!s_fence || s_fence->sched != sched) {
1243 dma_fence_put(fence);
1244 continue;
1245 }
1246
1247 r = amdgpu_sync_fence(&p->gang_leader->explicit_sync, fence);
1248 dma_fence_put(fence);
1249 if (r)
1250 return r;
1251 }
1252 return 0;
1253 }
1254
amdgpu_cs_post_dependencies(struct amdgpu_cs_parser * p)1255 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1256 {
1257 int i;
1258
1259 for (i = 0; i < p->num_post_deps; ++i) {
1260 if (p->post_deps[i].chain && p->post_deps[i].point) {
1261 drm_syncobj_add_point(p->post_deps[i].syncobj,
1262 p->post_deps[i].chain,
1263 p->fence, p->post_deps[i].point);
1264 p->post_deps[i].chain = NULL;
1265 } else {
1266 drm_syncobj_replace_fence(p->post_deps[i].syncobj,
1267 p->fence);
1268 }
1269 }
1270 }
1271
amdgpu_cs_submit(struct amdgpu_cs_parser * p,union drm_amdgpu_cs * cs)1272 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1273 union drm_amdgpu_cs *cs)
1274 {
1275 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1276 struct amdgpu_job *leader = p->gang_leader;
1277 struct amdgpu_bo_list_entry *e;
1278 struct drm_gem_object *gobj;
1279 unsigned long index;
1280 unsigned int i;
1281 uint64_t seq;
1282 int r;
1283
1284 for (i = 0; i < p->gang_size; ++i)
1285 drm_sched_job_arm(&p->jobs[i]->base);
1286
1287 for (i = 0; i < p->gang_size; ++i) {
1288 struct dma_fence *fence;
1289
1290 if (p->jobs[i] == leader)
1291 continue;
1292
1293 fence = &p->jobs[i]->base.s_fence->scheduled;
1294 dma_fence_get(fence);
1295 r = drm_sched_job_add_dependency(&leader->base, fence);
1296 if (r) {
1297 dma_fence_put(fence);
1298 return r;
1299 }
1300 }
1301
1302 if (p->gang_size > 1) {
1303 for (i = 0; i < p->gang_size; ++i)
1304 amdgpu_job_set_gang_leader(p->jobs[i], leader);
1305 }
1306
1307 /* No memory allocation is allowed while holding the notifier lock.
1308 * The lock is held until amdgpu_cs_submit is finished and fence is
1309 * added to BOs.
1310 */
1311 mutex_lock(&p->adev->notifier_lock);
1312
1313 /* If userptr are invalidated after amdgpu_cs_parser_bos(), return
1314 * -EAGAIN, drmIoctl in libdrm will restart the amdgpu_cs_ioctl.
1315 */
1316 r = 0;
1317 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1318 r |= !amdgpu_ttm_tt_get_user_pages_done(e->bo->tbo.ttm,
1319 e->range);
1320 e->range = NULL;
1321 }
1322 if (r) {
1323 r = -EAGAIN;
1324 mutex_unlock(&p->adev->notifier_lock);
1325 return r;
1326 }
1327
1328 p->fence = dma_fence_get(&leader->base.s_fence->finished);
1329 drm_exec_for_each_locked_object(&p->exec, index, gobj) {
1330
1331 ttm_bo_move_to_lru_tail_unlocked(&gem_to_amdgpu_bo(gobj)->tbo);
1332
1333 /* Everybody except for the gang leader uses READ */
1334 for (i = 0; i < p->gang_size; ++i) {
1335 if (p->jobs[i] == leader)
1336 continue;
1337
1338 dma_resv_add_fence(gobj->resv,
1339 &p->jobs[i]->base.s_fence->finished,
1340 DMA_RESV_USAGE_READ);
1341 }
1342
1343 /* The gang leader as remembered as writer */
1344 dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE);
1345 }
1346
1347 seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx],
1348 p->fence);
1349 amdgpu_cs_post_dependencies(p);
1350
1351 if ((leader->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1352 !p->ctx->preamble_presented) {
1353 leader->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1354 p->ctx->preamble_presented = true;
1355 }
1356
1357 cs->out.handle = seq;
1358 leader->uf_sequence = seq;
1359
1360 amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->exec.ticket);
1361 for (i = 0; i < p->gang_size; ++i) {
1362 amdgpu_job_free_resources(p->jobs[i]);
1363 trace_amdgpu_cs_ioctl(p->jobs[i]);
1364 drm_sched_entity_push_job(&p->jobs[i]->base);
1365 p->jobs[i] = NULL;
1366 }
1367
1368 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1369
1370 mutex_unlock(&p->adev->notifier_lock);
1371 mutex_unlock(&p->bo_list->bo_list_mutex);
1372 return 0;
1373 }
1374
1375 /* Cleanup the parser structure */
amdgpu_cs_parser_fini(struct amdgpu_cs_parser * parser)1376 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser)
1377 {
1378 unsigned int i;
1379
1380 amdgpu_sync_free(&parser->sync);
1381 drm_exec_fini(&parser->exec);
1382
1383 for (i = 0; i < parser->num_post_deps; i++) {
1384 drm_syncobj_put(parser->post_deps[i].syncobj);
1385 kfree(parser->post_deps[i].chain);
1386 }
1387 kfree(parser->post_deps);
1388
1389 dma_fence_put(parser->fence);
1390
1391 if (parser->ctx)
1392 amdgpu_ctx_put(parser->ctx);
1393 if (parser->bo_list)
1394 amdgpu_bo_list_put(parser->bo_list);
1395
1396 for (i = 0; i < parser->nchunks; i++)
1397 kvfree(parser->chunks[i].kdata);
1398 kvfree(parser->chunks);
1399 for (i = 0; i < parser->gang_size; ++i) {
1400 if (parser->jobs[i])
1401 amdgpu_job_free(parser->jobs[i]);
1402 }
1403 amdgpu_bo_unref(&parser->uf_bo);
1404 }
1405
amdgpu_cs_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1406 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1407 {
1408 struct amdgpu_device *adev = drm_to_adev(dev);
1409 struct amdgpu_cs_parser parser;
1410 int r;
1411
1412 if (amdgpu_ras_intr_triggered())
1413 return -EHWPOISON;
1414
1415 if (!adev->accel_working)
1416 return -EBUSY;
1417
1418 r = amdgpu_cs_parser_init(&parser, adev, filp, data);
1419 if (r) {
1420 if (printk_ratelimit())
1421 DRM_ERROR("Failed to initialize parser %d!\n", r);
1422 return r;
1423 }
1424
1425 r = amdgpu_cs_pass1(&parser, data);
1426 if (r)
1427 goto error_fini;
1428
1429 r = amdgpu_cs_pass2(&parser);
1430 if (r)
1431 goto error_fini;
1432
1433 r = amdgpu_cs_parser_bos(&parser, data);
1434 if (r) {
1435 if (r == -ENOMEM)
1436 DRM_ERROR("Not enough memory for command submission!\n");
1437 else if (r != -ERESTARTSYS && r != -EAGAIN)
1438 DRM_DEBUG("Failed to process the buffer list %d!\n", r);
1439 goto error_fini;
1440 }
1441
1442 r = amdgpu_cs_patch_jobs(&parser);
1443 if (r)
1444 goto error_backoff;
1445
1446 r = amdgpu_cs_vm_handling(&parser);
1447 if (r)
1448 goto error_backoff;
1449
1450 r = amdgpu_cs_sync_rings(&parser);
1451 if (r)
1452 goto error_backoff;
1453
1454 trace_amdgpu_cs_ibs(&parser);
1455
1456 r = amdgpu_cs_submit(&parser, data);
1457 if (r)
1458 goto error_backoff;
1459
1460 amdgpu_cs_parser_fini(&parser);
1461 return 0;
1462
1463 error_backoff:
1464 mutex_unlock(&parser.bo_list->bo_list_mutex);
1465
1466 error_fini:
1467 amdgpu_cs_parser_fini(&parser);
1468 return r;
1469 }
1470
1471 /**
1472 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1473 *
1474 * @dev: drm device
1475 * @data: data from userspace
1476 * @filp: file private
1477 *
1478 * Wait for the command submission identified by handle to finish.
1479 */
amdgpu_cs_wait_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1480 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1481 struct drm_file *filp)
1482 {
1483 union drm_amdgpu_wait_cs *wait = data;
1484 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1485 struct drm_sched_entity *entity;
1486 struct amdgpu_ctx *ctx;
1487 struct dma_fence *fence;
1488 long r;
1489
1490 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1491 if (ctx == NULL)
1492 return -EINVAL;
1493
1494 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1495 wait->in.ring, &entity);
1496 if (r) {
1497 amdgpu_ctx_put(ctx);
1498 return r;
1499 }
1500
1501 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1502 if (IS_ERR(fence))
1503 r = PTR_ERR(fence);
1504 else if (fence) {
1505 r = dma_fence_wait_timeout(fence, true, timeout);
1506 if (r > 0 && fence->error)
1507 r = fence->error;
1508 dma_fence_put(fence);
1509 } else
1510 r = 1;
1511
1512 amdgpu_ctx_put(ctx);
1513 if (r < 0)
1514 return r;
1515
1516 memset(wait, 0, sizeof(*wait));
1517 wait->out.status = (r == 0);
1518
1519 return 0;
1520 }
1521
1522 /**
1523 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1524 *
1525 * @adev: amdgpu device
1526 * @filp: file private
1527 * @user: drm_amdgpu_fence copied from user space
1528 */
amdgpu_cs_get_fence(struct amdgpu_device * adev,struct drm_file * filp,struct drm_amdgpu_fence * user)1529 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1530 struct drm_file *filp,
1531 struct drm_amdgpu_fence *user)
1532 {
1533 struct drm_sched_entity *entity;
1534 struct amdgpu_ctx *ctx;
1535 struct dma_fence *fence;
1536 int r;
1537
1538 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1539 if (ctx == NULL)
1540 return ERR_PTR(-EINVAL);
1541
1542 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1543 user->ring, &entity);
1544 if (r) {
1545 amdgpu_ctx_put(ctx);
1546 return ERR_PTR(r);
1547 }
1548
1549 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1550 amdgpu_ctx_put(ctx);
1551
1552 return fence;
1553 }
1554
amdgpu_cs_fence_to_handle_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1555 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1556 struct drm_file *filp)
1557 {
1558 struct amdgpu_device *adev = drm_to_adev(dev);
1559 union drm_amdgpu_fence_to_handle *info = data;
1560 struct dma_fence *fence;
1561 struct drm_syncobj *syncobj;
1562 struct sync_file *sync_file;
1563 int fd, r;
1564
1565 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1566 if (IS_ERR(fence))
1567 return PTR_ERR(fence);
1568
1569 if (!fence)
1570 fence = dma_fence_get_stub();
1571
1572 switch (info->in.what) {
1573 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1574 r = drm_syncobj_create(&syncobj, 0, fence);
1575 dma_fence_put(fence);
1576 if (r)
1577 return r;
1578 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1579 drm_syncobj_put(syncobj);
1580 return r;
1581
1582 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1583 r = drm_syncobj_create(&syncobj, 0, fence);
1584 dma_fence_put(fence);
1585 if (r)
1586 return r;
1587 r = drm_syncobj_get_fd(syncobj, (int *)&info->out.handle);
1588 drm_syncobj_put(syncobj);
1589 return r;
1590
1591 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1592 fd = get_unused_fd_flags(O_CLOEXEC);
1593 if (fd < 0) {
1594 dma_fence_put(fence);
1595 return fd;
1596 }
1597
1598 sync_file = sync_file_create(fence);
1599 dma_fence_put(fence);
1600 if (!sync_file) {
1601 put_unused_fd(fd);
1602 return -ENOMEM;
1603 }
1604
1605 fd_install(fd, sync_file->file);
1606 info->out.handle = fd;
1607 return 0;
1608
1609 default:
1610 dma_fence_put(fence);
1611 return -EINVAL;
1612 }
1613 }
1614
1615 /**
1616 * amdgpu_cs_wait_all_fences - wait on all fences to signal
1617 *
1618 * @adev: amdgpu device
1619 * @filp: file private
1620 * @wait: wait parameters
1621 * @fences: array of drm_amdgpu_fence
1622 */
amdgpu_cs_wait_all_fences(struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_wait_fences * wait,struct drm_amdgpu_fence * fences)1623 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1624 struct drm_file *filp,
1625 union drm_amdgpu_wait_fences *wait,
1626 struct drm_amdgpu_fence *fences)
1627 {
1628 uint32_t fence_count = wait->in.fence_count;
1629 unsigned int i;
1630 long r = 1;
1631
1632 for (i = 0; i < fence_count; i++) {
1633 struct dma_fence *fence;
1634 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1635
1636 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1637 if (IS_ERR(fence))
1638 return PTR_ERR(fence);
1639 else if (!fence)
1640 continue;
1641
1642 r = dma_fence_wait_timeout(fence, true, timeout);
1643 if (r > 0 && fence->error)
1644 r = fence->error;
1645
1646 dma_fence_put(fence);
1647 if (r < 0)
1648 return r;
1649
1650 if (r == 0)
1651 break;
1652 }
1653
1654 memset(wait, 0, sizeof(*wait));
1655 wait->out.status = (r > 0);
1656
1657 return 0;
1658 }
1659
1660 /**
1661 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1662 *
1663 * @adev: amdgpu device
1664 * @filp: file private
1665 * @wait: wait parameters
1666 * @fences: array of drm_amdgpu_fence
1667 */
amdgpu_cs_wait_any_fence(struct amdgpu_device * adev,struct drm_file * filp,union drm_amdgpu_wait_fences * wait,struct drm_amdgpu_fence * fences)1668 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1669 struct drm_file *filp,
1670 union drm_amdgpu_wait_fences *wait,
1671 struct drm_amdgpu_fence *fences)
1672 {
1673 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1674 uint32_t fence_count = wait->in.fence_count;
1675 uint32_t first = ~0;
1676 struct dma_fence **array;
1677 unsigned int i;
1678 long r;
1679
1680 /* Prepare the fence array */
1681 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1682
1683 if (array == NULL)
1684 return -ENOMEM;
1685
1686 for (i = 0; i < fence_count; i++) {
1687 struct dma_fence *fence;
1688
1689 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1690 if (IS_ERR(fence)) {
1691 r = PTR_ERR(fence);
1692 goto err_free_fence_array;
1693 } else if (fence) {
1694 array[i] = fence;
1695 } else { /* NULL, the fence has been already signaled */
1696 r = 1;
1697 first = i;
1698 goto out;
1699 }
1700 }
1701
1702 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1703 &first);
1704 if (r < 0)
1705 goto err_free_fence_array;
1706
1707 out:
1708 memset(wait, 0, sizeof(*wait));
1709 wait->out.status = (r > 0);
1710 wait->out.first_signaled = first;
1711
1712 if (first < fence_count && array[first])
1713 r = array[first]->error;
1714 else
1715 r = 0;
1716
1717 err_free_fence_array:
1718 for (i = 0; i < fence_count; i++)
1719 dma_fence_put(array[i]);
1720 kfree(array);
1721
1722 return r;
1723 }
1724
1725 /**
1726 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1727 *
1728 * @dev: drm device
1729 * @data: data from userspace
1730 * @filp: file private
1731 */
amdgpu_cs_wait_fences_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)1732 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1733 struct drm_file *filp)
1734 {
1735 struct amdgpu_device *adev = drm_to_adev(dev);
1736 union drm_amdgpu_wait_fences *wait = data;
1737 uint32_t fence_count = wait->in.fence_count;
1738 struct drm_amdgpu_fence *fences_user;
1739 struct drm_amdgpu_fence *fences;
1740 int r;
1741
1742 /* Get the fences from userspace */
1743 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1744 GFP_KERNEL);
1745 if (fences == NULL)
1746 return -ENOMEM;
1747
1748 fences_user = u64_to_user_ptr(wait->in.fences);
1749 if (copy_from_user(fences, fences_user,
1750 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1751 r = -EFAULT;
1752 goto err_free_fences;
1753 }
1754
1755 if (wait->in.wait_all)
1756 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1757 else
1758 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1759
1760 err_free_fences:
1761 kfree(fences);
1762
1763 return r;
1764 }
1765
1766 /**
1767 * amdgpu_cs_find_mapping - find bo_va for VM address
1768 *
1769 * @parser: command submission parser context
1770 * @addr: VM address
1771 * @bo: resulting BO of the mapping found
1772 * @map: Placeholder to return found BO mapping
1773 *
1774 * Search the buffer objects in the command submission context for a certain
1775 * virtual memory address. Returns allocation structure when found, NULL
1776 * otherwise.
1777 */
amdgpu_cs_find_mapping(struct amdgpu_cs_parser * parser,uint64_t addr,struct amdgpu_bo ** bo,struct amdgpu_bo_va_mapping ** map)1778 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1779 uint64_t addr, struct amdgpu_bo **bo,
1780 struct amdgpu_bo_va_mapping **map)
1781 {
1782 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1783 struct ttm_operation_ctx ctx = { false, false };
1784 struct amdgpu_vm *vm = &fpriv->vm;
1785 struct amdgpu_bo_va_mapping *mapping;
1786 int r;
1787
1788 addr /= AMDGPU_GPU_PAGE_SIZE;
1789
1790 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1791 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1792 return -EINVAL;
1793
1794 *bo = mapping->bo_va->base.bo;
1795 *map = mapping;
1796
1797 /* Double check that the BO is reserved by this CS */
1798 if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket)
1799 return -EINVAL;
1800
1801 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1802 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1803 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1804 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1805 if (r)
1806 return r;
1807 }
1808
1809 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1810 }
1811