1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 /**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45 #include <linux/irq.h>
46 #include <linux/pci.h>
47
48 #include <drm/drm_vblank.h>
49 #include <drm/amdgpu_drm.h>
50 #include <drm/drm_drv.h>
51 #include "amdgpu.h"
52 #include "amdgpu_ih.h"
53 #include "atom.h"
54 #include "amdgpu_connectors.h"
55 #include "amdgpu_trace.h"
56 #include "amdgpu_amdkfd.h"
57 #include "amdgpu_ras.h"
58
59 #include <linux/pm_runtime.h>
60
61 #ifdef CONFIG_DRM_AMD_DC
62 #include "amdgpu_dm_irq.h"
63 #endif
64
65 #define AMDGPU_WAIT_IDLE_TIMEOUT 200
66
67 const char *soc15_ih_clientid_name[] = {
68 "IH",
69 "SDMA2 or ACP",
70 "ATHUB",
71 "BIF",
72 "SDMA3 or DCE",
73 "SDMA4 or ISP",
74 "VMC1 or PCIE0",
75 "RLC",
76 "SDMA0",
77 "SDMA1",
78 "SE0SH",
79 "SE1SH",
80 "SE2SH",
81 "SE3SH",
82 "VCN1 or UVD1",
83 "THM",
84 "VCN or UVD",
85 "SDMA5 or VCE0",
86 "VMC",
87 "SDMA6 or XDMA",
88 "GRBM_CP",
89 "ATS",
90 "ROM_SMUIO",
91 "DF",
92 "SDMA7 or VCE1",
93 "PWR",
94 "reserved",
95 "UTCL2",
96 "EA",
97 "UTCL2LOG",
98 "MP0",
99 "MP1"
100 };
101
102 const int node_id_to_phys_map[NODEID_MAX] = {
103 [AID0_NODEID] = 0,
104 [XCD0_NODEID] = 0,
105 [XCD1_NODEID] = 1,
106 [AID1_NODEID] = 1,
107 [XCD2_NODEID] = 2,
108 [XCD3_NODEID] = 3,
109 [AID2_NODEID] = 2,
110 [XCD4_NODEID] = 4,
111 [XCD5_NODEID] = 5,
112 [AID3_NODEID] = 3,
113 [XCD6_NODEID] = 6,
114 [XCD7_NODEID] = 7,
115 };
116
117 /**
118 * amdgpu_irq_disable_all - disable *all* interrupts
119 *
120 * @adev: amdgpu device pointer
121 *
122 * Disable all types of interrupts from all sources.
123 */
amdgpu_irq_disable_all(struct amdgpu_device * adev)124 void amdgpu_irq_disable_all(struct amdgpu_device *adev)
125 {
126 unsigned long irqflags;
127 unsigned int i, j, k;
128 int r;
129
130 spin_lock_irqsave(&adev->irq.lock, irqflags);
131 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
132 if (!adev->irq.client[i].sources)
133 continue;
134
135 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
136 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
137
138 if (!src || !src->funcs->set || !src->num_types)
139 continue;
140
141 for (k = 0; k < src->num_types; ++k) {
142 r = src->funcs->set(adev, src, k,
143 AMDGPU_IRQ_STATE_DISABLE);
144 if (r)
145 DRM_ERROR("error disabling interrupt (%d)\n",
146 r);
147 }
148 }
149 }
150 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
151 }
152
153 /**
154 * amdgpu_irq_handler - IRQ handler
155 *
156 * @irq: IRQ number (unused)
157 * @arg: pointer to DRM device
158 *
159 * IRQ handler for amdgpu driver (all ASICs).
160 *
161 * Returns:
162 * result of handling the IRQ, as defined by &irqreturn_t
163 */
amdgpu_irq_handler(void * arg)164 irqreturn_t amdgpu_irq_handler(void *arg)
165 {
166 struct drm_device *dev = (struct drm_device *) arg;
167 struct amdgpu_device *adev = drm_to_adev(dev);
168 irqreturn_t ret;
169
170 if (!adev->irq.installed)
171 return 0;
172
173 ret = amdgpu_ih_process(adev, &adev->irq.ih);
174 if (ret == IRQ_HANDLED)
175 pm_runtime_mark_last_busy(dev->dev);
176
177 amdgpu_ras_interrupt_fatal_error_handler(adev);
178
179 return ret;
180 }
181
182 /**
183 * amdgpu_irq_handle_ih1 - kick of processing for IH1
184 *
185 * @work: work structure in struct amdgpu_irq
186 *
187 * Kick of processing IH ring 1.
188 */
amdgpu_irq_handle_ih1(struct work_struct * work)189 static void amdgpu_irq_handle_ih1(struct work_struct *work)
190 {
191 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
192 irq.ih1_work);
193
194 amdgpu_ih_process(adev, &adev->irq.ih1);
195 }
196
197 /**
198 * amdgpu_irq_handle_ih2 - kick of processing for IH2
199 *
200 * @work: work structure in struct amdgpu_irq
201 *
202 * Kick of processing IH ring 2.
203 */
amdgpu_irq_handle_ih2(struct work_struct * work)204 static void amdgpu_irq_handle_ih2(struct work_struct *work)
205 {
206 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
207 irq.ih2_work);
208
209 amdgpu_ih_process(adev, &adev->irq.ih2);
210 }
211
212 /**
213 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft
214 *
215 * @work: work structure in struct amdgpu_irq
216 *
217 * Kick of processing IH soft ring.
218 */
amdgpu_irq_handle_ih_soft(struct work_struct * work)219 static void amdgpu_irq_handle_ih_soft(struct work_struct *work)
220 {
221 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
222 irq.ih_soft_work);
223
224 amdgpu_ih_process(adev, &adev->irq.ih_soft);
225 }
226
227 /**
228 * amdgpu_msi_ok - check whether MSI functionality is enabled
229 *
230 * @adev: amdgpu device pointer (unused)
231 *
232 * Checks whether MSI functionality has been disabled via module parameter
233 * (all ASICs).
234 *
235 * Returns:
236 * *true* if MSIs are allowed to be enabled or *false* otherwise
237 */
amdgpu_msi_ok(struct amdgpu_device * adev)238 bool amdgpu_msi_ok(struct amdgpu_device *adev)
239 {
240 if (amdgpu_msi == 1)
241 return true;
242 else if (amdgpu_msi == 0)
243 return false;
244
245 return true;
246 }
247
amdgpu_restore_msix(struct amdgpu_device * adev)248 static void amdgpu_restore_msix(struct amdgpu_device *adev)
249 {
250 STUB();
251 #ifdef notyet
252 u16 ctrl;
253
254 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
255 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))
256 return;
257
258 /* VF FLR */
259 ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
260 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
261 ctrl |= PCI_MSIX_FLAGS_ENABLE;
262 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
263 #endif
264 }
265
266 /**
267 * amdgpu_irq_init - initialize interrupt handling
268 *
269 * @adev: amdgpu device pointer
270 *
271 * Sets up work functions for hotplug and reset interrupts, enables MSI
272 * functionality, initializes vblank, hotplug and reset interrupt handling.
273 *
274 * Returns:
275 * 0 on success or error code on failure
276 */
amdgpu_irq_init(struct amdgpu_device * adev)277 int amdgpu_irq_init(struct amdgpu_device *adev)
278 {
279 int r = 0;
280 unsigned int irq;
281
282 mtx_init(&adev->irq.lock, IPL_TTY);
283
284 #ifdef notyet
285 /* Enable MSI if not disabled by module parameter */
286 adev->irq.msi_enabled = false;
287
288 if (amdgpu_msi_ok(adev)) {
289 int nvec = pci_msix_vec_count(adev->pdev);
290 unsigned int flags;
291
292 if (nvec <= 0)
293 flags = PCI_IRQ_MSI;
294 else
295 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
296
297 /* we only need one vector */
298 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
299 if (nvec > 0) {
300 adev->irq.msi_enabled = true;
301 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
302 }
303 }
304 #endif
305
306 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
307 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
308 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
309
310 /* Use vector 0 for MSI-X. */
311 r = pci_irq_vector(adev->pdev, 0);
312 if (r < 0)
313 return r;
314 irq = r;
315
316 /* PCI devices require shared interrupts. */
317 r = request_irq(irq, amdgpu_irq_handler, IRQF_SHARED, adev_to_drm(adev)->driver->name,
318 adev_to_drm(adev));
319 if (r)
320 return r;
321 adev->irq.installed = true;
322 adev->irq.irq = irq;
323 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
324
325 DRM_DEBUG("amdgpu: irq initialized.\n");
326 return 0;
327 }
328
329
amdgpu_irq_fini_hw(struct amdgpu_device * adev)330 void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
331 {
332 if (adev->irq.installed) {
333 free_irq(adev->irq.irq, adev_to_drm(adev));
334 adev->irq.installed = false;
335 if (adev->irq.msi_enabled)
336 pci_free_irq_vectors(adev->pdev);
337 }
338
339 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
340 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
341 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
342 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
343 }
344
345 /**
346 * amdgpu_irq_fini_sw - shut down interrupt handling
347 *
348 * @adev: amdgpu device pointer
349 *
350 * Tears down work functions for hotplug and reset interrupts, disables MSI
351 * functionality, shuts down vblank, hotplug and reset interrupt handling,
352 * turns off interrupts from all sources (all ASICs).
353 */
amdgpu_irq_fini_sw(struct amdgpu_device * adev)354 void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
355 {
356 unsigned int i, j;
357
358 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
359 if (!adev->irq.client[i].sources)
360 continue;
361
362 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
363 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
364
365 if (!src)
366 continue;
367
368 kfree(src->enabled_types);
369 src->enabled_types = NULL;
370 }
371 kfree(adev->irq.client[i].sources);
372 adev->irq.client[i].sources = NULL;
373 }
374 }
375
376 /**
377 * amdgpu_irq_add_id - register IRQ source
378 *
379 * @adev: amdgpu device pointer
380 * @client_id: client id
381 * @src_id: source id
382 * @source: IRQ source pointer
383 *
384 * Registers IRQ source on a client.
385 *
386 * Returns:
387 * 0 on success or error code otherwise
388 */
amdgpu_irq_add_id(struct amdgpu_device * adev,unsigned int client_id,unsigned int src_id,struct amdgpu_irq_src * source)389 int amdgpu_irq_add_id(struct amdgpu_device *adev,
390 unsigned int client_id, unsigned int src_id,
391 struct amdgpu_irq_src *source)
392 {
393 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
394 return -EINVAL;
395
396 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
397 return -EINVAL;
398
399 if (!source->funcs)
400 return -EINVAL;
401
402 if (!adev->irq.client[client_id].sources) {
403 adev->irq.client[client_id].sources =
404 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
405 sizeof(struct amdgpu_irq_src *),
406 GFP_KERNEL);
407 if (!adev->irq.client[client_id].sources)
408 return -ENOMEM;
409 }
410
411 if (adev->irq.client[client_id].sources[src_id] != NULL)
412 return -EINVAL;
413
414 if (source->num_types && !source->enabled_types) {
415 atomic_t *types;
416
417 types = kcalloc(source->num_types, sizeof(atomic_t),
418 GFP_KERNEL);
419 if (!types)
420 return -ENOMEM;
421
422 source->enabled_types = types;
423 }
424
425 adev->irq.client[client_id].sources[src_id] = source;
426 return 0;
427 }
428
429 /**
430 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
431 *
432 * @adev: amdgpu device pointer
433 * @ih: interrupt ring instance
434 *
435 * Dispatches IRQ to IP blocks.
436 */
amdgpu_irq_dispatch(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)437 void amdgpu_irq_dispatch(struct amdgpu_device *adev,
438 struct amdgpu_ih_ring *ih)
439 {
440 u32 ring_index = ih->rptr >> 2;
441 struct amdgpu_iv_entry entry;
442 unsigned int client_id, src_id;
443 struct amdgpu_irq_src *src;
444 bool handled = false;
445 int r;
446
447 entry.ih = ih;
448 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
449
450 /*
451 * timestamp is not supported on some legacy SOCs (cik, cz, iceland,
452 * si and tonga), so initialize timestamp and timestamp_src to 0
453 */
454 entry.timestamp = 0;
455 entry.timestamp_src = 0;
456
457 amdgpu_ih_decode_iv(adev, &entry);
458
459 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
460
461 client_id = entry.client_id;
462 src_id = entry.src_id;
463
464 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
465 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
466
467 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
468 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
469
470 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
471 adev->irq.virq[src_id]) {
472 STUB();
473 #ifdef notyet
474 generic_handle_domain_irq(adev->irq.domain, src_id);
475 #endif
476
477 } else if (!adev->irq.client[client_id].sources) {
478 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
479 client_id, src_id);
480
481 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
482 r = src->funcs->process(adev, src, &entry);
483 if (r < 0)
484 DRM_ERROR("error processing interrupt (%d)\n", r);
485 else if (r)
486 handled = true;
487
488 } else {
489 DRM_DEBUG("Unregistered interrupt src_id: %d of client_id:%d\n",
490 src_id, client_id);
491 }
492
493 /* Send it to amdkfd as well if it isn't already handled */
494 if (!handled)
495 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
496
497 if (amdgpu_ih_ts_after(ih->processed_timestamp, entry.timestamp))
498 ih->processed_timestamp = entry.timestamp;
499 }
500
501 /**
502 * amdgpu_irq_delegate - delegate IV to soft IH ring
503 *
504 * @adev: amdgpu device pointer
505 * @entry: IV entry
506 * @num_dw: size of IV
507 *
508 * Delegate the IV to the soft IH ring and schedule processing of it. Used
509 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.
510 */
amdgpu_irq_delegate(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry,unsigned int num_dw)511 void amdgpu_irq_delegate(struct amdgpu_device *adev,
512 struct amdgpu_iv_entry *entry,
513 unsigned int num_dw)
514 {
515 amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw);
516 schedule_work(&adev->irq.ih_soft_work);
517 }
518
519 /**
520 * amdgpu_irq_update - update hardware interrupt state
521 *
522 * @adev: amdgpu device pointer
523 * @src: interrupt source pointer
524 * @type: type of interrupt
525 *
526 * Updates interrupt state for the specific source (all ASICs).
527 */
amdgpu_irq_update(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)528 int amdgpu_irq_update(struct amdgpu_device *adev,
529 struct amdgpu_irq_src *src, unsigned int type)
530 {
531 unsigned long irqflags;
532 enum amdgpu_interrupt_state state;
533 int r;
534
535 spin_lock_irqsave(&adev->irq.lock, irqflags);
536
537 /* We need to determine after taking the lock, otherwise
538 * we might disable just enabled interrupts again
539 */
540 if (amdgpu_irq_enabled(adev, src, type))
541 state = AMDGPU_IRQ_STATE_ENABLE;
542 else
543 state = AMDGPU_IRQ_STATE_DISABLE;
544
545 r = src->funcs->set(adev, src, type, state);
546 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
547 return r;
548 }
549
550 /**
551 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
552 *
553 * @adev: amdgpu device pointer
554 *
555 * Updates state of all types of interrupts on all sources on resume after
556 * reset.
557 */
amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device * adev)558 void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
559 {
560 int i, j, k;
561
562 if (amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev))
563 amdgpu_restore_msix(adev);
564
565 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
566 if (!adev->irq.client[i].sources)
567 continue;
568
569 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
570 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
571
572 if (!src || !src->funcs || !src->funcs->set)
573 continue;
574 for (k = 0; k < src->num_types; k++)
575 amdgpu_irq_update(adev, src, k);
576 }
577 }
578 }
579
580 /**
581 * amdgpu_irq_get - enable interrupt
582 *
583 * @adev: amdgpu device pointer
584 * @src: interrupt source pointer
585 * @type: type of interrupt
586 *
587 * Enables specified type of interrupt on the specified source (all ASICs).
588 *
589 * Returns:
590 * 0 on success or error code otherwise
591 */
amdgpu_irq_get(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)592 int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
593 unsigned int type)
594 {
595 if (!adev->irq.installed)
596 return -ENOENT;
597
598 if (type >= src->num_types)
599 return -EINVAL;
600
601 if (!src->enabled_types || !src->funcs->set)
602 return -EINVAL;
603
604 if (atomic_inc_return(&src->enabled_types[type]) == 1)
605 return amdgpu_irq_update(adev, src, type);
606
607 return 0;
608 }
609
610 /**
611 * amdgpu_irq_put - disable interrupt
612 *
613 * @adev: amdgpu device pointer
614 * @src: interrupt source pointer
615 * @type: type of interrupt
616 *
617 * Enables specified type of interrupt on the specified source (all ASICs).
618 *
619 * Returns:
620 * 0 on success or error code otherwise
621 */
amdgpu_irq_put(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)622 int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
623 unsigned int type)
624 {
625 if (!adev->irq.installed)
626 return -ENOENT;
627
628 if (type >= src->num_types)
629 return -EINVAL;
630
631 if (!src->enabled_types || !src->funcs->set)
632 return -EINVAL;
633
634 if (WARN_ON(!amdgpu_irq_enabled(adev, src, type)))
635 return -EINVAL;
636
637 if (atomic_dec_and_test(&src->enabled_types[type]))
638 return amdgpu_irq_update(adev, src, type);
639
640 return 0;
641 }
642
643 /**
644 * amdgpu_irq_enabled - check whether interrupt is enabled or not
645 *
646 * @adev: amdgpu device pointer
647 * @src: interrupt source pointer
648 * @type: type of interrupt
649 *
650 * Checks whether the given type of interrupt is enabled on the given source.
651 *
652 * Returns:
653 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
654 * invalid parameters
655 */
amdgpu_irq_enabled(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type)656 bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
657 unsigned int type)
658 {
659 if (!adev->irq.installed)
660 return false;
661
662 if (type >= src->num_types)
663 return false;
664
665 if (!src->enabled_types || !src->funcs->set)
666 return false;
667
668 return !!atomic_read(&src->enabled_types[type]);
669 }
670
671 #ifdef __linux__
672 /* XXX: Generic IRQ handling */
amdgpu_irq_mask(struct irq_data * irqd)673 static void amdgpu_irq_mask(struct irq_data *irqd)
674 {
675 /* XXX */
676 }
677
amdgpu_irq_unmask(struct irq_data * irqd)678 static void amdgpu_irq_unmask(struct irq_data *irqd)
679 {
680 /* XXX */
681 }
682
683 /* amdgpu hardware interrupt chip descriptor */
684 static struct irq_chip amdgpu_irq_chip = {
685 .name = "amdgpu-ih",
686 .irq_mask = amdgpu_irq_mask,
687 .irq_unmask = amdgpu_irq_unmask,
688 };
689 #endif
690
691 #ifdef __linux__
692 /**
693 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
694 *
695 * @d: amdgpu IRQ domain pointer (unused)
696 * @irq: virtual IRQ number
697 * @hwirq: hardware irq number
698 *
699 * Current implementation assigns simple interrupt handler to the given virtual
700 * IRQ.
701 *
702 * Returns:
703 * 0 on success or error code otherwise
704 */
amdgpu_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)705 static int amdgpu_irqdomain_map(struct irq_domain *d,
706 unsigned int irq, irq_hw_number_t hwirq)
707 {
708 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
709 return -EPERM;
710
711 irq_set_chip_and_handler(irq,
712 &amdgpu_irq_chip, handle_simple_irq);
713 return 0;
714 }
715
716 /* Implementation of methods for amdgpu IRQ domain */
717 static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
718 .map = amdgpu_irqdomain_map,
719 };
720 #endif
721
722 /**
723 * amdgpu_irq_add_domain - create a linear IRQ domain
724 *
725 * @adev: amdgpu device pointer
726 *
727 * Creates an IRQ domain for GPU interrupt sources
728 * that may be driven by another driver (e.g., ACP).
729 *
730 * Returns:
731 * 0 on success or error code otherwise
732 */
amdgpu_irq_add_domain(struct amdgpu_device * adev)733 int amdgpu_irq_add_domain(struct amdgpu_device *adev)
734 {
735 #ifdef __linux__
736 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
737 &amdgpu_hw_irqdomain_ops, adev);
738 if (!adev->irq.domain) {
739 DRM_ERROR("GPU irq add domain failed\n");
740 return -ENODEV;
741 }
742 #endif
743
744 return 0;
745 }
746
747 /**
748 * amdgpu_irq_remove_domain - remove the IRQ domain
749 *
750 * @adev: amdgpu device pointer
751 *
752 * Removes the IRQ domain for GPU interrupt sources
753 * that may be driven by another driver (e.g., ACP).
754 */
amdgpu_irq_remove_domain(struct amdgpu_device * adev)755 void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
756 {
757 STUB();
758 #if 0
759 if (adev->irq.domain) {
760 irq_domain_remove(adev->irq.domain);
761 adev->irq.domain = NULL;
762 }
763 #endif
764 }
765
766 /**
767 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
768 *
769 * @adev: amdgpu device pointer
770 * @src_id: IH source id
771 *
772 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
773 * Use this for components that generate a GPU interrupt, but are driven
774 * by a different driver (e.g., ACP).
775 *
776 * Returns:
777 * Linux IRQ
778 */
amdgpu_irq_create_mapping(struct amdgpu_device * adev,unsigned int src_id)779 unsigned int amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned int src_id)
780 {
781 STUB();
782 return 0;
783 #if 0
784 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
785
786 return adev->irq.virq[src_id];
787 #endif
788 }
789