1 /*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21
22 #include "amdgpu.h"
23 #include "amdgpu_ras.h"
24
amdgpu_nbio_ras_sw_init(struct amdgpu_device * adev)25 int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev)
26 {
27 int err;
28 struct amdgpu_nbio_ras *ras;
29
30 if (!adev->nbio.ras)
31 return 0;
32
33 ras = adev->nbio.ras;
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
35 if (err) {
36 dev_err(adev->dev, "Failed to register pcie_bif ras block!\n");
37 return err;
38 }
39
40 strlcpy(ras->ras_block.ras_comm.name, "pcie_bif",
41 sizeof(ras->ras_block.ras_comm.name));
42 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF;
43 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
44 adev->nbio.ras_if = &ras->ras_block.ras_comm;
45
46 return 0;
47 }
48
amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device * adev)49 u64 amdgpu_nbio_get_pcie_replay_count(struct amdgpu_device *adev)
50 {
51 if (adev->nbio.funcs && adev->nbio.funcs->get_pcie_replay_count)
52 return adev->nbio.funcs->get_pcie_replay_count(adev);
53
54 return 0;
55 }
56
amdgpu_nbio_get_pcie_usage(struct amdgpu_device * adev,uint64_t * count0,uint64_t * count1)57 void amdgpu_nbio_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
58 uint64_t *count1)
59 {
60 if (adev->nbio.funcs->get_pcie_usage)
61 adev->nbio.funcs->get_pcie_usage(adev, count0, count1);
62
63 }
64
amdgpu_nbio_ras_late_init(struct amdgpu_device * adev,struct ras_common_if * ras_block)65 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block)
66 {
67 int r;
68 r = amdgpu_ras_block_late_init(adev, ras_block);
69 if (r)
70 return r;
71
72 if (amdgpu_ras_is_supported(adev, ras_block->block)) {
73 r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
74 if (r)
75 goto late_fini;
76 r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
77 if (r)
78 goto late_fini;
79 }
80
81 return 0;
82 late_fini:
83 amdgpu_ras_block_late_fini(adev, ras_block);
84 return r;
85 }
86