1 /* $NetBSD: amdgpu_ttm.c,v 1.12 2022/07/29 12:43:15 riastradh Exp $ */
2
3 /*
4 * Copyright 2009 Jerome Glisse.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
25 * of the Software.
26 *
27 */
28 /*
29 * Authors:
30 * Jerome Glisse <glisse@freedesktop.org>
31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 * Dave Airlie
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ttm.c,v 1.12 2022/07/29 12:43:15 riastradh Exp $");
37
38 #include <linux/dma-mapping.h>
39 #include <linux/iommu.h>
40 #include <linux/hmm.h>
41 #include <linux/pagemap.h>
42 #include <linux/sched/task.h>
43 #include <linux/sched/mm.h>
44 #include <linux/seq_file.h>
45 #include <linux/slab.h>
46 #include <linux/swap.h>
47 #include <linux/swiotlb.h>
48 #include <linux/dma-buf.h>
49 #include <linux/sizes.h>
50
51 #include <drm/ttm/ttm_bo_api.h>
52 #include <drm/ttm/ttm_bo_driver.h>
53 #include <drm/ttm/ttm_placement.h>
54 #include <drm/ttm/ttm_module.h>
55 #include <drm/ttm/ttm_page_alloc.h>
56
57 #include <drm/drm_debugfs.h>
58 #include <drm/amdgpu_drm.h>
59
60 #include "amdgpu.h"
61 #include "amdgpu_object.h"
62 #include "amdgpu_trace.h"
63 #include "amdgpu_amdkfd.h"
64 #include "amdgpu_sdma.h"
65 #include "amdgpu_ras.h"
66 #include "bif/bif_4_1_d.h"
67
68 #include <linux/nbsd-namespace.h>
69
70 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
71 struct ttm_mem_reg *mem, unsigned num_pages,
72 uint64_t offset, unsigned window,
73 struct amdgpu_ring *ring,
74 uint64_t *addr);
75
76 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
77 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
78
amdgpu_invalidate_caches(struct ttm_bo_device * bdev,uint32_t flags)79 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
80 {
81 return 0;
82 }
83
84 /**
85 * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
86 * memory request.
87 *
88 * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
89 * @type: The type of memory requested
90 * @man: The memory type manager for each domain
91 *
92 * This is called by ttm_bo_init_mm() when a buffer object is being
93 * initialized.
94 */
amdgpu_init_mem_type(struct ttm_bo_device * bdev,uint32_t type,struct ttm_mem_type_manager * man)95 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
96 struct ttm_mem_type_manager *man)
97 {
98 struct amdgpu_device *adev;
99
100 adev = amdgpu_ttm_adev(bdev);
101
102 switch (type) {
103 case TTM_PL_SYSTEM:
104 /* System memory */
105 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
106 man->available_caching = TTM_PL_MASK_CACHING;
107 man->default_caching = TTM_PL_FLAG_CACHED;
108 break;
109 case TTM_PL_TT:
110 /* GTT memory */
111 man->func = &amdgpu_gtt_mgr_func;
112 man->gpu_offset = adev->gmc.gart_start;
113 man->available_caching = TTM_PL_MASK_CACHING;
114 man->default_caching = TTM_PL_FLAG_CACHED;
115 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
116 break;
117 case TTM_PL_VRAM:
118 /* "On-card" video ram */
119 man->func = &amdgpu_vram_mgr_func;
120 man->gpu_offset = adev->gmc.vram_start;
121 man->flags = TTM_MEMTYPE_FLAG_FIXED |
122 TTM_MEMTYPE_FLAG_MAPPABLE;
123 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
124 man->default_caching = TTM_PL_FLAG_WC;
125 break;
126 case AMDGPU_PL_GDS:
127 case AMDGPU_PL_GWS:
128 case AMDGPU_PL_OA:
129 /* On-chip GDS memory*/
130 man->func = &ttm_bo_manager_func;
131 man->gpu_offset = 0;
132 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
133 man->available_caching = TTM_PL_FLAG_UNCACHED;
134 man->default_caching = TTM_PL_FLAG_UNCACHED;
135 break;
136 default:
137 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
138 return -EINVAL;
139 }
140 return 0;
141 }
142
143 /**
144 * amdgpu_evict_flags - Compute placement flags
145 *
146 * @bo: The buffer object to evict
147 * @placement: Possible destination(s) for evicted BO
148 *
149 * Fill in placement data when ttm_bo_evict() is called
150 */
amdgpu_evict_flags(struct ttm_buffer_object * bo,struct ttm_placement * placement)151 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
152 struct ttm_placement *placement)
153 {
154 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
155 struct amdgpu_bo *abo;
156 static const struct ttm_place placements = {
157 .fpfn = 0,
158 .lpfn = 0,
159 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
160 };
161
162 /* Don't handle scatter gather BOs */
163 if (bo->type == ttm_bo_type_sg) {
164 placement->num_placement = 0;
165 placement->num_busy_placement = 0;
166 return;
167 }
168
169 /* Object isn't an AMDGPU object so ignore */
170 if (!amdgpu_bo_is_amdgpu_bo(bo)) {
171 placement->placement = &placements;
172 placement->busy_placement = &placements;
173 placement->num_placement = 1;
174 placement->num_busy_placement = 1;
175 return;
176 }
177
178 abo = ttm_to_amdgpu_bo(bo);
179 switch (bo->mem.mem_type) {
180 case AMDGPU_PL_GDS:
181 case AMDGPU_PL_GWS:
182 case AMDGPU_PL_OA:
183 placement->num_placement = 0;
184 placement->num_busy_placement = 0;
185 return;
186
187 case TTM_PL_VRAM:
188 if (!adev->mman.buffer_funcs_enabled) {
189 /* Move to system memory */
190 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
191 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
192 !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
193 amdgpu_bo_in_cpu_visible_vram(abo)) {
194
195 /* Try evicting to the CPU inaccessible part of VRAM
196 * first, but only set GTT as busy placement, so this
197 * BO will be evicted to GTT rather than causing other
198 * BOs to be evicted from VRAM
199 */
200 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
201 AMDGPU_GEM_DOMAIN_GTT);
202 abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
203 abo->placements[0].lpfn = 0;
204 abo->placement.busy_placement = &abo->placements[1];
205 abo->placement.num_busy_placement = 1;
206 } else {
207 /* Move to GTT memory */
208 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
209 }
210 break;
211 case TTM_PL_TT:
212 default:
213 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
214 break;
215 }
216 *placement = abo->placement;
217 }
218
219 /**
220 * amdgpu_verify_access - Verify access for a mmap call
221 *
222 * @bo: The buffer object to map
223 * @filp: The file pointer from the process performing the mmap
224 *
225 * This is called by ttm_bo_mmap() to verify whether a process
226 * has the right to mmap a BO to their process space.
227 */
amdgpu_verify_access(struct ttm_buffer_object * bo,struct file * filp)228 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
229 {
230 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
231
232 /*
233 * Don't verify access for KFD BOs. They don't have a GEM
234 * object associated with them.
235 */
236 if (abo->kfd_bo)
237 return 0;
238
239 if (amdgpu_ttm_tt_get_usermm(bo->ttm))
240 return -EPERM;
241 #ifdef __NetBSD__
242 return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
243 filp->f_data);
244 #else
245 return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
246 filp->private_data);
247 #endif
248 }
249
250 /**
251 * amdgpu_move_null - Register memory for a buffer object
252 *
253 * @bo: The bo to assign the memory to
254 * @new_mem: The memory to be assigned.
255 *
256 * Assign the memory from new_mem to the memory of the buffer object bo.
257 */
amdgpu_move_null(struct ttm_buffer_object * bo,struct ttm_mem_reg * new_mem)258 static void amdgpu_move_null(struct ttm_buffer_object *bo,
259 struct ttm_mem_reg *new_mem)
260 {
261 struct ttm_mem_reg *old_mem = &bo->mem;
262
263 BUG_ON(old_mem->mm_node != NULL);
264 *old_mem = *new_mem;
265 new_mem->mm_node = NULL;
266 }
267
268 /**
269 * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
270 *
271 * @bo: The bo to assign the memory to.
272 * @mm_node: Memory manager node for drm allocator.
273 * @mem: The region where the bo resides.
274 *
275 */
amdgpu_mm_node_addr(struct ttm_buffer_object * bo,struct drm_mm_node * mm_node,struct ttm_mem_reg * mem)276 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
277 struct drm_mm_node *mm_node,
278 struct ttm_mem_reg *mem)
279 {
280 uint64_t addr = 0;
281
282 if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
283 addr = mm_node->start << PAGE_SHIFT;
284 addr += bo->bdev->man[mem->mem_type].gpu_offset;
285 }
286 return addr;
287 }
288
289 /**
290 * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
291 * @offset. It also modifies the offset to be within the drm_mm_node returned
292 *
293 * @mem: The region where the bo resides.
294 * @offset: The offset that drm_mm_node is used for finding.
295 *
296 */
amdgpu_find_mm_node(struct ttm_mem_reg * mem,unsigned long * offset)297 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
298 unsigned long *offset)
299 {
300 struct drm_mm_node *mm_node = mem->mm_node;
301
302 while (*offset >= (mm_node->size << PAGE_SHIFT)) {
303 *offset -= (mm_node->size << PAGE_SHIFT);
304 ++mm_node;
305 }
306 return mm_node;
307 }
308
309 /**
310 * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
311 *
312 * The function copies @size bytes from {src->mem + src->offset} to
313 * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
314 * move and different for a BO to BO copy.
315 *
316 * @f: Returns the last fence if multiple jobs are submitted.
317 */
amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device * adev,struct amdgpu_copy_mem * src,struct amdgpu_copy_mem * dst,uint64_t size,struct dma_resv * resv,struct dma_fence ** f)318 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
319 struct amdgpu_copy_mem *src,
320 struct amdgpu_copy_mem *dst,
321 uint64_t size,
322 struct dma_resv *resv,
323 struct dma_fence **f)
324 {
325 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
326 struct drm_mm_node *src_mm, *dst_mm;
327 uint64_t src_node_start, dst_node_start, src_node_size,
328 dst_node_size, src_page_offset, dst_page_offset;
329 struct dma_fence *fence = NULL;
330 int r = 0;
331 const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
332 AMDGPU_GPU_PAGE_SIZE);
333
334 if (!adev->mman.buffer_funcs_enabled) {
335 DRM_ERROR("Trying to move memory with ring turned off.\n");
336 return -EINVAL;
337 }
338
339 src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
340 src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
341 src->offset;
342 src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
343 src_page_offset = src_node_start & (PAGE_SIZE - 1);
344
345 dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
346 dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
347 dst->offset;
348 dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
349 dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
350
351 mutex_lock(&adev->mman.gtt_window_lock);
352
353 while (size) {
354 unsigned long cur_size;
355 uint64_t from = src_node_start, to = dst_node_start;
356 struct dma_fence *next;
357
358 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
359 * begins at an offset, then adjust the size accordingly
360 */
361 cur_size = min3(min(src_node_size, dst_node_size), size,
362 GTT_MAX_BYTES);
363 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
364 cur_size + dst_page_offset > GTT_MAX_BYTES)
365 cur_size -= max(src_page_offset, dst_page_offset);
366
367 /* Map only what needs to be accessed. Map src to window 0 and
368 * dst to window 1
369 */
370 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
371 r = amdgpu_map_buffer(src->bo, src->mem,
372 PFN_UP(cur_size + src_page_offset),
373 src_node_start, 0, ring,
374 &from);
375 if (r)
376 goto error;
377 /* Adjust the offset because amdgpu_map_buffer returns
378 * start of mapped page
379 */
380 from += src_page_offset;
381 }
382
383 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
384 r = amdgpu_map_buffer(dst->bo, dst->mem,
385 PFN_UP(cur_size + dst_page_offset),
386 dst_node_start, 1, ring,
387 &to);
388 if (r)
389 goto error;
390 to += dst_page_offset;
391 }
392
393 r = amdgpu_copy_buffer(ring, from, to, cur_size,
394 resv, &next, false, true);
395 if (r)
396 goto error;
397
398 dma_fence_put(fence);
399 fence = next;
400
401 size -= cur_size;
402 if (!size)
403 break;
404
405 src_node_size -= cur_size;
406 if (!src_node_size) {
407 src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
408 src->mem);
409 src_node_size = (src_mm->size << PAGE_SHIFT);
410 src_page_offset = 0;
411 } else {
412 src_node_start += cur_size;
413 src_page_offset = src_node_start & (PAGE_SIZE - 1);
414 }
415 dst_node_size -= cur_size;
416 if (!dst_node_size) {
417 dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
418 dst->mem);
419 dst_node_size = (dst_mm->size << PAGE_SHIFT);
420 dst_page_offset = 0;
421 } else {
422 dst_node_start += cur_size;
423 dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
424 }
425 }
426 error:
427 mutex_unlock(&adev->mman.gtt_window_lock);
428 if (f)
429 *f = dma_fence_get(fence);
430 dma_fence_put(fence);
431 return r;
432 }
433
434 /**
435 * amdgpu_move_blit - Copy an entire buffer to another buffer
436 *
437 * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
438 * help move buffers to and from VRAM.
439 */
amdgpu_move_blit(struct ttm_buffer_object * bo,bool evict,bool no_wait_gpu,struct ttm_mem_reg * new_mem,struct ttm_mem_reg * old_mem)440 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
441 bool evict, bool no_wait_gpu,
442 struct ttm_mem_reg *new_mem,
443 struct ttm_mem_reg *old_mem)
444 {
445 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
446 struct amdgpu_copy_mem src, dst;
447 struct dma_fence *fence = NULL;
448 int r;
449
450 src.bo = bo;
451 dst.bo = bo;
452 src.mem = old_mem;
453 dst.mem = new_mem;
454 src.offset = 0;
455 dst.offset = 0;
456
457 r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
458 new_mem->num_pages << PAGE_SHIFT,
459 bo->base.resv, &fence);
460 if (r)
461 goto error;
462
463 /* clear the space being freed */
464 if (old_mem->mem_type == TTM_PL_VRAM &&
465 (ttm_to_amdgpu_bo(bo)->flags &
466 AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
467 struct dma_fence *wipe_fence = NULL;
468
469 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
470 NULL, &wipe_fence);
471 if (r) {
472 goto error;
473 } else if (wipe_fence) {
474 dma_fence_put(fence);
475 fence = wipe_fence;
476 }
477 }
478
479 /* Always block for VM page tables before committing the new location */
480 if (bo->type == ttm_bo_type_kernel)
481 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
482 else
483 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
484 dma_fence_put(fence);
485 return r;
486
487 error:
488 if (fence)
489 dma_fence_wait(fence, false);
490 dma_fence_put(fence);
491 return r;
492 }
493
494 /**
495 * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
496 *
497 * Called by amdgpu_bo_move().
498 */
amdgpu_move_vram_ram(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_mem_reg * new_mem)499 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
500 struct ttm_operation_ctx *ctx,
501 struct ttm_mem_reg *new_mem)
502 {
503 struct ttm_mem_reg *old_mem = &bo->mem;
504 struct ttm_mem_reg tmp_mem;
505 struct ttm_place placements;
506 struct ttm_placement placement;
507 int r;
508
509 /* create space/pages for new_mem in GTT space */
510 tmp_mem = *new_mem;
511 tmp_mem.mm_node = NULL;
512 placement.num_placement = 1;
513 placement.placement = &placements;
514 placement.num_busy_placement = 1;
515 placement.busy_placement = &placements;
516 placements.fpfn = 0;
517 placements.lpfn = 0;
518 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
519 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
520 if (unlikely(r)) {
521 pr_err("Failed to find GTT space for blit from VRAM\n");
522 return r;
523 }
524
525 /* set caching flags */
526 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
527 if (unlikely(r)) {
528 goto out_cleanup;
529 }
530
531 /* Bind the memory to the GTT space */
532 r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
533 if (unlikely(r)) {
534 goto out_cleanup;
535 }
536
537 /* blit VRAM to GTT */
538 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
539 if (unlikely(r)) {
540 goto out_cleanup;
541 }
542
543 /* move BO (in tmp_mem) to new_mem */
544 r = ttm_bo_move_ttm(bo, ctx, new_mem);
545 out_cleanup:
546 ttm_bo_mem_put(bo, &tmp_mem);
547 return r;
548 }
549
550 /**
551 * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
552 *
553 * Called by amdgpu_bo_move().
554 */
amdgpu_move_ram_vram(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_mem_reg * new_mem)555 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
556 struct ttm_operation_ctx *ctx,
557 struct ttm_mem_reg *new_mem)
558 {
559 struct ttm_mem_reg *old_mem = &bo->mem;
560 struct ttm_mem_reg tmp_mem;
561 struct ttm_placement placement;
562 struct ttm_place placements;
563 int r;
564
565 /* make space in GTT for old_mem buffer */
566 tmp_mem = *new_mem;
567 tmp_mem.mm_node = NULL;
568 placement.num_placement = 1;
569 placement.placement = &placements;
570 placement.num_busy_placement = 1;
571 placement.busy_placement = &placements;
572 placements.fpfn = 0;
573 placements.lpfn = 0;
574 placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
575 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
576 if (unlikely(r)) {
577 pr_err("Failed to find GTT space for blit to VRAM\n");
578 return r;
579 }
580
581 /* move/bind old memory to GTT space */
582 r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
583 if (unlikely(r)) {
584 goto out_cleanup;
585 }
586
587 /* copy to VRAM */
588 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
589 if (unlikely(r)) {
590 goto out_cleanup;
591 }
592 out_cleanup:
593 ttm_bo_mem_put(bo, &tmp_mem);
594 return r;
595 }
596
597 /**
598 * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
599 *
600 * Called by amdgpu_bo_move()
601 */
amdgpu_mem_visible(struct amdgpu_device * adev,struct ttm_mem_reg * mem)602 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
603 struct ttm_mem_reg *mem)
604 {
605 struct drm_mm_node *nodes = mem->mm_node;
606
607 if (mem->mem_type == TTM_PL_SYSTEM ||
608 mem->mem_type == TTM_PL_TT)
609 return true;
610 if (mem->mem_type != TTM_PL_VRAM)
611 return false;
612
613 /* ttm_mem_reg_ioremap only supports contiguous memory */
614 if (nodes->size != mem->num_pages)
615 return false;
616
617 return ((nodes->start + nodes->size) << PAGE_SHIFT)
618 <= adev->gmc.visible_vram_size;
619 }
620
621 /**
622 * amdgpu_bo_move - Move a buffer object to a new memory location
623 *
624 * Called by ttm_bo_handle_move_mem()
625 */
amdgpu_bo_move(struct ttm_buffer_object * bo,bool evict,struct ttm_operation_ctx * ctx,struct ttm_mem_reg * new_mem)626 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
627 struct ttm_operation_ctx *ctx,
628 struct ttm_mem_reg *new_mem)
629 {
630 struct amdgpu_device *adev;
631 struct amdgpu_bo *abo;
632 struct ttm_mem_reg *old_mem = &bo->mem;
633 int r;
634
635 /* Can't move a pinned BO */
636 abo = ttm_to_amdgpu_bo(bo);
637 if (WARN_ON_ONCE(abo->pin_count > 0))
638 return -EINVAL;
639
640 adev = amdgpu_ttm_adev(bo->bdev);
641
642 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
643 amdgpu_move_null(bo, new_mem);
644 return 0;
645 }
646 if ((old_mem->mem_type == TTM_PL_TT &&
647 new_mem->mem_type == TTM_PL_SYSTEM) ||
648 (old_mem->mem_type == TTM_PL_SYSTEM &&
649 new_mem->mem_type == TTM_PL_TT)) {
650 /* bind is enough */
651 amdgpu_move_null(bo, new_mem);
652 return 0;
653 }
654 if (old_mem->mem_type == AMDGPU_PL_GDS ||
655 old_mem->mem_type == AMDGPU_PL_GWS ||
656 old_mem->mem_type == AMDGPU_PL_OA ||
657 new_mem->mem_type == AMDGPU_PL_GDS ||
658 new_mem->mem_type == AMDGPU_PL_GWS ||
659 new_mem->mem_type == AMDGPU_PL_OA) {
660 /* Nothing to save here */
661 amdgpu_move_null(bo, new_mem);
662 return 0;
663 }
664
665 if (!adev->mman.buffer_funcs_enabled) {
666 r = -ENODEV;
667 goto memcpy;
668 }
669
670 if (old_mem->mem_type == TTM_PL_VRAM &&
671 new_mem->mem_type == TTM_PL_SYSTEM) {
672 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
673 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
674 new_mem->mem_type == TTM_PL_VRAM) {
675 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
676 } else {
677 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
678 new_mem, old_mem);
679 }
680
681 if (r) {
682 memcpy:
683 /* Check that all memory is CPU accessible */
684 if (!amdgpu_mem_visible(adev, old_mem) ||
685 !amdgpu_mem_visible(adev, new_mem)) {
686 pr_err("Move buffer fallback to memcpy unavailable\n");
687 return r;
688 }
689
690 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
691 if (r)
692 return r;
693 }
694
695 if (bo->type == ttm_bo_type_device &&
696 new_mem->mem_type == TTM_PL_VRAM &&
697 old_mem->mem_type != TTM_PL_VRAM) {
698 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
699 * accesses the BO after it's moved.
700 */
701 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
702 }
703
704 /* update statistics */
705 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
706 return 0;
707 }
708
709 /**
710 * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
711 *
712 * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
713 */
amdgpu_ttm_io_mem_reserve(struct ttm_bo_device * bdev,struct ttm_mem_reg * mem)714 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
715 {
716 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
717 struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
718 struct drm_mm_node *mm_node = mem->mm_node;
719
720 mem->bus.addr = NULL;
721 mem->bus.offset = 0;
722 mem->bus.size = mem->num_pages << PAGE_SHIFT;
723 mem->bus.base = 0;
724 mem->bus.is_iomem = false;
725 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
726 return -EINVAL;
727 switch (mem->mem_type) {
728 case TTM_PL_SYSTEM:
729 /* system memory */
730 return 0;
731 case TTM_PL_TT:
732 break;
733 case TTM_PL_VRAM:
734 mem->bus.offset = mem->start << PAGE_SHIFT;
735 /* check if it's visible */
736 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
737 return -EINVAL;
738 /* Only physically contiguous buffers apply. In a contiguous
739 * buffer, size of the first mm_node would match the number of
740 * pages in ttm_mem_reg.
741 */
742 if (adev->mman.aper_base_kaddr &&
743 (mm_node->size == mem->num_pages))
744 mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
745 mem->bus.offset;
746
747 mem->bus.base = adev->gmc.aper_base;
748 mem->bus.is_iomem = true;
749 break;
750 default:
751 return -EINVAL;
752 }
753 return 0;
754 }
755
amdgpu_ttm_io_mem_free(struct ttm_bo_device * bdev,struct ttm_mem_reg * mem)756 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
757 {
758 }
759
amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object * bo,unsigned long page_offset)760 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
761 unsigned long page_offset)
762 {
763 struct drm_mm_node *mm;
764 unsigned long offset = (page_offset << PAGE_SHIFT);
765
766 mm = amdgpu_find_mm_node(&bo->mem, &offset);
767 #ifdef __NetBSD__
768 /*
769 * vm_prot and flags are encoded in the pmap cookie, but we
770 * then discard them; the caller will reapply them as
771 * appropriate before it gets to pmap_enter.
772 *
773 * XXX What if the flags determine not just extra bits in the
774 * cookie, but the address itself, in case different mapping
775 * types (like prefetchable) are exposed through different
776 * ranges instead of different page table entry bit?
777 */
778 const paddr_t cookie = bus_space_mmap(bo->bdev->memt, bo->mem.bus.base,
779 (mm->start + page_offset) << PAGE_SHIFT, /*vm_prot*/0, /*flags*/0);
780 return pmap_phys_address(cookie) >> PAGE_SHIFT;
781 #else
782 return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
783 (offset >> PAGE_SHIFT);
784 #endif
785 }
786
787 /*
788 * TTM backend functions.
789 */
790 struct amdgpu_ttm_tt {
791 struct ttm_dma_tt ttm;
792 struct drm_gem_object *gobj;
793 u64 offset;
794 uint64_t userptr;
795 #ifdef __NetBSD__
796 struct proc *usertask;
797 #else
798 struct task_struct *usertask;
799 #endif
800 uint32_t userflags;
801 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
802 struct hmm_range *range;
803 #endif
804 };
805
806 #ifdef CONFIG_DRM_AMDGPU_USERPTR
807 /* flags used by HMM internal, not related to CPU/GPU PTE flags */
808 static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
809 (1 << 0), /* HMM_PFN_VALID */
810 (1 << 1), /* HMM_PFN_WRITE */
811 0 /* HMM_PFN_DEVICE_PRIVATE */
812 };
813
814 static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
815 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
816 0, /* HMM_PFN_NONE */
817 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
818 };
819
820 /**
821 * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
822 * memory and start HMM tracking CPU page table update
823 *
824 * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
825 * once afterwards to stop HMM tracking
826 */
amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo * bo,struct page ** pages)827 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
828 {
829 struct ttm_tt *ttm = bo->tbo.ttm;
830 struct amdgpu_ttm_tt *gtt = (void *)ttm;
831 unsigned long start = gtt->userptr;
832 struct vm_area_struct *vma;
833 struct hmm_range *range;
834 unsigned long timeout;
835 struct mm_struct *mm;
836 unsigned long i;
837 int r = 0;
838
839 mm = bo->notifier.mm;
840 if (unlikely(!mm)) {
841 DRM_DEBUG_DRIVER("BO is not registered?\n");
842 return -EFAULT;
843 }
844
845 /* Another get_user_pages is running at the same time?? */
846 if (WARN_ON(gtt->range))
847 return -EFAULT;
848
849 if (!mmget_not_zero(mm)) /* Happens during process shutdown */
850 return -ESRCH;
851
852 range = kzalloc(sizeof(*range), GFP_KERNEL);
853 if (unlikely(!range)) {
854 r = -ENOMEM;
855 goto out;
856 }
857 range->notifier = &bo->notifier;
858 range->flags = hmm_range_flags;
859 range->values = hmm_range_values;
860 range->pfn_shift = PAGE_SHIFT;
861 range->start = bo->notifier.interval_tree.start;
862 range->end = bo->notifier.interval_tree.last + 1;
863 range->default_flags = hmm_range_flags[HMM_PFN_VALID];
864 if (!amdgpu_ttm_tt_is_readonly(ttm))
865 range->default_flags |= range->flags[HMM_PFN_WRITE];
866
867 range->pfns = kvmalloc_array(ttm->num_pages, sizeof(*range->pfns),
868 GFP_KERNEL);
869 if (unlikely(!range->pfns)) {
870 r = -ENOMEM;
871 goto out_free_ranges;
872 }
873
874 down_read(&mm->mmap_sem);
875 vma = find_vma(mm, start);
876 if (unlikely(!vma || start < vma->vm_start)) {
877 r = -EFAULT;
878 goto out_unlock;
879 }
880 if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
881 vma->vm_file)) {
882 r = -EPERM;
883 goto out_unlock;
884 }
885 up_read(&mm->mmap_sem);
886 timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
887
888 retry:
889 range->notifier_seq = mmu_interval_read_begin(&bo->notifier);
890
891 down_read(&mm->mmap_sem);
892 r = hmm_range_fault(range, 0);
893 up_read(&mm->mmap_sem);
894 if (unlikely(r <= 0)) {
895 /*
896 * FIXME: This timeout should encompass the retry from
897 * mmu_interval_read_retry() as well.
898 */
899 if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout))
900 goto retry;
901 goto out_free_pfns;
902 }
903
904 for (i = 0; i < ttm->num_pages; i++) {
905 /* FIXME: The pages cannot be touched outside the notifier_lock */
906 pages[i] = hmm_device_entry_to_page(range, range->pfns[i]);
907 if (unlikely(!pages[i])) {
908 pr_err("Page fault failed for pfn[%lu] = 0x%llx\n",
909 i, range->pfns[i]);
910 r = -ENOMEM;
911
912 goto out_free_pfns;
913 }
914 }
915
916 gtt->range = range;
917 mmput(mm);
918
919 return 0;
920
921 out_unlock:
922 up_read(&mm->mmap_sem);
923 out_free_pfns:
924 kvfree(range->pfns);
925 out_free_ranges:
926 kfree(range);
927 out:
928 mmput(mm);
929 return r;
930 }
931
932 /**
933 * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
934 * Check if the pages backing this ttm range have been invalidated
935 *
936 * Returns: true if pages are still valid
937 */
amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt * ttm)938 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
939 {
940 struct amdgpu_ttm_tt *gtt = (void *)ttm;
941 bool r = false;
942
943 if (!gtt || !gtt->userptr)
944 return false;
945
946 DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%lx\n",
947 gtt->userptr, ttm->num_pages);
948
949 WARN_ONCE(!gtt->range || !gtt->range->pfns,
950 "No user pages to check\n");
951
952 if (gtt->range) {
953 /*
954 * FIXME: Must always hold notifier_lock for this, and must
955 * not ignore the return code.
956 */
957 r = mmu_interval_read_retry(gtt->range->notifier,
958 gtt->range->notifier_seq);
959 kvfree(gtt->range->pfns);
960 kfree(gtt->range);
961 gtt->range = NULL;
962 }
963
964 return !r;
965 }
966 #endif
967
968 /**
969 * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
970 *
971 * Called by amdgpu_cs_list_validate(). This creates the page list
972 * that backs user memory and will ultimately be mapped into the device
973 * address space.
974 */
amdgpu_ttm_tt_set_user_pages(struct ttm_tt * ttm,struct page ** pages)975 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
976 {
977 unsigned long i;
978
979 for (i = 0; i < ttm->num_pages; ++i)
980 ttm->pages[i] = pages ? pages[i] : NULL;
981 }
982
983 /**
984 * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
985 *
986 * Called by amdgpu_ttm_backend_bind()
987 **/
amdgpu_ttm_tt_pin_userptr(struct ttm_tt * ttm)988 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
989 {
990 #ifdef __NetBSD__ /* XXX amdgpu userptr */
991 return -ENODEV;
992 #else
993 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
994 struct amdgpu_ttm_tt *gtt = (void *)ttm;
995 unsigned nents;
996 int r;
997
998 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
999 enum dma_data_direction direction = write ?
1000 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1001
1002 /* Allocate an SG array and squash pages into it */
1003 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
1004 ttm->num_pages << PAGE_SHIFT,
1005 GFP_KERNEL);
1006 if (r)
1007 goto release_sg;
1008
1009 /* Map SG to device */
1010 r = -ENOMEM;
1011 nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1012 if (nents != ttm->sg->nents)
1013 goto release_sg;
1014
1015 /* convert SG to linear array of pages and dma addresses */
1016 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1017 gtt->ttm.dma_address, ttm->num_pages);
1018
1019 return 0;
1020
1021 release_sg:
1022 kfree(ttm->sg);
1023 return r;
1024 #endif
1025 }
1026
1027 /**
1028 * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
1029 */
amdgpu_ttm_tt_unpin_userptr(struct ttm_tt * ttm)1030 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
1031 {
1032 #ifndef __NetBSD__ /* XXX amdgpu userptr */
1033 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1034 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1035
1036 int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1037 enum dma_data_direction direction = write ?
1038 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
1039
1040 /* double check that we don't free the table twice */
1041 if (!ttm->sg->sgl)
1042 return;
1043
1044 /* unmap the pages mapped to the device */
1045 dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
1046
1047 sg_free_table(ttm->sg);
1048
1049 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
1050 if (gtt->range) {
1051 unsigned long i;
1052
1053 for (i = 0; i < ttm->num_pages; i++) {
1054 if (ttm->pages[i] !=
1055 hmm_device_entry_to_page(gtt->range,
1056 gtt->range->pfns[i]))
1057 break;
1058 }
1059
1060 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
1061 }
1062 #endif
1063 #endif
1064 }
1065
amdgpu_ttm_gart_bind(struct amdgpu_device * adev,struct ttm_buffer_object * tbo,uint64_t flags)1066 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1067 struct ttm_buffer_object *tbo,
1068 uint64_t flags)
1069 {
1070 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1071 struct ttm_tt *ttm = tbo->ttm;
1072 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1073 int r;
1074
1075 if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
1076 uint64_t page_idx = 1;
1077
1078 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1079 ttm->pages, gtt->ttm.dma_address, flags);
1080 if (r)
1081 goto gart_bind_fail;
1082
1083 /* Patch mtype of the second part BO */
1084 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1085 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
1086
1087 r = amdgpu_gart_bind(adev,
1088 gtt->offset + (page_idx << PAGE_SHIFT),
1089 ttm->num_pages - page_idx,
1090 &ttm->pages[page_idx],
1091 &(gtt->ttm.dma_address[page_idx]), flags);
1092 } else {
1093 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1094 ttm->pages, gtt->ttm.dma_address, flags);
1095 }
1096
1097 gart_bind_fail:
1098 if (r)
1099 DRM_ERROR("failed to bind %lu pages at 0x%08"PRIX64"\n",
1100 ttm->num_pages, gtt->offset);
1101
1102 return r;
1103 }
1104
1105 /**
1106 * amdgpu_ttm_backend_bind - Bind GTT memory
1107 *
1108 * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1109 * This handles binding GTT memory to the device address space.
1110 */
amdgpu_ttm_backend_bind(struct ttm_tt * ttm,struct ttm_mem_reg * bo_mem)1111 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1112 struct ttm_mem_reg *bo_mem)
1113 {
1114 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1115 struct amdgpu_ttm_tt *gtt = (void*)ttm;
1116 uint64_t flags;
1117 int r = 0;
1118
1119 if (gtt->userptr) {
1120 r = amdgpu_ttm_tt_pin_userptr(ttm);
1121 if (r) {
1122 DRM_ERROR("failed to pin userptr\n");
1123 return r;
1124 }
1125 }
1126 if (!ttm->num_pages) {
1127 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1128 ttm->num_pages, bo_mem, ttm);
1129 }
1130
1131 if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1132 bo_mem->mem_type == AMDGPU_PL_GWS ||
1133 bo_mem->mem_type == AMDGPU_PL_OA)
1134 return -EINVAL;
1135
1136 if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1137 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1138 return 0;
1139 }
1140
1141 /* compute PTE flags relevant to this BO memory */
1142 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1143
1144 /* bind pages into GART page tables */
1145 gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1146 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1147 ttm->pages, gtt->ttm.dma_address, flags);
1148
1149 if (r)
1150 DRM_ERROR("failed to bind %lu pages at 0x%08"PRIX64"\n",
1151 ttm->num_pages, gtt->offset);
1152 return r;
1153 }
1154
1155 /**
1156 * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1157 */
amdgpu_ttm_alloc_gart(struct ttm_buffer_object * bo)1158 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1159 {
1160 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1161 struct ttm_operation_ctx ctx = { false, false };
1162 struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1163 struct ttm_mem_reg tmp;
1164 struct ttm_placement placement;
1165 struct ttm_place placements;
1166 uint64_t addr, flags;
1167 int r;
1168
1169 if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1170 return 0;
1171
1172 addr = amdgpu_gmc_agp_addr(bo);
1173 if (addr != AMDGPU_BO_INVALID_OFFSET) {
1174 bo->mem.start = addr >> PAGE_SHIFT;
1175 } else {
1176
1177 /* allocate GART space */
1178 tmp = bo->mem;
1179 tmp.mm_node = NULL;
1180 placement.num_placement = 1;
1181 placement.placement = &placements;
1182 placement.num_busy_placement = 1;
1183 placement.busy_placement = &placements;
1184 placements.fpfn = 0;
1185 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1186 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1187 TTM_PL_FLAG_TT;
1188
1189 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1190 if (unlikely(r))
1191 return r;
1192
1193 /* compute PTE flags for this buffer object */
1194 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1195
1196 /* Bind pages */
1197 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1198 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1199 if (unlikely(r)) {
1200 ttm_bo_mem_put(bo, &tmp);
1201 return r;
1202 }
1203
1204 ttm_bo_mem_put(bo, &bo->mem);
1205 bo->mem = tmp;
1206 }
1207
1208 bo->offset = (bo->mem.start << PAGE_SHIFT) +
1209 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1210
1211 return 0;
1212 }
1213
1214 /**
1215 * amdgpu_ttm_recover_gart - Rebind GTT pages
1216 *
1217 * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1218 * rebind GTT pages during a GPU reset.
1219 */
amdgpu_ttm_recover_gart(struct ttm_buffer_object * tbo)1220 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1221 {
1222 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1223 uint64_t flags;
1224 int r;
1225
1226 if (!tbo->ttm)
1227 return 0;
1228
1229 flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1230 r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1231
1232 return r;
1233 }
1234
1235 /**
1236 * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1237 *
1238 * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1239 * ttm_tt_destroy().
1240 */
amdgpu_ttm_backend_unbind(struct ttm_tt * ttm)1241 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1242 {
1243 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1244 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1245 int r;
1246
1247 /* if the pages have userptr pinning then clear that first */
1248 if (gtt->userptr)
1249 amdgpu_ttm_tt_unpin_userptr(ttm);
1250
1251 if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1252 return 0;
1253
1254 /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1255 r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1256 if (r)
1257 DRM_ERROR("failed to unbind %lu pages at 0x%08"PRIX64"\n",
1258 gtt->ttm.ttm.num_pages, gtt->offset);
1259 return r;
1260 }
1261
amdgpu_ttm_backend_destroy(struct ttm_tt * ttm)1262 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1263 {
1264 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1265
1266 #ifndef __NetBSD__ /* XXX amdgpu userptr */
1267 if (gtt->usertask)
1268 put_task_struct(gtt->usertask);
1269 #endif
1270
1271 ttm_dma_tt_fini(>t->ttm);
1272 kfree(gtt);
1273 }
1274
1275 static struct ttm_backend_func amdgpu_backend_func = {
1276 .bind = &amdgpu_ttm_backend_bind,
1277 .unbind = &amdgpu_ttm_backend_unbind,
1278 .destroy = &amdgpu_ttm_backend_destroy,
1279 };
1280
1281 /**
1282 * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1283 *
1284 * @bo: The buffer object to create a GTT ttm_tt object around
1285 *
1286 * Called by ttm_tt_create().
1287 */
amdgpu_ttm_tt_create(struct ttm_buffer_object * bo,uint32_t page_flags)1288 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1289 uint32_t page_flags)
1290 {
1291 struct amdgpu_ttm_tt *gtt;
1292
1293 gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1294 if (gtt == NULL) {
1295 return NULL;
1296 }
1297 gtt->ttm.ttm.func = &amdgpu_backend_func;
1298 gtt->gobj = &bo->base;
1299
1300 /* allocate space for the uninitialized page entries */
1301 if (ttm_sg_tt_init(>t->ttm, bo, page_flags)) {
1302 kfree(gtt);
1303 return NULL;
1304 }
1305 return >t->ttm.ttm;
1306 }
1307
1308 /**
1309 * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1310 *
1311 * Map the pages of a ttm_tt object to an address space visible
1312 * to the underlying device.
1313 */
amdgpu_ttm_tt_populate(struct ttm_tt * ttm,struct ttm_operation_ctx * ctx)1314 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1315 struct ttm_operation_ctx *ctx)
1316 {
1317 #ifndef __NetBSD__
1318 struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1319 #endif
1320 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1321
1322 /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1323 if (gtt && gtt->userptr) {
1324 #ifdef __NetBSD__
1325 ttm->sg = NULL;
1326 #else
1327 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1328 if (!ttm->sg)
1329 return -ENOMEM;
1330 #endif
1331
1332 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1333 ttm->state = tt_unbound;
1334 return 0;
1335 }
1336
1337 if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1338 if (!ttm->sg) {
1339 struct dma_buf_attachment *attach;
1340 struct sg_table *sgt;
1341
1342 attach = gtt->gobj->import_attach;
1343 sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1344 if (IS_ERR(sgt))
1345 return PTR_ERR(sgt);
1346
1347 ttm->sg = sgt;
1348 }
1349
1350 #ifdef __NetBSD__
1351 int r = drm_prime_bus_dmamap_load_sgt(ttm->bdev->dmat,
1352 gtt->ttm.dma_address, ttm->sg);
1353 if (r)
1354 return r;
1355 #else
1356 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1357 gtt->ttm.dma_address,
1358 ttm->num_pages);
1359 #endif
1360 ttm->state = tt_unbound;
1361 return 0;
1362 }
1363
1364 #ifdef __NetBSD__
1365 /* XXX errno NetBSD->Linux */
1366 return ttm_bus_dma_populate(>t->ttm);
1367 #else
1368 #ifdef CONFIG_SWIOTLB
1369 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1370 return ttm_dma_populate(>t->ttm, adev->dev, ctx);
1371 }
1372 #endif
1373
1374 /* fall back to generic helper to populate the page array
1375 * and map them to the device */
1376 return ttm_populate_and_map_pages(adev->dev, >t->ttm, ctx);
1377 #endif
1378 }
1379
1380 /**
1381 * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1382 *
1383 * Unmaps pages of a ttm_tt object from the device address space and
1384 * unpopulates the page array backing it.
1385 */
amdgpu_ttm_tt_unpopulate(struct ttm_tt * ttm)1386 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1387 {
1388 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1389 #ifndef __NetBSD__
1390 struct amdgpu_device *adev;
1391 #endif
1392
1393 if (gtt && gtt->userptr) {
1394 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1395 kfree(ttm->sg);
1396 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1397 return;
1398 }
1399
1400 if (ttm->sg && gtt->gobj->import_attach) {
1401 struct dma_buf_attachment *attach;
1402
1403 attach = gtt->gobj->import_attach;
1404 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1405 ttm->sg = NULL;
1406 return;
1407 }
1408
1409 if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1410 return;
1411
1412 #ifdef __NetBSD__
1413 ttm_bus_dma_unpopulate(>t->ttm);
1414 return;
1415 #else
1416 adev = amdgpu_ttm_adev(ttm->bdev);
1417
1418 #ifdef CONFIG_SWIOTLB
1419 if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1420 ttm_dma_unpopulate(>t->ttm, adev->dev);
1421 return;
1422 }
1423 #endif
1424
1425 /* fall back to generic helper to unmap and unpopulate array */
1426 ttm_unmap_and_unpopulate_pages(adev->dev, >t->ttm);
1427 #endif /* __NetBSD__ */
1428 }
1429
1430 #ifdef __NetBSD__
amdgpu_ttm_tt_swapout(struct ttm_tt * ttm)1431 static void amdgpu_ttm_tt_swapout(struct ttm_tt *ttm)
1432 {
1433 struct amdgpu_ttm_tt *gtt = container_of(ttm, struct amdgpu_ttm_tt,
1434 ttm.ttm);
1435 struct ttm_dma_tt *ttm_dma = >t->ttm;
1436
1437 ttm_bus_dma_swapout(ttm_dma);
1438 }
1439
1440 static const struct uvm_pagerops amdgpu_uvm_ops = {
1441 .pgo_reference = &ttm_bo_uvm_reference,
1442 .pgo_detach = &ttm_bo_uvm_detach,
1443 .pgo_fault = &ttm_bo_uvm_fault,
1444 };
1445 #endif
1446
1447 /**
1448 * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1449 * task
1450 *
1451 * @ttm: The ttm_tt object to bind this userptr object to
1452 * @addr: The address in the current tasks VM space to use
1453 * @flags: Requirements of userptr object.
1454 *
1455 * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1456 * to current task
1457 */
amdgpu_ttm_tt_set_userptr(struct ttm_tt * ttm,uint64_t addr,uint32_t flags)1458 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1459 uint32_t flags)
1460 {
1461 #ifdef __NetBSD__ /* XXX amdgpu userptr */
1462 return -ENODEV;
1463 #else
1464 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1465
1466 if (gtt == NULL)
1467 return -EINVAL;
1468
1469 gtt->userptr = addr;
1470 gtt->userflags = flags;
1471
1472 if (gtt->usertask)
1473 put_task_struct(gtt->usertask);
1474 gtt->usertask = current->group_leader;
1475 get_task_struct(gtt->usertask);
1476
1477 return 0;
1478 #endif
1479 }
1480
1481 /**
1482 * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1483 */
1484 #ifdef __NetBSD__
amdgpu_ttm_tt_get_usermm(struct ttm_tt * ttm)1485 struct vmspace *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1486 #else
1487 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1488 #endif
1489 {
1490 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1491
1492 if (gtt == NULL)
1493 return NULL;
1494
1495 if (gtt->usertask == NULL)
1496 return NULL;
1497
1498 #ifdef __NetBSD__
1499 return gtt->usertask->p_vmspace;
1500 #else
1501 return gtt->usertask->mm;
1502 #endif
1503 }
1504
1505 /**
1506 * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1507 * address range for the current task.
1508 *
1509 */
amdgpu_ttm_tt_affect_userptr(struct ttm_tt * ttm,unsigned long start,unsigned long end)1510 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1511 unsigned long end)
1512 {
1513 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1514 unsigned long size;
1515
1516 if (gtt == NULL || !gtt->userptr)
1517 return false;
1518
1519 /* Return false if no part of the ttm_tt object lies within
1520 * the range
1521 */
1522 size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1523 if (gtt->userptr > end || gtt->userptr + size <= start)
1524 return false;
1525
1526 return true;
1527 }
1528
1529 /**
1530 * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1531 */
amdgpu_ttm_tt_is_userptr(struct ttm_tt * ttm)1532 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1533 {
1534 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1535
1536 if (gtt == NULL || !gtt->userptr)
1537 return false;
1538
1539 return true;
1540 }
1541
1542 /**
1543 * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1544 */
amdgpu_ttm_tt_is_readonly(struct ttm_tt * ttm)1545 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1546 {
1547 struct amdgpu_ttm_tt *gtt = (void *)ttm;
1548
1549 if (gtt == NULL)
1550 return false;
1551
1552 return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1553 }
1554
1555 /**
1556 * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1557 *
1558 * @ttm: The ttm_tt object to compute the flags for
1559 * @mem: The memory registry backing this ttm_tt object
1560 *
1561 * Figure out the flags to use for a VM PDE (Page Directory Entry).
1562 */
amdgpu_ttm_tt_pde_flags(struct ttm_tt * ttm,struct ttm_mem_reg * mem)1563 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1564 {
1565 uint64_t flags = 0;
1566
1567 if (mem && mem->mem_type != TTM_PL_SYSTEM)
1568 flags |= AMDGPU_PTE_VALID;
1569
1570 if (mem && mem->mem_type == TTM_PL_TT) {
1571 flags |= AMDGPU_PTE_SYSTEM;
1572
1573 if (ttm->caching_state == tt_cached)
1574 flags |= AMDGPU_PTE_SNOOPED;
1575 }
1576
1577 return flags;
1578 }
1579
1580 /**
1581 * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1582 *
1583 * @ttm: The ttm_tt object to compute the flags for
1584 * @mem: The memory registry backing this ttm_tt object
1585
1586 * Figure out the flags to use for a VM PTE (Page Table Entry).
1587 */
amdgpu_ttm_tt_pte_flags(struct amdgpu_device * adev,struct ttm_tt * ttm,struct ttm_mem_reg * mem)1588 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1589 struct ttm_mem_reg *mem)
1590 {
1591 uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1592
1593 flags |= adev->gart.gart_pte_flags;
1594 flags |= AMDGPU_PTE_READABLE;
1595
1596 if (!amdgpu_ttm_tt_is_readonly(ttm))
1597 flags |= AMDGPU_PTE_WRITEABLE;
1598
1599 return flags;
1600 }
1601
1602 /**
1603 * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1604 * object.
1605 *
1606 * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1607 * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1608 * it can find space for a new object and by ttm_bo_force_list_clean() which is
1609 * used to clean out a memory space.
1610 */
amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object * bo,const struct ttm_place * place)1611 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1612 const struct ttm_place *place)
1613 {
1614 unsigned long num_pages = bo->mem.num_pages;
1615 struct drm_mm_node *node = bo->mem.mm_node;
1616 struct dma_resv_list *flist;
1617 struct dma_fence *f;
1618 int i;
1619
1620 if (bo->type == ttm_bo_type_kernel &&
1621 !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1622 return false;
1623
1624 /* If bo is a KFD BO, check if the bo belongs to the current process.
1625 * If true, then return false as any KFD process needs all its BOs to
1626 * be resident to run successfully
1627 */
1628 #ifdef __NetBSD__ /* XXX amdgpu kfd */
1629 __USE(flist);
1630 __USE(f);
1631 __USE(i);
1632 #else
1633 flist = dma_resv_get_list(bo->base.resv);
1634 if (flist) {
1635 for (i = 0; i < flist->shared_count; ++i) {
1636 f = rcu_dereference_protected(flist->shared[i],
1637 dma_resv_held(bo->base.resv));
1638 if (amdkfd_fence_check_mm(f, current->mm))
1639 return false;
1640 }
1641 }
1642 #endif
1643
1644 switch (bo->mem.mem_type) {
1645 case TTM_PL_TT:
1646 return true;
1647
1648 case TTM_PL_VRAM:
1649 /* Check each drm MM node individually */
1650 while (num_pages) {
1651 if (place->fpfn < (node->start + node->size) &&
1652 !(place->lpfn && place->lpfn <= node->start))
1653 return true;
1654
1655 num_pages -= node->size;
1656 ++node;
1657 }
1658 return false;
1659
1660 default:
1661 break;
1662 }
1663
1664 return ttm_bo_eviction_valuable(bo, place);
1665 }
1666
1667 /**
1668 * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1669 *
1670 * @bo: The buffer object to read/write
1671 * @offset: Offset into buffer object
1672 * @buf: Secondary buffer to write/read from
1673 * @len: Length in bytes of access
1674 * @write: true if writing
1675 *
1676 * This is used to access VRAM that backs a buffer object via MMIO
1677 * access for debugging purposes.
1678 */
amdgpu_ttm_access_memory(struct ttm_buffer_object * bo,unsigned long offset,void * buf,int len,int write)1679 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1680 unsigned long offset,
1681 void *buf, int len, int write)
1682 {
1683 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1684 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1685 struct drm_mm_node *nodes;
1686 uint32_t value = 0;
1687 int ret = 0;
1688 uint64_t pos;
1689 unsigned long flags;
1690
1691 if (bo->mem.mem_type != TTM_PL_VRAM)
1692 return -EIO;
1693
1694 nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1695 pos = (nodes->start << PAGE_SHIFT) + offset;
1696
1697 while (len && pos < adev->gmc.mc_vram_size) {
1698 uint64_t aligned_pos = pos & ~(uint64_t)3;
1699 uint32_t bytes = 4 - (pos & 3);
1700 uint32_t shift = (pos & 3) * 8;
1701 uint32_t mask = 0xffffffff << shift;
1702
1703 if (len < bytes) {
1704 mask &= 0xffffffff >> (bytes - len) * 8;
1705 bytes = len;
1706 }
1707
1708 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1709 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1710 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1711 if (!write || mask != 0xffffffff)
1712 value = RREG32_NO_KIQ(mmMM_DATA);
1713 if (write) {
1714 value &= ~mask;
1715 value |= (*(uint32_t *)buf << shift) & mask;
1716 WREG32_NO_KIQ(mmMM_DATA, value);
1717 }
1718 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1719 if (!write) {
1720 value = (value & mask) >> shift;
1721 memcpy(buf, &value, bytes);
1722 }
1723
1724 ret += bytes;
1725 buf = (uint8_t *)buf + bytes;
1726 pos += bytes;
1727 len -= bytes;
1728 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1729 ++nodes;
1730 pos = (nodes->start << PAGE_SHIFT);
1731 }
1732 }
1733
1734 return ret;
1735 }
1736
1737 static struct ttm_bo_driver amdgpu_bo_driver = {
1738 .ttm_tt_create = &amdgpu_ttm_tt_create,
1739 .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1740 .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1741 #ifdef __NetBSD__
1742 .ttm_tt_swapout = &amdgpu_ttm_tt_swapout,
1743 .ttm_uvm_ops = &amdgpu_uvm_ops,
1744 #endif
1745 .invalidate_caches = &amdgpu_invalidate_caches,
1746 .init_mem_type = &amdgpu_init_mem_type,
1747 .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1748 .evict_flags = &amdgpu_evict_flags,
1749 .move = &amdgpu_bo_move,
1750 .verify_access = &amdgpu_verify_access,
1751 .move_notify = &amdgpu_bo_move_notify,
1752 .release_notify = &amdgpu_bo_release_notify,
1753 .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1754 .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1755 .io_mem_free = &amdgpu_ttm_io_mem_free,
1756 .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1757 .access_memory = &amdgpu_ttm_access_memory,
1758 .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1759 };
1760
1761 /*
1762 * Firmware Reservation functions
1763 */
1764 /**
1765 * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1766 *
1767 * @adev: amdgpu_device pointer
1768 *
1769 * free fw reserved vram if it has been reserved.
1770 */
amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device * adev)1771 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1772 {
1773 amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1774 NULL, &adev->fw_vram_usage.va);
1775 }
1776
1777 /**
1778 * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1779 *
1780 * @adev: amdgpu_device pointer
1781 *
1782 * create bo vram reservation from fw.
1783 */
amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device * adev)1784 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1785 {
1786 uint64_t vram_size = adev->gmc.visible_vram_size;
1787
1788 adev->fw_vram_usage.va = NULL;
1789 adev->fw_vram_usage.reserved_bo = NULL;
1790
1791 if (adev->fw_vram_usage.size == 0 ||
1792 adev->fw_vram_usage.size > vram_size)
1793 return 0;
1794
1795 return amdgpu_bo_create_kernel_at(adev,
1796 adev->fw_vram_usage.start_offset,
1797 adev->fw_vram_usage.size,
1798 AMDGPU_GEM_DOMAIN_VRAM,
1799 &adev->fw_vram_usage.reserved_bo,
1800 &adev->fw_vram_usage.va);
1801 }
1802
1803 /*
1804 * Memoy training reservation functions
1805 */
1806
1807 /**
1808 * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1809 *
1810 * @adev: amdgpu_device pointer
1811 *
1812 * free memory training reserved vram if it has been reserved.
1813 */
amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device * adev)1814 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1815 {
1816 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1817
1818 ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1819 amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1820 ctx->c2p_bo = NULL;
1821
1822 return 0;
1823 }
1824
amdgpu_ttm_training_get_c2p_offset(u64 vram_size)1825 static u64 amdgpu_ttm_training_get_c2p_offset(u64 vram_size)
1826 {
1827 if ((vram_size & (SZ_1M - 1)) < (SZ_4K + 1) )
1828 vram_size -= SZ_1M;
1829
1830 return ALIGN(vram_size, SZ_1M);
1831 }
1832
1833 /**
1834 * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from memory training
1835 *
1836 * @adev: amdgpu_device pointer
1837 *
1838 * create bo vram reservation from memory training.
1839 */
amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device * adev)1840 static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
1841 {
1842 int ret;
1843 struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1844
1845 memset(ctx, 0, sizeof(*ctx));
1846 if (!adev->fw_vram_usage.mem_train_support) {
1847 DRM_DEBUG("memory training does not support!\n");
1848 return 0;
1849 }
1850
1851 ctx->c2p_train_data_offset = amdgpu_ttm_training_get_c2p_offset(adev->gmc.mc_vram_size);
1852 ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1853 ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1854
1855 DRM_DEBUG("train_data_size:%"PRIx64",p2c_train_data_offset:%"PRIx64",c2p_train_data_offset:%"PRIx64".\n",
1856 ctx->train_data_size,
1857 ctx->p2c_train_data_offset,
1858 ctx->c2p_train_data_offset);
1859
1860 ret = amdgpu_bo_create_kernel_at(adev,
1861 ctx->c2p_train_data_offset,
1862 ctx->train_data_size,
1863 AMDGPU_GEM_DOMAIN_VRAM,
1864 &ctx->c2p_bo,
1865 NULL);
1866 if (ret) {
1867 DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1868 amdgpu_ttm_training_reserve_vram_fini(adev);
1869 return ret;
1870 }
1871
1872 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1873 return 0;
1874 }
1875
1876 /**
1877 * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1878 * gtt/vram related fields.
1879 *
1880 * This initializes all of the memory space pools that the TTM layer
1881 * will need such as the GTT space (system memory mapped to the device),
1882 * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1883 * can be mapped per VMID.
1884 */
amdgpu_ttm_init(struct amdgpu_device * adev)1885 int amdgpu_ttm_init(struct amdgpu_device *adev)
1886 {
1887 uint64_t gtt_size;
1888 int r;
1889 u64 vis_vram_limit;
1890 void *stolen_vga_buf;
1891
1892 mutex_init(&adev->mman.gtt_window_lock);
1893
1894 /* No others user of address space so set it to 0 */
1895 r = ttm_bo_device_init(&adev->mman.bdev,
1896 &amdgpu_bo_driver,
1897 #ifdef __NetBSD__
1898 adev->ddev->bst,
1899 adev->ddev->dmat,
1900 #else
1901 adev->ddev->anon_inode->i_mapping,
1902 #endif
1903 adev->ddev->vma_offset_manager,
1904 dma_addressing_limited(adev->dev));
1905 if (r) {
1906 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1907 return r;
1908 }
1909 adev->mman.initialized = true;
1910
1911 /* We opt to avoid OOM on system pages allocations */
1912 adev->mman.bdev.no_retry = true;
1913
1914 /* Initialize VRAM pool with all of VRAM divided into pages */
1915 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1916 adev->gmc.real_vram_size >> PAGE_SHIFT);
1917 if (r) {
1918 DRM_ERROR("Failed initializing VRAM heap.\n");
1919 return r;
1920 }
1921
1922 /* Reduce size of CPU-visible VRAM if requested */
1923 vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1924 if (amdgpu_vis_vram_limit > 0 &&
1925 vis_vram_limit <= adev->gmc.visible_vram_size)
1926 adev->gmc.visible_vram_size = vis_vram_limit;
1927
1928 /* Change the size here instead of the init above so only lpfn is affected */
1929 amdgpu_ttm_set_buffer_funcs_status(adev, false);
1930 #ifdef __NetBSD__
1931 #ifdef _LP64
1932 if (bus_space_map(adev->gmc.aper_tag, adev->gmc.aper_base,
1933 adev->gmc.visible_vram_size,
1934 BUS_SPACE_MAP_LINEAR|BUS_SPACE_MAP_PREFETCHABLE,
1935 &adev->mman.aper_base_handle)) {
1936 return -EIO;
1937 }
1938 adev->mman.aper_base_kaddr = bus_space_vaddr(adev->gmc.aper_tag,
1939 adev->mman.aper_base_handle);
1940 KASSERT(adev->mman.aper_base_kaddr != NULL);
1941 #endif /* _LP64 */
1942 #else /* __NetBSD__ */
1943 #ifdef CONFIG_64BIT
1944 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1945 adev->gmc.visible_vram_size);
1946 #endif
1947 #endif
1948
1949 /*
1950 *The reserved vram for firmware must be pinned to the specified
1951 *place on the VRAM, so reserve it early.
1952 */
1953 r = amdgpu_ttm_fw_reserve_vram_init(adev);
1954 if (r) {
1955 return r;
1956 }
1957
1958 /*
1959 *The reserved vram for memory training must be pinned to the specified
1960 *place on the VRAM, so reserve it early.
1961 */
1962 r = amdgpu_ttm_training_reserve_vram_init(adev);
1963 if (r)
1964 return r;
1965
1966 /* allocate memory as required for VGA
1967 * This is used for VGA emulation and pre-OS scanout buffers to
1968 * avoid display artifacts while transitioning between pre-OS
1969 * and driver. */
1970 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1971 AMDGPU_GEM_DOMAIN_VRAM,
1972 &adev->stolen_vga_memory,
1973 NULL, &stolen_vga_buf);
1974 if (r)
1975 return r;
1976
1977 /*
1978 * reserve one TMR (64K) memory at the top of VRAM which holds
1979 * IP Discovery data and is protected by PSP.
1980 */
1981 r = amdgpu_bo_create_kernel_at(adev,
1982 adev->gmc.real_vram_size - DISCOVERY_TMR_SIZE,
1983 DISCOVERY_TMR_SIZE,
1984 AMDGPU_GEM_DOMAIN_VRAM,
1985 &adev->discovery_memory,
1986 NULL);
1987 if (r)
1988 return r;
1989
1990 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1991 (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1992
1993 /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1994 * or whatever the user passed on module init */
1995 if (amdgpu_gtt_size == -1) {
1996 struct sysinfo si;
1997
1998 si_meminfo(&si);
1999 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
2000 adev->gmc.mc_vram_size),
2001 ((uint64_t)si.totalram * si.mem_unit * 3/4));
2002 }
2003 else
2004 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
2005
2006 /* Initialize GTT memory pool */
2007 r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
2008 if (r) {
2009 DRM_ERROR("Failed initializing GTT heap.\n");
2010 return r;
2011 }
2012 DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
2013 (unsigned)(gtt_size / (1024 * 1024)));
2014
2015 /* Initialize various on-chip memory pools */
2016 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
2017 adev->gds.gds_size);
2018 if (r) {
2019 DRM_ERROR("Failed initializing GDS heap.\n");
2020 return r;
2021 }
2022
2023 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
2024 adev->gds.gws_size);
2025 if (r) {
2026 DRM_ERROR("Failed initializing gws heap.\n");
2027 return r;
2028 }
2029
2030 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
2031 adev->gds.oa_size);
2032 if (r) {
2033 DRM_ERROR("Failed initializing oa heap.\n");
2034 return r;
2035 }
2036
2037 /* Register debugfs entries for amdgpu_ttm */
2038 r = amdgpu_ttm_debugfs_init(adev);
2039 if (r) {
2040 DRM_ERROR("Failed to init debugfs\n");
2041 return r;
2042 }
2043 return 0;
2044 }
2045
2046 /**
2047 * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
2048 */
amdgpu_ttm_late_init(struct amdgpu_device * adev)2049 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
2050 {
2051 void *stolen_vga_buf;
2052 /* return the VGA stolen memory (if any) back to VRAM */
2053 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
2054 }
2055
2056 /**
2057 * amdgpu_ttm_fini - De-initialize the TTM memory pools
2058 */
amdgpu_ttm_fini(struct amdgpu_device * adev)2059 void amdgpu_ttm_fini(struct amdgpu_device *adev)
2060 {
2061 if (!adev->mman.initialized)
2062 return;
2063
2064 amdgpu_ttm_debugfs_fini(adev);
2065 amdgpu_ttm_training_reserve_vram_fini(adev);
2066 /* return the IP Discovery TMR memory back to VRAM */
2067 amdgpu_bo_free_kernel(&adev->discovery_memory, NULL, NULL);
2068 amdgpu_ttm_fw_reserve_vram_fini(adev);
2069
2070 #ifdef __NetBSD__
2071 if (adev->mman.aper_base_handle) {
2072 bus_space_unmap(adev->gmc.aper_tag,
2073 adev->mman.aper_base_handle, adev->gmc.visible_vram_size);
2074 }
2075 #else
2076 if (adev->mman.aper_base_kaddr)
2077 iounmap(adev->mman.aper_base_kaddr);
2078 #endif
2079 adev->mman.aper_base_kaddr = NULL;
2080
2081 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
2082 ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
2083 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
2084 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
2085 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
2086 ttm_bo_device_release(&adev->mman.bdev);
2087 adev->mman.initialized = false;
2088 mutex_destroy(&adev->mman.gtt_window_lock);
2089 DRM_INFO("amdgpu: ttm finalized\n");
2090 }
2091
2092 /**
2093 * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
2094 *
2095 * @adev: amdgpu_device pointer
2096 * @enable: true when we can use buffer functions.
2097 *
2098 * Enable/disable use of buffer functions during suspend/resume. This should
2099 * only be called at bootup or when userspace isn't running.
2100 */
amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device * adev,bool enable)2101 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
2102 {
2103 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
2104 uint64_t size;
2105 int r;
2106
2107 if (!adev->mman.initialized || adev->in_gpu_reset ||
2108 adev->mman.buffer_funcs_enabled == enable)
2109 return;
2110
2111 if (enable) {
2112 struct amdgpu_ring *ring;
2113 struct drm_gpu_scheduler *sched;
2114
2115 ring = adev->mman.buffer_funcs_ring;
2116 sched = &ring->sched;
2117 r = drm_sched_entity_init(&adev->mman.entity,
2118 DRM_SCHED_PRIORITY_KERNEL, &sched,
2119 1, NULL);
2120 if (r) {
2121 DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
2122 r);
2123 return;
2124 }
2125 } else {
2126 drm_sched_entity_destroy(&adev->mman.entity);
2127 dma_fence_put(man->move);
2128 man->move = NULL;
2129 }
2130
2131 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
2132 if (enable)
2133 size = adev->gmc.real_vram_size;
2134 else
2135 size = adev->gmc.visible_vram_size;
2136 man->size = size >> PAGE_SHIFT;
2137 adev->mman.buffer_funcs_enabled = enable;
2138 }
2139
2140 #ifdef __NetBSD__
2141
2142 int
amdgpu_mmap_object(struct drm_device * dev,off_t offset,size_t size,vm_prot_t prot,struct uvm_object ** uobjp,voff_t * uoffsetp,struct file * file)2143 amdgpu_mmap_object(struct drm_device *dev, off_t offset, size_t size,
2144 vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp,
2145 struct file *file)
2146 {
2147 struct amdgpu_device *adev = dev->dev_private;
2148
2149 KASSERT(0 == (offset & (PAGE_SIZE - 1)));
2150
2151 if (__predict_false(adev == NULL)) /* XXX How?? */
2152 return -EINVAL;
2153
2154 return ttm_bo_mmap_object(&adev->mman.bdev, offset, size, prot,
2155 uobjp, uoffsetp, file);
2156 }
2157
2158 #else /* __NetBSD__ */
2159
amdgpu_mmap(struct file * filp,struct vm_area_struct * vma)2160 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
2161 {
2162 struct drm_file *file_priv = filp->private_data;
2163 struct amdgpu_device *adev = file_priv->minor->dev->dev_private;
2164
2165 if (adev == NULL)
2166 return -EINVAL;
2167
2168 return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
2169 }
2170
2171 #endif /* __NetBSD__ */
amdgpu_map_buffer(struct ttm_buffer_object * bo,struct ttm_mem_reg * mem,unsigned num_pages,uint64_t offset,unsigned window,struct amdgpu_ring * ring,uint64_t * addr)2172 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
2173 struct ttm_mem_reg *mem, unsigned num_pages,
2174 uint64_t offset, unsigned window,
2175 struct amdgpu_ring *ring,
2176 uint64_t *addr)
2177 {
2178 struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
2179 struct amdgpu_device *adev = ring->adev;
2180 struct ttm_tt *ttm = bo->ttm;
2181 struct amdgpu_job *job;
2182 unsigned num_dw, num_bytes;
2183 dma_addr_t *dma_address;
2184 struct dma_fence *fence;
2185 uint64_t src_addr, dst_addr;
2186 uint64_t flags;
2187 int r;
2188
2189 BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
2190 AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
2191
2192 *addr = adev->gmc.gart_start;
2193 *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
2194 AMDGPU_GPU_PAGE_SIZE;
2195
2196 num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
2197 num_bytes = num_pages * 8;
2198
2199 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
2200 if (r)
2201 return r;
2202
2203 src_addr = num_dw * 4;
2204 src_addr += job->ibs[0].gpu_addr;
2205
2206 dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2207 dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
2208 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
2209 dst_addr, num_bytes);
2210
2211 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2212 WARN_ON(job->ibs[0].length_dw > num_dw);
2213
2214 #ifdef __NetBSD__
2215 __USE(dma_address);
2216 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2217 r = amdgpu_gart_map(adev, 0, num_pages, offset, gtt->ttm.dma_address,
2218 flags, &job->ibs[0].ptr[num_dw]);
2219 #else
2220 dma_address = >t->ttm.dma_address[offset >> PAGE_SHIFT];
2221 flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2222 r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2223 &job->ibs[0].ptr[num_dw]);
2224 #endif
2225 if (r)
2226 goto error_free;
2227
2228 r = amdgpu_job_submit(job, &adev->mman.entity,
2229 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2230 if (r)
2231 goto error_free;
2232
2233 dma_fence_put(fence);
2234
2235 return r;
2236
2237 error_free:
2238 amdgpu_job_free(job);
2239 return r;
2240 }
2241
amdgpu_copy_buffer(struct amdgpu_ring * ring,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,struct dma_resv * resv,struct dma_fence ** fence,bool direct_submit,bool vm_needs_flush)2242 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2243 uint64_t dst_offset, uint32_t byte_count,
2244 struct dma_resv *resv,
2245 struct dma_fence **fence, bool direct_submit,
2246 bool vm_needs_flush)
2247 {
2248 struct amdgpu_device *adev = ring->adev;
2249 struct amdgpu_job *job;
2250
2251 uint32_t max_bytes;
2252 unsigned num_loops, num_dw;
2253 unsigned i;
2254 int r;
2255
2256 if (direct_submit && !ring->sched.ready) {
2257 DRM_ERROR("Trying to move memory with ring turned off.\n");
2258 return -EINVAL;
2259 }
2260
2261 max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2262 num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2263 num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
2264
2265 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2266 if (r)
2267 return r;
2268
2269 if (vm_needs_flush) {
2270 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2271 job->vm_needs_flush = true;
2272 }
2273 if (resv) {
2274 r = amdgpu_sync_resv(adev, &job->sync, resv,
2275 AMDGPU_FENCE_OWNER_UNDEFINED,
2276 false);
2277 if (r) {
2278 DRM_ERROR("sync failed (%d).\n", r);
2279 goto error_free;
2280 }
2281 }
2282
2283 for (i = 0; i < num_loops; i++) {
2284 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2285
2286 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2287 dst_offset, cur_size_in_bytes);
2288
2289 src_offset += cur_size_in_bytes;
2290 dst_offset += cur_size_in_bytes;
2291 byte_count -= cur_size_in_bytes;
2292 }
2293
2294 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2295 WARN_ON(job->ibs[0].length_dw > num_dw);
2296 if (direct_submit)
2297 r = amdgpu_job_submit_direct(job, ring, fence);
2298 else
2299 r = amdgpu_job_submit(job, &adev->mman.entity,
2300 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2301 if (r)
2302 goto error_free;
2303
2304 return r;
2305
2306 error_free:
2307 amdgpu_job_free(job);
2308 DRM_ERROR("Error scheduling IBs (%d)\n", r);
2309 return r;
2310 }
2311
amdgpu_fill_buffer(struct amdgpu_bo * bo,uint32_t src_data,struct dma_resv * resv,struct dma_fence ** fence)2312 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2313 uint32_t src_data,
2314 struct dma_resv *resv,
2315 struct dma_fence **fence)
2316 {
2317 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2318 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2319 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2320
2321 struct drm_mm_node *mm_node;
2322 unsigned long num_pages;
2323 unsigned int num_loops, num_dw;
2324
2325 struct amdgpu_job *job;
2326 int r;
2327
2328 if (!adev->mman.buffer_funcs_enabled) {
2329 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2330 return -EINVAL;
2331 }
2332
2333 if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2334 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2335 if (r)
2336 return r;
2337 }
2338
2339 num_pages = bo->tbo.num_pages;
2340 mm_node = bo->tbo.mem.mm_node;
2341 num_loops = 0;
2342 while (num_pages) {
2343 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2344
2345 num_loops += DIV_ROUND_UP_ULL(byte_count, max_bytes);
2346 num_pages -= mm_node->size;
2347 ++mm_node;
2348 }
2349 num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2350
2351 /* for IB padding */
2352 num_dw += 64;
2353
2354 r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2355 if (r)
2356 return r;
2357
2358 if (resv) {
2359 r = amdgpu_sync_resv(adev, &job->sync, resv,
2360 AMDGPU_FENCE_OWNER_UNDEFINED, false);
2361 if (r) {
2362 DRM_ERROR("sync failed (%d).\n", r);
2363 goto error_free;
2364 }
2365 }
2366
2367 num_pages = bo->tbo.num_pages;
2368 mm_node = bo->tbo.mem.mm_node;
2369
2370 while (num_pages) {
2371 uint64_t byte_count = mm_node->size << PAGE_SHIFT;
2372 uint64_t dst_addr;
2373
2374 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2375 while (byte_count) {
2376 uint32_t cur_size_in_bytes = min_t(uint64_t, byte_count,
2377 max_bytes);
2378
2379 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2380 dst_addr, cur_size_in_bytes);
2381
2382 dst_addr += cur_size_in_bytes;
2383 byte_count -= cur_size_in_bytes;
2384 }
2385
2386 num_pages -= mm_node->size;
2387 ++mm_node;
2388 }
2389
2390 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2391 WARN_ON(job->ibs[0].length_dw > num_dw);
2392 r = amdgpu_job_submit(job, &adev->mman.entity,
2393 AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2394 if (r)
2395 goto error_free;
2396
2397 return 0;
2398
2399 error_free:
2400 amdgpu_job_free(job);
2401 return r;
2402 }
2403
2404 #if defined(CONFIG_DEBUG_FS)
2405
amdgpu_mm_dump_table(struct seq_file * m,void * data)2406 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2407 {
2408 struct drm_info_node *node = (struct drm_info_node *)m->private;
2409 unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2410 struct drm_device *dev = node->minor->dev;
2411 struct amdgpu_device *adev = dev->dev_private;
2412 struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2413 struct drm_printer p = drm_seq_file_printer(m);
2414
2415 man->func->debug(man, &p);
2416 return 0;
2417 }
2418
2419 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2420 {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2421 {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2422 {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2423 {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2424 {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2425 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2426 #ifdef CONFIG_SWIOTLB
2427 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2428 #endif
2429 };
2430
2431 /**
2432 * amdgpu_ttm_vram_read - Linear read access to VRAM
2433 *
2434 * Accesses VRAM via MMIO for debugging purposes.
2435 */
amdgpu_ttm_vram_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2436 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2437 size_t size, loff_t *pos)
2438 {
2439 struct amdgpu_device *adev = file_inode(f)->i_private;
2440 ssize_t result = 0;
2441 int r;
2442
2443 if (size & 0x3 || *pos & 0x3)
2444 return -EINVAL;
2445
2446 if (*pos >= adev->gmc.mc_vram_size)
2447 return -ENXIO;
2448
2449 while (size) {
2450 unsigned long flags;
2451 uint32_t value;
2452
2453 if (*pos >= adev->gmc.mc_vram_size)
2454 return result;
2455
2456 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2457 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2458 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2459 value = RREG32_NO_KIQ(mmMM_DATA);
2460 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2461
2462 r = put_user(value, (uint32_t *)buf);
2463 if (r)
2464 return r;
2465
2466 result += 4;
2467 buf += 4;
2468 *pos += 4;
2469 size -= 4;
2470 }
2471
2472 return result;
2473 }
2474
2475 /**
2476 * amdgpu_ttm_vram_write - Linear write access to VRAM
2477 *
2478 * Accesses VRAM via MMIO for debugging purposes.
2479 */
amdgpu_ttm_vram_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2480 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2481 size_t size, loff_t *pos)
2482 {
2483 struct amdgpu_device *adev = file_inode(f)->i_private;
2484 ssize_t result = 0;
2485 int r;
2486
2487 if (size & 0x3 || *pos & 0x3)
2488 return -EINVAL;
2489
2490 if (*pos >= adev->gmc.mc_vram_size)
2491 return -ENXIO;
2492
2493 while (size) {
2494 unsigned long flags;
2495 uint32_t value;
2496
2497 if (*pos >= adev->gmc.mc_vram_size)
2498 return result;
2499
2500 r = get_user(value, (uint32_t *)buf);
2501 if (r)
2502 return r;
2503
2504 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2505 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2506 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2507 WREG32_NO_KIQ(mmMM_DATA, value);
2508 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2509
2510 result += 4;
2511 buf += 4;
2512 *pos += 4;
2513 size -= 4;
2514 }
2515
2516 return result;
2517 }
2518
2519 static const struct file_operations amdgpu_ttm_vram_fops = {
2520 .owner = THIS_MODULE,
2521 .read = amdgpu_ttm_vram_read,
2522 .write = amdgpu_ttm_vram_write,
2523 .llseek = default_llseek,
2524 };
2525
2526 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2527
2528 /**
2529 * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2530 */
amdgpu_ttm_gtt_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2531 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2532 size_t size, loff_t *pos)
2533 {
2534 struct amdgpu_device *adev = file_inode(f)->i_private;
2535 ssize_t result = 0;
2536 int r;
2537
2538 while (size) {
2539 loff_t p = *pos / PAGE_SIZE;
2540 unsigned off = *pos & ~PAGE_MASK;
2541 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2542 struct page *page;
2543 void *ptr;
2544
2545 if (p >= adev->gart.num_cpu_pages)
2546 return result;
2547
2548 page = adev->gart.pages[p];
2549 if (page) {
2550 ptr = kmap(page);
2551 ptr += off;
2552
2553 r = copy_to_user(buf, ptr, cur_size);
2554 kunmap(adev->gart.pages[p]);
2555 } else
2556 r = clear_user(buf, cur_size);
2557
2558 if (r)
2559 return -EFAULT;
2560
2561 result += cur_size;
2562 buf += cur_size;
2563 *pos += cur_size;
2564 size -= cur_size;
2565 }
2566
2567 return result;
2568 }
2569
2570 static const struct file_operations amdgpu_ttm_gtt_fops = {
2571 .owner = THIS_MODULE,
2572 .read = amdgpu_ttm_gtt_read,
2573 .llseek = default_llseek
2574 };
2575
2576 #endif
2577
2578 /**
2579 * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2580 *
2581 * This function is used to read memory that has been mapped to the
2582 * GPU and the known addresses are not physical addresses but instead
2583 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2584 */
amdgpu_iomem_read(struct file * f,char __user * buf,size_t size,loff_t * pos)2585 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2586 size_t size, loff_t *pos)
2587 {
2588 struct amdgpu_device *adev = file_inode(f)->i_private;
2589 struct iommu_domain *dom;
2590 ssize_t result = 0;
2591 int r;
2592
2593 /* retrieve the IOMMU domain if any for this device */
2594 dom = iommu_get_domain_for_dev(adev->dev);
2595
2596 while (size) {
2597 phys_addr_t addr = *pos & PAGE_MASK;
2598 loff_t off = *pos & ~PAGE_MASK;
2599 size_t bytes = PAGE_SIZE - off;
2600 unsigned long pfn;
2601 struct page *p;
2602 void *ptr;
2603
2604 bytes = bytes < size ? bytes : size;
2605
2606 /* Translate the bus address to a physical address. If
2607 * the domain is NULL it means there is no IOMMU active
2608 * and the address translation is the identity
2609 */
2610 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2611
2612 pfn = addr >> PAGE_SHIFT;
2613 if (!pfn_valid(pfn))
2614 return -EPERM;
2615
2616 p = pfn_to_page(pfn);
2617 if (p->mapping != adev->mman.bdev.dev_mapping)
2618 return -EPERM;
2619
2620 ptr = kmap(p);
2621 r = copy_to_user(buf, ptr + off, bytes);
2622 kunmap(p);
2623 if (r)
2624 return -EFAULT;
2625
2626 size -= bytes;
2627 *pos += bytes;
2628 result += bytes;
2629 }
2630
2631 return result;
2632 }
2633
2634 /**
2635 * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2636 *
2637 * This function is used to write memory that has been mapped to the
2638 * GPU and the known addresses are not physical addresses but instead
2639 * bus addresses (e.g., what you'd put in an IB or ring buffer).
2640 */
amdgpu_iomem_write(struct file * f,const char __user * buf,size_t size,loff_t * pos)2641 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2642 size_t size, loff_t *pos)
2643 {
2644 struct amdgpu_device *adev = file_inode(f)->i_private;
2645 struct iommu_domain *dom;
2646 ssize_t result = 0;
2647 int r;
2648
2649 dom = iommu_get_domain_for_dev(adev->dev);
2650
2651 while (size) {
2652 phys_addr_t addr = *pos & PAGE_MASK;
2653 loff_t off = *pos & ~PAGE_MASK;
2654 size_t bytes = PAGE_SIZE - off;
2655 unsigned long pfn;
2656 struct page *p;
2657 void *ptr;
2658
2659 bytes = bytes < size ? bytes : size;
2660
2661 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2662
2663 pfn = addr >> PAGE_SHIFT;
2664 if (!pfn_valid(pfn))
2665 return -EPERM;
2666
2667 p = pfn_to_page(pfn);
2668 if (p->mapping != adev->mman.bdev.dev_mapping)
2669 return -EPERM;
2670
2671 ptr = kmap(p);
2672 r = copy_from_user(ptr + off, buf, bytes);
2673 kunmap(p);
2674 if (r)
2675 return -EFAULT;
2676
2677 size -= bytes;
2678 *pos += bytes;
2679 result += bytes;
2680 }
2681
2682 return result;
2683 }
2684
2685 static const struct file_operations amdgpu_ttm_iomem_fops = {
2686 .owner = THIS_MODULE,
2687 .read = amdgpu_iomem_read,
2688 .write = amdgpu_iomem_write,
2689 .llseek = default_llseek
2690 };
2691
2692 static const struct {
2693 char *name;
2694 const struct file_operations *fops;
2695 int domain;
2696 } ttm_debugfs_entries[] = {
2697 { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2698 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2699 { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2700 #endif
2701 { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2702 };
2703
2704 #endif
2705
amdgpu_ttm_debugfs_init(struct amdgpu_device * adev)2706 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2707 {
2708 #if defined(CONFIG_DEBUG_FS)
2709 unsigned count;
2710
2711 struct drm_minor *minor = adev->ddev->primary;
2712 struct dentry *ent, *root = minor->debugfs_root;
2713
2714 for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2715 ent = debugfs_create_file(
2716 ttm_debugfs_entries[count].name,
2717 S_IFREG | S_IRUGO, root,
2718 adev,
2719 ttm_debugfs_entries[count].fops);
2720 if (IS_ERR(ent))
2721 return PTR_ERR(ent);
2722 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2723 i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2724 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2725 i_size_write(ent->d_inode, adev->gmc.gart_size);
2726 adev->mman.debugfs_entries[count] = ent;
2727 }
2728
2729 count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2730
2731 #ifdef CONFIG_SWIOTLB
2732 if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2733 --count;
2734 #endif
2735
2736 return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2737 #else
2738 return 0;
2739 #endif
2740 }
2741
amdgpu_ttm_debugfs_fini(struct amdgpu_device * adev)2742 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2743 {
2744 #if defined(CONFIG_DEBUG_FS)
2745 unsigned i;
2746
2747 for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2748 debugfs_remove(adev->mman.debugfs_entries[i]);
2749 #endif
2750 }
2751