1 /* $NetBSD: amr.c,v 1.61 2016/07/14 04:19:27 msaitoh Exp $ */
2
3 /*-
4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*-
33 * Copyright (c) 1999,2000 Michael Smith
34 * Copyright (c) 2000 BSDi
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 * SUCH DAMAGE.
57 *
58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp
59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp
60 */
61
62 /*
63 * Driver for AMI RAID controllers.
64 */
65
66 #include <sys/cdefs.h>
67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.61 2016/07/14 04:19:27 msaitoh Exp $");
68
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/kernel.h>
72 #include <sys/device.h>
73 #include <sys/queue.h>
74 #include <sys/proc.h>
75 #include <sys/buf.h>
76 #include <sys/malloc.h>
77 #include <sys/conf.h>
78 #include <sys/kthread.h>
79 #include <sys/kauth.h>
80 #include <sys/mutex.h>
81 #include <sys/condvar.h>
82
83 #include <machine/endian.h>
84 #include <sys/bus.h>
85
86 #include <dev/pci/pcidevs.h>
87 #include <dev/pci/pcivar.h>
88 #include <dev/pci/amrreg.h>
89 #include <dev/pci/amrvar.h>
90 #include <dev/pci/amrio.h>
91
92 #include "locators.h"
93
94 static void amr_attach(device_t, device_t, void *);
95 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *);
96 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t,
97 void *);
98 static int amr_init(struct amr_softc *, const char *,
99 struct pci_attach_args *pa);
100 static int amr_intr(void *);
101 static int amr_match(device_t, cfdata_t, void *);
102 static int amr_print(void *, const char *);
103 static void amr_shutdown(void *);
104 static void amr_teardown(struct amr_softc *);
105 static void amr_quartz_thread(void *);
106 static void amr_std_thread(void *);
107
108 static int amr_quartz_get_work(struct amr_softc *,
109 struct amr_mailbox_resp *);
110 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *);
111 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *);
112 static int amr_std_submit(struct amr_softc *, struct amr_ccb *);
113
114 static dev_type_open(amropen);
115 static dev_type_close(amrclose);
116 static dev_type_ioctl(amrioctl);
117
118 CFATTACH_DECL_NEW(amr, sizeof(struct amr_softc),
119 amr_match, amr_attach, NULL, NULL);
120
121 const struct cdevsw amr_cdevsw = {
122 .d_open = amropen,
123 .d_close = amrclose,
124 .d_read = noread,
125 .d_write = nowrite,
126 .d_ioctl = amrioctl,
127 .d_stop = nostop,
128 .d_tty = notty,
129 .d_poll = nopoll,
130 .d_mmap = nommap,
131 .d_kqfilter = nokqfilter,
132 .d_discard = nodiscard,
133 .d_flag = D_OTHER
134 };
135
136 extern struct cfdriver amr_cd;
137
138 #define AT_QUARTZ 0x01 /* `Quartz' chipset */
139 #define AT_SIG 0x02 /* Check for signature */
140
141 static struct amr_pci_type {
142 u_short apt_vendor;
143 u_short apt_product;
144 u_short apt_flags;
145 } const amr_pci_type[] = {
146 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 },
147 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 },
148 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ },
149 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ },
150 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG },
151 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ },
152 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ },
153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ },
154 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ },
155 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ },
156 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ },
157 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ },
158 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ },
159 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ },
160 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ },
161 };
162
163 static struct amr_typestr {
164 const char *at_str;
165 int at_sig;
166 } const amr_typestr[] = {
167 { "Series 431", AMR_SIG_431 },
168 { "Series 438", AMR_SIG_438 },
169 { "Series 466", AMR_SIG_466 },
170 { "Series 467", AMR_SIG_467 },
171 { "Series 490", AMR_SIG_490 },
172 { "Series 762", AMR_SIG_762 },
173 { "HP NetRAID (T5)", AMR_SIG_T5 },
174 { "HP NetRAID (T7)", AMR_SIG_T7 },
175 };
176
177 static struct {
178 const char *ds_descr;
179 int ds_happy;
180 } const amr_dstate[] = {
181 { "offline", 0 },
182 { "degraded", 1 },
183 { "optimal", 1 },
184 { "online", 1 },
185 { "failed", 0 },
186 { "rebuilding", 1 },
187 { "hotspare", 0 },
188 };
189
190 static void *amr_sdh;
191
192 static kcondvar_t thread_cv;
193 static kmutex_t thread_mutex;
194
195 static int amr_max_segs;
196 int amr_max_xfer;
197
198 static inline u_int8_t
amr_inb(struct amr_softc * amr,int off)199 amr_inb(struct amr_softc *amr, int off)
200 {
201 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1,
202 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ);
203 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off));
204 }
205
206 static inline u_int32_t
amr_inl(struct amr_softc * amr,int off)207 amr_inl(struct amr_softc *amr, int off)
208 {
209 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4,
210 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ);
211 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off));
212 }
213
214 static inline void
amr_outb(struct amr_softc * amr,int off,u_int8_t val)215 amr_outb(struct amr_softc *amr, int off, u_int8_t val)
216 {
217 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val);
218 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1,
219 BUS_SPACE_BARRIER_WRITE);
220 }
221
222 static inline void
amr_outl(struct amr_softc * amr,int off,u_int32_t val)223 amr_outl(struct amr_softc *amr, int off, u_int32_t val)
224 {
225 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val);
226 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4,
227 BUS_SPACE_BARRIER_WRITE);
228 }
229
230 /*
231 * Match a supported device.
232 */
233 static int
amr_match(device_t parent,cfdata_t match,void * aux)234 amr_match(device_t parent, cfdata_t match, void *aux)
235 {
236 struct pci_attach_args *pa;
237 pcireg_t s;
238 int i;
239
240 pa = (struct pci_attach_args *)aux;
241
242 /*
243 * Don't match the device if it's operating in I2O mode. In this
244 * case it should be handled by the `iop' driver.
245 */
246 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O)
247 return (0);
248
249 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++)
250 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor &&
251 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product)
252 break;
253
254 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0]))
255 return (0);
256
257 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0)
258 return (1);
259
260 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff;
261 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1);
262 }
263
264 /*
265 * Attach a supported device.
266 */
267 static void
amr_attach(device_t parent,device_t self,void * aux)268 amr_attach(device_t parent, device_t self, void *aux)
269 {
270 struct pci_attach_args *pa;
271 struct amr_attach_args amra;
272 const struct amr_pci_type *apt;
273 struct amr_softc *amr;
274 pci_chipset_tag_t pc;
275 pci_intr_handle_t ih;
276 const char *intrstr;
277 pcireg_t reg;
278 int rseg, i, j, size, rv, memreg, ioreg;
279 struct amr_ccb *ac;
280 int locs[AMRCF_NLOCS];
281 char intrbuf[PCI_INTRSTR_LEN];
282
283 aprint_naive(": RAID controller\n");
284
285 amr = device_private(self);
286 amr->amr_dv = self;
287
288 mutex_init(&amr->amr_mutex, MUTEX_DEFAULT, IPL_BIO);
289
290 pa = (struct pci_attach_args *)aux;
291 pc = pa->pa_pc;
292
293 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++)
294 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor &&
295 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product)
296 break;
297 apt = amr_pci_type + i;
298
299 memreg = ioreg = 0;
300 for (i = 0x10; i <= 0x14; i += 4) {
301 reg = pci_conf_read(pc, pa->pa_tag, i);
302 switch (PCI_MAPREG_TYPE(reg)) {
303 case PCI_MAPREG_TYPE_MEM:
304 if (PCI_MAPREG_MEM_SIZE(reg) != 0)
305 memreg = i;
306 break;
307 case PCI_MAPREG_TYPE_IO:
308 if (PCI_MAPREG_IO_SIZE(reg) != 0)
309 ioreg = i;
310 break;
311 }
312 }
313
314 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0,
315 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0)
316 ;
317 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0,
318 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0)
319 ;
320 else {
321 aprint_error("can't map control registers\n");
322 amr_teardown(amr);
323 return;
324 }
325
326 amr->amr_flags |= AMRF_PCI_REGS;
327 amr->amr_dmat = pa->pa_dmat;
328 amr->amr_pc = pa->pa_pc;
329
330 /* Enable the device. */
331 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
332 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
333 reg | PCI_COMMAND_MASTER_ENABLE);
334
335 /* Map and establish the interrupt. */
336 if (pci_intr_map(pa, &ih)) {
337 aprint_error("can't map interrupt\n");
338 amr_teardown(amr);
339 return;
340 }
341 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
342 amr->amr_ih = pci_intr_establish(pc, ih, IPL_BIO, amr_intr, amr);
343 if (amr->amr_ih == NULL) {
344 aprint_error("can't establish interrupt");
345 if (intrstr != NULL)
346 aprint_error(" at %s", intrstr);
347 aprint_error("\n");
348 amr_teardown(amr);
349 return;
350 }
351 amr->amr_flags |= AMRF_PCI_INTR;
352
353 /*
354 * Allocate space for the mailbox and S/G lists. Some controllers
355 * don't like S/G lists to be located below 0x2000, so we allocate
356 * enough slop to enable us to compensate.
357 *
358 * The standard mailbox structure needs to be aligned on a 16-byte
359 * boundary. The 64-bit mailbox has one extra field, 4 bytes in
360 * size, which precedes the standard mailbox.
361 */
362 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000;
363 amr->amr_dmasize = size;
364
365 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0,
366 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
367 aprint_error_dev(amr->amr_dv,
368 "unable to allocate buffer, rv = %d\n", rv);
369 amr_teardown(amr);
370 return;
371 }
372 amr->amr_flags |= AMRF_DMA_ALLOC;
373
374 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size,
375 (void **)&amr->amr_mbox,
376 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
377 aprint_error_dev(amr->amr_dv, "unable to map buffer, rv = %d\n",
378 rv);
379 amr_teardown(amr);
380 return;
381 }
382 amr->amr_flags |= AMRF_DMA_MAP;
383
384 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0,
385 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) {
386 aprint_error_dev(amr->amr_dv,
387 "unable to create buffer DMA map, rv = %d\n", rv);
388 amr_teardown(amr);
389 return;
390 }
391 amr->amr_flags |= AMRF_DMA_CREATE;
392
393 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap,
394 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) {
395 aprint_error_dev(amr->amr_dv,
396 "unable to load buffer DMA map, rv = %d\n", rv);
397 amr_teardown(amr);
398 return;
399 }
400 amr->amr_flags |= AMRF_DMA_LOAD;
401
402 memset(amr->amr_mbox, 0, size);
403
404 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr;
405 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff;
406 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox +
407 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr);
408
409 /*
410 * Allocate and initalise the command control blocks.
411 */
412 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_NOWAIT | M_ZERO);
413 amr->amr_ccbs = ac;
414 SLIST_INIT(&amr->amr_ccb_freelist);
415 TAILQ_INIT(&amr->amr_ccb_active);
416 amr->amr_flags |= AMRF_CCBS;
417
418 if (amr_max_xfer == 0) {
419 amr_max_xfer = min(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS);
420 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE;
421 }
422
423 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) {
424 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer,
425 amr_max_segs, amr_max_xfer, 0,
426 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map);
427 if (rv != 0)
428 break;
429
430 ac->ac_ident = i;
431 cv_init(&ac->ac_cv, "amr1ccb");
432 mutex_init(&ac->ac_mutex, MUTEX_DEFAULT, IPL_NONE);
433 amr_ccb_free(amr, ac);
434 }
435 if (i != AMR_MAX_CMDS) {
436 aprint_error_dev(amr->amr_dv, "memory exhausted\n");
437 amr_teardown(amr);
438 return;
439 }
440
441 /*
442 * Take care of model-specific tasks.
443 */
444 if ((apt->apt_flags & AT_QUARTZ) != 0) {
445 amr->amr_submit = amr_quartz_submit;
446 amr->amr_get_work = amr_quartz_get_work;
447 } else {
448 amr->amr_submit = amr_std_submit;
449 amr->amr_get_work = amr_std_get_work;
450
451 /* Notify the controller of the mailbox location. */
452 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16);
453 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR);
454
455 /* Clear outstanding interrupts and enable interrupts. */
456 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR);
457 amr_outb(amr, AMR_SREG_TOGL,
458 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE);
459 }
460
461 /*
462 * Retrieve parameters, and tell the world about us.
463 */
464 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_NOWAIT);
465 amr->amr_flags |= AMRF_ENQBUF;
466 amr->amr_maxqueuecnt = i;
467 aprint_normal(": AMI RAID ");
468 if (amr_init(amr, intrstr, pa) != 0) {
469 amr_teardown(amr);
470 return;
471 }
472
473 /*
474 * Cap the maximum number of outstanding commands. AMI's Linux
475 * driver doesn't trust the controller's reported value, and lockups
476 * have been seen when we do.
477 */
478 amr->amr_maxqueuecnt = min(amr->amr_maxqueuecnt, AMR_MAX_CMDS);
479 if (amr->amr_maxqueuecnt > i)
480 amr->amr_maxqueuecnt = i;
481
482 /* Set our `shutdownhook' before we start any device activity. */
483 if (amr_sdh == NULL)
484 amr_sdh = shutdownhook_establish(amr_shutdown, NULL);
485
486 /* Attach sub-devices. */
487 for (j = 0; j < amr->amr_numdrives; j++) {
488 if (amr->amr_drive[j].al_size == 0)
489 continue;
490 amra.amra_unit = j;
491
492 locs[AMRCF_UNIT] = j;
493
494 amr->amr_drive[j].al_dv = config_found_sm_loc(amr->amr_dv,
495 "amr", locs, &amra, amr_print, config_stdsubmatch);
496 }
497
498 SIMPLEQ_INIT(&amr->amr_ccb_queue);
499
500 cv_init(&thread_cv, "amrwdog");
501 mutex_init(&thread_mutex, MUTEX_DEFAULT, IPL_NONE);
502
503 if ((apt->apt_flags & AT_QUARTZ) == 0) {
504 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL,
505 amr_std_thread, amr, &amr->amr_thread,
506 "%s", device_xname(amr->amr_dv));
507 } else {
508 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL,
509 amr_quartz_thread, amr, &amr->amr_thread,
510 "%s", device_xname(amr->amr_dv));
511 }
512 if (rv != 0)
513 aprint_error_dev(amr->amr_dv, "unable to create thread (%d)",
514 rv);
515 else
516 amr->amr_flags |= AMRF_THREAD;
517 }
518
519 /*
520 * Free up resources.
521 */
522 static void
amr_teardown(struct amr_softc * amr)523 amr_teardown(struct amr_softc *amr)
524 {
525 struct amr_ccb *ac;
526 int fl;
527
528 fl = amr->amr_flags;
529
530 if ((fl & AMRF_THREAD) != 0) {
531 amr->amr_flags |= AMRF_THREAD_EXIT;
532 mutex_enter(&thread_mutex);
533 cv_broadcast(&thread_cv);
534 mutex_exit(&thread_mutex);
535 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) {
536 mutex_enter(&thread_mutex);
537 cv_wait(&thread_cv, &thread_mutex);
538 mutex_exit(&thread_mutex);
539 }
540 }
541 if ((fl & AMRF_CCBS) != 0) {
542 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) {
543 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map);
544 }
545 free(amr->amr_ccbs, M_DEVBUF);
546 }
547 if ((fl & AMRF_ENQBUF) != 0)
548 free(amr->amr_enqbuf, M_DEVBUF);
549 if ((fl & AMRF_DMA_LOAD) != 0)
550 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap);
551 if ((fl & AMRF_DMA_MAP) != 0)
552 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox,
553 amr->amr_dmasize);
554 if ((fl & AMRF_DMA_ALLOC) != 0)
555 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1);
556 if ((fl & AMRF_DMA_CREATE) != 0)
557 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap);
558 if ((fl & AMRF_PCI_INTR) != 0)
559 pci_intr_disestablish(amr->amr_pc, amr->amr_ih);
560 if ((fl & AMRF_PCI_REGS) != 0)
561 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios);
562 }
563
564 /*
565 * Print autoconfiguration message for a sub-device.
566 */
567 static int
amr_print(void * aux,const char * pnp)568 amr_print(void *aux, const char *pnp)
569 {
570 struct amr_attach_args *amra;
571
572 amra = (struct amr_attach_args *)aux;
573
574 if (pnp != NULL)
575 aprint_normal("block device at %s", pnp);
576 aprint_normal(" unit %d", amra->amra_unit);
577 return (UNCONF);
578 }
579
580 /*
581 * Retrieve operational parameters and describe the controller.
582 */
583 static int
amr_init(struct amr_softc * amr,const char * intrstr,struct pci_attach_args * pa)584 amr_init(struct amr_softc *amr, const char *intrstr,
585 struct pci_attach_args *pa)
586 {
587 struct amr_adapter_info *aa;
588 struct amr_prodinfo *ap;
589 struct amr_enquiry *ae;
590 struct amr_enquiry3 *aex;
591 const char *prodstr;
592 u_int i, sig, ishp;
593 char sbuf[64];
594
595 /*
596 * Try to get 40LD product info, which tells us what the card is
597 * labelled as.
598 */
599 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0,
600 amr->amr_enqbuf);
601 if (ap != NULL) {
602 aprint_normal("<%.80s>\n", ap->ap_product);
603 if (intrstr != NULL)
604 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n",
605 intrstr);
606 aprint_normal_dev(amr->amr_dv,
607 "firmware %.16s, BIOS %.16s, %dMB RAM\n",
608 ap->ap_firmware, ap->ap_bios, le16toh(ap->ap_memsize));
609
610 amr->amr_maxqueuecnt = ap->ap_maxio;
611
612 /*
613 * Fetch and record state of logical drives.
614 */
615 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3,
616 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf);
617 if (aex == NULL) {
618 aprint_error_dev(amr->amr_dv, "ENQUIRY3 failed\n");
619 return (-1);
620 }
621
622 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) {
623 aprint_error_dev(amr->amr_dv, "Inquiry returned more "
624 "drives (%d) than the array can handle (%zu)\n",
625 aex->ae_numldrives,
626 __arraycount(aex->ae_drivestate));
627 aex->ae_numldrives = __arraycount(aex->ae_drivestate);
628 }
629 if (aex->ae_numldrives > AMR_MAX_UNITS) {
630 aprint_error_dev(amr->amr_dv,
631 "adjust AMR_MAX_UNITS to %d (currently %d)\n",
632 AMR_MAX_UNITS, amr->amr_numdrives);
633 amr->amr_numdrives = AMR_MAX_UNITS;
634 } else
635 amr->amr_numdrives = aex->ae_numldrives;
636
637 for (i = 0; i < amr->amr_numdrives; i++) {
638 amr->amr_drive[i].al_size =
639 le32toh(aex->ae_drivesize[i]);
640 amr->amr_drive[i].al_state = aex->ae_drivestate[i];
641 amr->amr_drive[i].al_properties = aex->ae_driveprop[i];
642 }
643
644 return (0);
645 }
646
647 /*
648 * Try 8LD extended ENQUIRY to get the controller signature. Once
649 * found, search for a product description.
650 */
651 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf);
652 if (ae != NULL) {
653 i = 0;
654 sig = le32toh(ae->ae_signature);
655
656 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) {
657 if (amr_typestr[i].at_sig == sig)
658 break;
659 i++;
660 }
661 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) {
662 snprintf(sbuf, sizeof(sbuf),
663 "unknown ENQUIRY2 sig (0x%08x)", sig);
664 prodstr = sbuf;
665 } else
666 prodstr = amr_typestr[i].at_str;
667 } else {
668 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf);
669 if (ae == NULL) {
670 aprint_error_dev(amr->amr_dv,
671 "unsupported controller\n");
672 return (-1);
673 }
674
675 switch (PCI_PRODUCT(pa->pa_id)) {
676 case PCI_PRODUCT_AMI_MEGARAID:
677 prodstr = "Series 428";
678 break;
679 case PCI_PRODUCT_AMI_MEGARAID2:
680 prodstr = "Series 434";
681 break;
682 default:
683 snprintf(sbuf, sizeof(sbuf),
684 "unknown PCI dev (0x%04x)",
685 PCI_PRODUCT(pa->pa_id));
686 prodstr = sbuf;
687 break;
688 }
689 }
690
691 /*
692 * HP NetRaid controllers have a special encoding of the firmware
693 * and BIOS versions. The AMI version seems to have it as strings
694 * whereas the HP version does it with a leading uppercase character
695 * and two binary numbers.
696 */
697 aa = &ae->ae_adapter;
698
699 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' &&
700 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' &&
701 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' &&
702 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') {
703 if (le32toh(ae->ae_signature) == AMR_SIG_438) {
704 /* The AMI 438 is a NetRaid 3si in HP-land. */
705 prodstr = "HP NetRaid 3si";
706 }
707 ishp = 1;
708 } else
709 ishp = 0;
710
711 aprint_normal("<%s>\n", prodstr);
712 if (intrstr != NULL)
713 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n",
714 intrstr);
715
716 if (ishp)
717 aprint_normal_dev(amr->amr_dv, "firmware <%c.%02d.%02d>, "
718 "BIOS <%c.%02d.%02d>, %dMB RAM\n", aa->aa_firmware[2],
719 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2],
720 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize);
721 else
722 aprint_normal_dev(amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, "
723 "%dMB RAM\n", aa->aa_firmware, aa->aa_bios,
724 aa->aa_memorysize);
725
726 amr->amr_maxqueuecnt = aa->aa_maxio;
727
728 /*
729 * Record state of logical drives.
730 */
731 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) {
732 aprint_error_dev(amr->amr_dv, "Inquiry returned more drives "
733 "(%d) than the array can handle (%zu)\n",
734 ae->ae_ldrv.al_numdrives,
735 __arraycount(ae->ae_ldrv.al_size));
736 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size);
737 }
738 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) {
739 aprint_error_dev(amr->amr_dv,
740 "adjust AMR_MAX_UNITS to %d (currently %d)\n",
741 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS);
742 amr->amr_numdrives = AMR_MAX_UNITS;
743 } else
744 amr->amr_numdrives = ae->ae_ldrv.al_numdrives;
745
746 for (i = 0; i < amr->amr_numdrives; i++) {
747 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]);
748 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i];
749 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i];
750 }
751
752 return (0);
753 }
754
755 /*
756 * Flush the internal cache on each configured controller. Called at
757 * shutdown time.
758 */
759 static void
amr_shutdown(void * cookie)760 amr_shutdown(void *cookie)
761 {
762 extern struct cfdriver amr_cd;
763 struct amr_softc *amr;
764 struct amr_ccb *ac;
765 int i, rv;
766
767 for (i = 0; i < amr_cd.cd_ndevs; i++) {
768 if ((amr = device_lookup_private(&amr_cd, i)) == NULL)
769 continue;
770
771 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) {
772 ac->ac_cmd.mb_command = AMR_CMD_FLUSH;
773 rv = amr_ccb_poll(amr, ac, 30000);
774 amr_ccb_free(amr, ac);
775 }
776 if (rv != 0)
777 aprint_error_dev(amr->amr_dv,
778 "unable to flush cache (%d)\n", rv);
779 }
780 }
781
782 /*
783 * Interrupt service routine.
784 */
785 static int
amr_intr(void * cookie)786 amr_intr(void *cookie)
787 {
788 struct amr_softc *amr;
789 struct amr_ccb *ac;
790 struct amr_mailbox_resp mbox;
791 u_int i, forus, idx;
792
793 amr = cookie;
794 forus = 0;
795
796 mutex_spin_enter(&amr->amr_mutex);
797
798 while ((*amr->amr_get_work)(amr, &mbox) == 0) {
799 /* Iterate over completed commands in this result. */
800 for (i = 0; i < mbox.mb_nstatus; i++) {
801 idx = mbox.mb_completed[i] - 1;
802 ac = amr->amr_ccbs + idx;
803
804 if (idx >= amr->amr_maxqueuecnt) {
805 printf("%s: bad status (bogus ID: %u=%u)\n",
806 device_xname(amr->amr_dv), i, idx);
807 continue;
808 }
809
810 if ((ac->ac_flags & AC_ACTIVE) == 0) {
811 printf("%s: bad status (not active; 0x04%x)\n",
812 device_xname(amr->amr_dv), ac->ac_flags);
813 continue;
814 }
815
816 ac->ac_status = mbox.mb_status;
817 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) |
818 AC_COMPLETE;
819 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq);
820
821 if ((ac->ac_flags & AC_MOAN) != 0)
822 printf("%s: ccb %d completed\n",
823 device_xname(amr->amr_dv), ac->ac_ident);
824
825 /* Pass notification to upper layers. */
826 mutex_spin_exit(&amr->amr_mutex);
827 if (ac->ac_handler != NULL) {
828 (*ac->ac_handler)(ac);
829 } else {
830 mutex_enter(&ac->ac_mutex);
831 cv_signal(&ac->ac_cv);
832 mutex_exit(&ac->ac_mutex);
833 }
834 mutex_spin_enter(&amr->amr_mutex);
835 }
836 forus = 1;
837 }
838
839 mutex_spin_exit(&amr->amr_mutex);
840
841 if (forus)
842 amr_ccb_enqueue(amr, NULL);
843
844 return (forus);
845 }
846
847 /*
848 * Watchdog thread.
849 */
850 static void
amr_quartz_thread(void * cookie)851 amr_quartz_thread(void *cookie)
852 {
853 struct amr_softc *amr;
854 struct amr_ccb *ac;
855
856 amr = cookie;
857
858 for (;;) {
859 mutex_enter(&thread_mutex);
860 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS);
861 mutex_exit(&thread_mutex);
862
863 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) {
864 amr->amr_flags ^= AMRF_THREAD_EXIT;
865 mutex_enter(&thread_mutex);
866 cv_signal(&thread_cv);
867 mutex_exit(&thread_mutex);
868 kthread_exit(0);
869 }
870
871 if (amr_intr(amr) == 0)
872 amr_ccb_enqueue(amr, NULL);
873
874 mutex_spin_enter(&amr->amr_mutex);
875 ac = TAILQ_FIRST(&amr->amr_ccb_active);
876 while (ac != NULL) {
877 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime)
878 break;
879 if ((ac->ac_flags & AC_MOAN) == 0) {
880 printf("%s: ccb %d timed out; mailbox:\n",
881 device_xname(amr->amr_dv), ac->ac_ident);
882 amr_ccb_dump(amr, ac);
883 ac->ac_flags |= AC_MOAN;
884 }
885 ac = TAILQ_NEXT(ac, ac_chain.tailq);
886 }
887 mutex_spin_exit(&amr->amr_mutex);
888 }
889 }
890
891 static void
amr_std_thread(void * cookie)892 amr_std_thread(void *cookie)
893 {
894 struct amr_softc *amr;
895 struct amr_ccb *ac;
896 struct amr_logdrive *al;
897 struct amr_enquiry *ae;
898 int rv, i;
899
900 amr = cookie;
901 ae = amr->amr_enqbuf;
902
903 for (;;) {
904 mutex_enter(&thread_mutex);
905 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS);
906 mutex_exit(&thread_mutex);
907
908 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) {
909 amr->amr_flags ^= AMRF_THREAD_EXIT;
910 mutex_enter(&thread_mutex);
911 cv_signal(&thread_cv);
912 mutex_exit(&thread_mutex);
913 kthread_exit(0);
914 }
915
916 if (amr_intr(amr) == 0)
917 amr_ccb_enqueue(amr, NULL);
918
919 mutex_spin_enter(&amr->amr_mutex);
920 ac = TAILQ_FIRST(&amr->amr_ccb_active);
921 while (ac != NULL) {
922 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime)
923 break;
924 if ((ac->ac_flags & AC_MOAN) == 0) {
925 printf("%s: ccb %d timed out; mailbox:\n",
926 device_xname(amr->amr_dv), ac->ac_ident);
927 amr_ccb_dump(amr, ac);
928 ac->ac_flags |= AC_MOAN;
929 }
930 ac = TAILQ_NEXT(ac, ac_chain.tailq);
931 }
932 mutex_spin_exit(&amr->amr_mutex);
933
934 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) {
935 printf("%s: ccb_alloc failed (%d)\n",
936 device_xname(amr->amr_dv), rv);
937 continue;
938 }
939
940 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY;
941
942 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf,
943 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN);
944 if (rv != 0) {
945 aprint_error_dev(amr->amr_dv, "ccb_map failed (%d)\n",
946 rv);
947 amr_ccb_free(amr, ac);
948 continue;
949 }
950
951 rv = amr_ccb_wait(amr, ac);
952 amr_ccb_unmap(amr, ac);
953 if (rv != 0) {
954 aprint_error_dev(amr->amr_dv,
955 "enquiry failed (st=%d)\n", ac->ac_status);
956 continue;
957 }
958 amr_ccb_free(amr, ac);
959
960 al = amr->amr_drive;
961 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) {
962 if (al->al_dv == NULL)
963 continue;
964 if (al->al_state == ae->ae_ldrv.al_state[i])
965 continue;
966
967 printf("%s: state changed: %s -> %s\n",
968 device_xname(al->al_dv),
969 amr_drive_state(al->al_state, NULL),
970 amr_drive_state(ae->ae_ldrv.al_state[i], NULL));
971
972 al->al_state = ae->ae_ldrv.al_state[i];
973 }
974 }
975 }
976
977 /*
978 * Return a text description of a logical drive's current state.
979 */
980 const char *
amr_drive_state(int state,int * happy)981 amr_drive_state(int state, int *happy)
982 {
983 const char *str;
984
985 state = AMR_DRV_CURSTATE(state);
986 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) {
987 if (happy)
988 *happy = 1;
989 str = "status unknown";
990 } else {
991 if (happy)
992 *happy = amr_dstate[state].ds_happy;
993 str = amr_dstate[state].ds_descr;
994 }
995
996 return (str);
997 }
998
999 /*
1000 * Run a generic enquiry-style command.
1001 */
1002 static void *
amr_enquire(struct amr_softc * amr,u_int8_t cmd,u_int8_t cmdsub,u_int8_t cmdqual,void * sbuf)1003 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub,
1004 u_int8_t cmdqual, void *sbuf)
1005 {
1006 struct amr_ccb *ac;
1007 u_int8_t *mb;
1008 int rv;
1009
1010 if (amr_ccb_alloc(amr, &ac) != 0)
1011 return (NULL);
1012
1013 /* Build the command proper. */
1014 mb = (u_int8_t *)&ac->ac_cmd;
1015 mb[0] = cmd;
1016 mb[2] = cmdsub;
1017 mb[3] = cmdqual;
1018
1019 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN);
1020 if (rv == 0) {
1021 rv = amr_ccb_poll(amr, ac, 2000);
1022 amr_ccb_unmap(amr, ac);
1023 }
1024 amr_ccb_free(amr, ac);
1025
1026 return (rv ? NULL : sbuf);
1027 }
1028
1029 /*
1030 * Allocate and initialise a CCB.
1031 */
1032 int
amr_ccb_alloc(struct amr_softc * amr,struct amr_ccb ** acp)1033 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp)
1034 {
1035 mutex_spin_enter(&amr->amr_mutex);
1036 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) {
1037 mutex_spin_exit(&amr->amr_mutex);
1038 return (EAGAIN);
1039 }
1040 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist);
1041 mutex_spin_exit(&amr->amr_mutex);
1042
1043 return (0);
1044 }
1045
1046 /*
1047 * Free a CCB.
1048 */
1049 void
amr_ccb_free(struct amr_softc * amr,struct amr_ccb * ac)1050 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac)
1051 {
1052 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd));
1053 ac->ac_cmd.mb_ident = ac->ac_ident + 1;
1054 ac->ac_cmd.mb_busy = 1;
1055 ac->ac_handler = NULL;
1056 ac->ac_flags = 0;
1057
1058 mutex_spin_enter(&amr->amr_mutex);
1059 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist);
1060 mutex_spin_exit(&amr->amr_mutex);
1061 }
1062
1063 /*
1064 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in
1065 * the order that they were enqueued and try to submit their command blocks
1066 * to the controller for execution.
1067 */
1068 void
amr_ccb_enqueue(struct amr_softc * amr,struct amr_ccb * ac)1069 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac)
1070 {
1071 if (ac != NULL) {
1072 mutex_spin_enter(&amr->amr_mutex);
1073 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq);
1074 mutex_spin_exit(&amr->amr_mutex);
1075 }
1076
1077 while (SIMPLEQ_FIRST(&amr->amr_ccb_queue) != NULL) {
1078 mutex_spin_enter(&amr->amr_mutex);
1079 if ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) {
1080 if ((*amr->amr_submit)(amr, ac) != 0) {
1081 mutex_spin_exit(&amr->amr_mutex);
1082 break;
1083 }
1084 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue,
1085 ac_chain.simpleq);
1086 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac,
1087 ac_chain.tailq);
1088 }
1089 mutex_spin_exit(&amr->amr_mutex);
1090 }
1091 }
1092
1093 /*
1094 * Map the specified CCB's data buffer onto the bus, and fill the
1095 * scatter-gather list.
1096 */
1097 int
amr_ccb_map(struct amr_softc * amr,struct amr_ccb * ac,void * data,int size,int tflag)1098 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size,
1099 int tflag)
1100 {
1101 struct amr_sgentry *sge;
1102 struct amr_mailbox_cmd *mb;
1103 int nsegs, i, rv, sgloff;
1104 bus_dmamap_t xfer;
1105 int dmaflag = 0;
1106
1107 xfer = ac->ac_xfer_map;
1108
1109 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL,
1110 BUS_DMA_NOWAIT);
1111 if (rv != 0)
1112 return (rv);
1113
1114 mb = &ac->ac_cmd;
1115 ac->ac_xfer_size = size;
1116 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN));
1117 sgloff = AMR_SGL_SIZE * ac->ac_ident;
1118
1119 if (tflag & AC_XFER_OUT)
1120 dmaflag |= BUS_DMASYNC_PREWRITE;
1121 if (tflag & AC_XFER_IN)
1122 dmaflag |= BUS_DMASYNC_PREREAD;
1123
1124 /* We don't need to use a scatter/gather list for just 1 segment. */
1125 nsegs = xfer->dm_nsegs;
1126 if (nsegs == 1) {
1127 mb->mb_nsgelem = 0;
1128 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr);
1129 ac->ac_flags |= AC_NOSGL;
1130 } else {
1131 mb->mb_nsgelem = nsegs;
1132 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff);
1133
1134 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff);
1135 for (i = 0; i < nsegs; i++, sge++) {
1136 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr);
1137 sge->sge_count = htole32(xfer->dm_segs[i].ds_len);
1138 }
1139 }
1140
1141 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag);
1142
1143 if ((ac->ac_flags & AC_NOSGL) == 0)
1144 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff,
1145 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE);
1146
1147 return (0);
1148 }
1149
1150 /*
1151 * Unmap the specified CCB's data buffer.
1152 */
1153 void
amr_ccb_unmap(struct amr_softc * amr,struct amr_ccb * ac)1154 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac)
1155 {
1156 int dmaflag = 0;
1157
1158 if (ac->ac_flags & AC_XFER_IN)
1159 dmaflag |= BUS_DMASYNC_POSTREAD;
1160 if (ac->ac_flags & AC_XFER_OUT)
1161 dmaflag |= BUS_DMASYNC_POSTWRITE;
1162
1163 if ((ac->ac_flags & AC_NOSGL) == 0)
1164 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap,
1165 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE,
1166 BUS_DMASYNC_POSTWRITE);
1167 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size,
1168 dmaflag);
1169 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map);
1170 }
1171
1172 /*
1173 * Submit a command to the controller and poll on completion. Return
1174 * non-zero on timeout or error.
1175 */
1176 int
amr_ccb_poll(struct amr_softc * amr,struct amr_ccb * ac,int timo)1177 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo)
1178 {
1179 int rv, i;
1180
1181 mutex_spin_enter(&amr->amr_mutex);
1182 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) {
1183 mutex_spin_exit(&amr->amr_mutex);
1184 return (rv);
1185 }
1186 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq);
1187 mutex_spin_exit(&amr->amr_mutex);
1188
1189 for (i = timo * 10; i > 0; i--) {
1190 amr_intr(amr);
1191 if ((ac->ac_flags & AC_COMPLETE) != 0)
1192 break;
1193 DELAY(100);
1194 }
1195
1196 if (i == 0)
1197 printf("%s: polled operation timed out after %d ms\n",
1198 device_xname(amr->amr_dv), timo);
1199
1200 return ((i == 0 || ac->ac_status != 0) ? EIO : 0);
1201 }
1202
1203 /*
1204 * Submit a command to the controller and sleep on completion. Return
1205 * non-zero on error.
1206 */
1207 int
amr_ccb_wait(struct amr_softc * amr,struct amr_ccb * ac)1208 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac)
1209 {
1210 amr_ccb_enqueue(amr, ac);
1211 mutex_enter(&ac->ac_mutex);
1212 cv_wait(&ac->ac_cv, &ac->ac_mutex);
1213 mutex_exit(&ac->ac_mutex);
1214
1215 return (ac->ac_status != 0 ? EIO : 0);
1216 }
1217
1218 #if 0
1219 /*
1220 * Wait for the mailbox to become available.
1221 */
1222 static int
1223 amr_mbox_wait(struct amr_softc *amr)
1224 {
1225 int timo;
1226
1227 for (timo = 10000; timo != 0; timo--) {
1228 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1229 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1230 if (amr->amr_mbox->mb_cmd.mb_busy == 0)
1231 break;
1232 DELAY(100);
1233 }
1234
1235 if (timo == 0)
1236 printf("%s: controller wedged\n", device_xname(amr->amr_dv));
1237
1238 return (timo != 0 ? 0 : EAGAIN);
1239 }
1240 #endif
1241
1242 /*
1243 * Tell the controller that the mailbox contains a valid command. Must be
1244 * called with interrupts blocked.
1245 */
1246 static int
amr_quartz_submit(struct amr_softc * amr,struct amr_ccb * ac)1247 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac)
1248 {
1249 int i = 0;
1250 u_int32_t v;
1251
1252 amr->amr_mbox->mb_poll = 0;
1253 amr->amr_mbox->mb_ack = 0;
1254
1255 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1256 sizeof(struct amr_mailbox),
1257 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1258
1259 v = amr_inl(amr, AMR_QREG_ODB);
1260 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1261 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1262 while ((amr->amr_mbox->mb_cmd.mb_busy != 0) && (i++ < 10)) {
1263 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1264 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD);
1265 /* This is a no-op read that flushes pending mailbox updates */
1266 v = amr_inl(amr, AMR_QREG_ODB);
1267 DELAY(1);
1268 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1269 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1270 }
1271
1272 if (amr->amr_mbox->mb_cmd.mb_busy != 0)
1273 return (EAGAIN);
1274
1275 v = amr_inl(amr, AMR_QREG_IDB);
1276 if ((v & AMR_QIDB_SUBMIT) != 0) {
1277 amr->amr_mbox->mb_cmd.mb_busy = 0;
1278 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1279 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1280 printf("%s: submit failed\n", device_xname(amr->amr_dv));
1281 return (EAGAIN);
1282 }
1283
1284 amr->amr_mbox->mb_segment = 0;
1285 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd));
1286 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1287 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1288
1289 ac->ac_start_time = time_uptime;
1290 ac->ac_flags |= AC_ACTIVE;
1291
1292 amr_outl(amr, AMR_QREG_IDB,
1293 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT);
1294 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1295 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE);
1296
1297 return (0);
1298 }
1299
1300 static int
amr_std_submit(struct amr_softc * amr,struct amr_ccb * ac)1301 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac)
1302 {
1303
1304 amr->amr_mbox->mb_poll = 0;
1305 amr->amr_mbox->mb_ack = 0;
1306
1307 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1308 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1309
1310 if (amr->amr_mbox->mb_cmd.mb_busy != 0)
1311 return (EAGAIN);
1312
1313 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) {
1314 amr->amr_mbox->mb_cmd.mb_busy = 0;
1315 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1316 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1317 return (EAGAIN);
1318 }
1319
1320 amr->amr_mbox->mb_segment = 0;
1321 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd));
1322
1323 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1324 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1325
1326 ac->ac_start_time = time_uptime;
1327 ac->ac_flags |= AC_ACTIVE;
1328 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST);
1329
1330 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1331 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE);
1332
1333 return (0);
1334 }
1335
1336 /*
1337 * Claim any work that the controller has completed; acknowledge completion,
1338 * save details of the completion in (mbsave). Must be called with
1339 * interrupts blocked.
1340 */
1341 static int
amr_quartz_get_work(struct amr_softc * amr,struct amr_mailbox_resp * mbsave)1342 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave)
1343 {
1344 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1345 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD);
1346
1347 /* Work waiting for us? */
1348 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY)
1349 return (-1);
1350
1351 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1352 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1353
1354 /* Save the mailbox, which contains a list of completed commands. */
1355 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave));
1356
1357 /* Ack the interrupt and mailbox transfer. */
1358 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY);
1359 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK);
1360
1361 /*
1362 * This waits for the controller to notice that we've taken the
1363 * command from it. It's very inefficient, and we shouldn't do it,
1364 * but if we remove this code, we stop completing commands under
1365 * load.
1366 *
1367 * Peter J says we shouldn't do this. The documentation says we
1368 * should. Who is right?
1369 */
1370 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0)
1371 DELAY(10);
1372
1373 return (0);
1374 }
1375
1376 static int
amr_std_get_work(struct amr_softc * amr,struct amr_mailbox_resp * mbsave)1377 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave)
1378 {
1379 u_int8_t istat;
1380
1381 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1382 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD);
1383
1384 /* Check for valid interrupt status. */
1385 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0)
1386 return (-1);
1387
1388 /* Ack the interrupt. */
1389 amr_outb(amr, AMR_SREG_INTR, istat);
1390
1391 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1392 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1393
1394 /* Save mailbox, which contains a list of completed commands. */
1395 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave));
1396
1397 /* Ack mailbox transfer. */
1398 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR);
1399
1400 return (0);
1401 }
1402
1403 static void
amr_ccb_dump(struct amr_softc * amr,struct amr_ccb * ac)1404 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac)
1405 {
1406 int i;
1407
1408 printf("%s: ", device_xname(amr->amr_dv));
1409 for (i = 0; i < 4; i++)
1410 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]);
1411 printf("\n");
1412 }
1413
1414 static int
amropen(dev_t dev,int flag,int mode,struct lwp * l)1415 amropen(dev_t dev, int flag, int mode, struct lwp *l)
1416 {
1417 struct amr_softc *amr;
1418
1419 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL)
1420 return (ENXIO);
1421 if ((amr->amr_flags & AMRF_OPEN) != 0)
1422 return (EBUSY);
1423
1424 amr->amr_flags |= AMRF_OPEN;
1425 return (0);
1426 }
1427
1428 static int
amrclose(dev_t dev,int flag,int mode,struct lwp * l)1429 amrclose(dev_t dev, int flag, int mode, struct lwp *l)
1430 {
1431 struct amr_softc *amr;
1432
1433 amr = device_lookup_private(&amr_cd, minor(dev));
1434 amr->amr_flags &= ~AMRF_OPEN;
1435 return (0);
1436 }
1437
1438 /* used below to correct for a firmware bug */
1439 static unsigned long
amrioctl_buflen(unsigned long len)1440 amrioctl_buflen(unsigned long len)
1441 {
1442 if (len <= 4 * 1024)
1443 return (4 * 1024);
1444 if (len <= 8 * 1024)
1445 return (8 * 1024);
1446 if (len <= 32 * 1024)
1447 return (32 * 1024);
1448 if (len <= 64 * 1024)
1449 return (64 * 1024);
1450 return (len);
1451 }
1452
1453 static int
amrioctl(dev_t dev,u_long cmd,void * data,int flag,struct lwp * l)1454 amrioctl(dev_t dev, u_long cmd, void *data, int flag,
1455 struct lwp *l)
1456 {
1457 struct amr_softc *amr;
1458 struct amr_user_ioctl *au;
1459 struct amr_ccb *ac;
1460 struct amr_mailbox_ioctl *mbi;
1461 unsigned long au_length;
1462 uint8_t *au_cmd;
1463 int error;
1464 void *dp = NULL, *au_buffer;
1465
1466 amr = device_lookup_private(&amr_cd, minor(dev));
1467
1468 /* This should be compatible with the FreeBSD interface */
1469
1470 switch (cmd) {
1471 case AMR_IO_VERSION:
1472 *(int *)data = AMR_IO_VERSION_NUMBER;
1473 return 0;
1474 case AMR_IO_COMMAND:
1475 error = kauth_authorize_device_passthru(l->l_cred, dev,
1476 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data);
1477 if (error)
1478 return (error);
1479
1480 au = (struct amr_user_ioctl *)data;
1481 au_cmd = au->au_cmd;
1482 au_buffer = au->au_buffer;
1483 au_length = au->au_length;
1484 break;
1485 default:
1486 return ENOTTY;
1487 }
1488
1489 if (au_cmd[0] == AMR_CMD_PASS) {
1490 /* not yet */
1491 return EOPNOTSUPP;
1492 }
1493
1494 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06)
1495 return (EINVAL);
1496
1497 /*
1498 * allocate kernel memory for data, doing I/O directly to user
1499 * buffer isn't that easy. Correct allocation size for a bug
1500 * in at least some versions of the device firmware, by using
1501 * the amrioctl_buflen() function, defined above.
1502 */
1503 dp = malloc(amrioctl_buflen(au_length), M_DEVBUF, M_WAITOK|M_ZERO);
1504 if (dp == NULL)
1505 return ENOMEM;
1506 if ((error = copyin(au_buffer, dp, au_length)) != 0)
1507 goto out;
1508
1509 /* direct command to controller */
1510 while (amr_ccb_alloc(amr, &ac) != 0) {
1511 mutex_enter(&thread_mutex);
1512 error = cv_timedwait_sig(&thread_cv, &thread_mutex, hz);
1513 mutex_exit(&thread_mutex);
1514 if (error == EINTR)
1515 goto out;
1516 }
1517
1518 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd;
1519 mbi->mb_command = au_cmd[0];
1520 mbi->mb_channel = au_cmd[1];
1521 mbi->mb_param = au_cmd[2];
1522 mbi->mb_pad[0] = au_cmd[3];
1523 mbi->mb_drive = au_cmd[4];
1524 error = amr_ccb_map(amr, ac, dp, (int)au_length,
1525 AC_XFER_IN | AC_XFER_OUT);
1526 if (error == 0) {
1527 error = amr_ccb_wait(amr, ac);
1528 amr_ccb_unmap(amr, ac);
1529 if (error == 0)
1530 error = copyout(dp, au_buffer, au_length);
1531
1532 }
1533 amr_ccb_free(amr, ac);
1534 out:
1535 free(dp, M_DEVBUF);
1536 return (error);
1537 }
1538