1 /*-
2 * Copyright (c) 2013 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas of 3am Software Foundry.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include "opt_multiprocessor.h"
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(1, "$NetBSD: arm32_tlb.c,v 1.10 2016/07/11 16:09:27 matt Exp $");
34
35 #include <sys/param.h>
36 #include <sys/types.h>
37
38 #include <uvm/uvm.h>
39
40 #include <arm/locore.h>
41
42 bool arm_has_tlbiasid_p; // CPU supports TLBIASID system coprocessor op
43
44 tlb_asid_t
tlb_get_asid(void)45 tlb_get_asid(void)
46 {
47 return armreg_contextidr_read() & 0xff;
48 }
49
50 void
tlb_set_asid(tlb_asid_t asid)51 tlb_set_asid(tlb_asid_t asid)
52 {
53 arm_dsb();
54 if (asid == KERNEL_PID) {
55 armreg_ttbcr_write(armreg_ttbcr_read() | TTBCR_S_PD0);
56 arm_isb();
57 }
58 armreg_contextidr_write(asid);
59 arm_isb();
60 }
61
62 void
tlb_invalidate_all(void)63 tlb_invalidate_all(void)
64 {
65 const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
66 arm_dsb();
67 #ifdef MULTIPROCESSOR
68 armreg_tlbiallis_write(0);
69 #else
70 armreg_tlbiall_write(0);
71 #endif
72 arm_isb();
73 if (__predict_false(vivt_icache_p)) {
74 if (arm_has_tlbiasid_p) {
75 armreg_icialluis_write(0);
76 } else {
77 armreg_iciallu_write(0);
78 }
79 }
80 arm_dsb();
81 arm_isb();
82 }
83
84 void
tlb_invalidate_globals(void)85 tlb_invalidate_globals(void)
86 {
87 tlb_invalidate_all();
88 }
89
90 void
tlb_invalidate_asids(tlb_asid_t lo,tlb_asid_t hi)91 tlb_invalidate_asids(tlb_asid_t lo, tlb_asid_t hi)
92 {
93 const bool vivt_icache_p = arm_pcache.icache_type == CACHE_TYPE_VIVT;
94 arm_dsb();
95 if (arm_has_tlbiasid_p) {
96 for (; lo <= hi; lo++) {
97 #ifdef MULTIPROCESSOR
98 armreg_tlbiasidis_write(lo);
99 #else
100 armreg_tlbiasid_write(lo);
101 #endif
102 }
103 arm_dsb();
104 arm_isb();
105 if (__predict_false(vivt_icache_p)) {
106 #ifdef MULTIPROCESSOR
107 armreg_icialluis_write(0);
108 #else
109 armreg_iciallu_write(0);
110 #endif
111 }
112 } else {
113 armreg_tlbiall_write(0);
114 arm_isb();
115 if (__predict_false(vivt_icache_p)) {
116 armreg_iciallu_write(0);
117 }
118 }
119 arm_isb();
120 }
121
122 void
tlb_invalidate_addr(vaddr_t va,tlb_asid_t asid)123 tlb_invalidate_addr(vaddr_t va, tlb_asid_t asid)
124 {
125 arm_dsb();
126 va = trunc_page(va) | asid;
127 for (vaddr_t eva = va + PAGE_SIZE; va < eva; va += L2_S_SIZE) {
128 #ifdef MULTIPROCESSOR
129 armreg_tlbimvais_write(va);
130 #else
131 armreg_tlbimva_write(va);
132 #endif
133 //armreg_tlbiall_write(asid);
134 }
135 arm_isb();
136 }
137
138 bool
tlb_update_addr(vaddr_t va,tlb_asid_t asid,pt_entry_t pte,bool insert_p)139 tlb_update_addr(vaddr_t va, tlb_asid_t asid, pt_entry_t pte, bool insert_p)
140 {
141 tlb_invalidate_addr(va, asid);
142 return true;
143 }
144
145 #if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA5)
146 static u_int
tlb_cortex_a5_record_asids(u_long * mapp,tlb_asid_t asid_max)147 tlb_cortex_a5_record_asids(u_long *mapp, tlb_asid_t asid_max)
148 {
149 u_int nasids = 0;
150 for (size_t va_index = 0; va_index < 63; va_index++) {
151 for (size_t way = 0; way < 2; way++) {
152 armreg_tlbdataop_write(
153 __SHIFTIN(way, ARM_TLBDATAOP_WAY)
154 | __SHIFTIN(va_index, ARM_A5_TLBDATAOP_INDEX));
155 arm_isb();
156 const uint64_t d = ((uint64_t) armreg_tlbdata1_read())
157 | armreg_tlbdata0_read();
158 if (!(d & ARM_TLBDATA_VALID)
159 || !(d & ARM_A5_TLBDATA_nG))
160 continue;
161
162 const tlb_asid_t asid = __SHIFTOUT(d,
163 ARM_A5_TLBDATA_ASID);
164 const u_long mask = 1L << (asid & 31);
165 const size_t idx = asid >> 5;
166 if (mapp[idx] & mask)
167 continue;
168
169 mapp[idx] |= mask;
170 nasids++;
171 }
172 }
173 return nasids;
174 }
175 #endif
176
177 #if !defined(MULTIPROCESSOR) && defined(CPU_CORTEXA7)
178 static u_int
tlb_cortex_a7_record_asids(u_long * mapp,tlb_asid_t asid_max)179 tlb_cortex_a7_record_asids(u_long *mapp, tlb_asid_t asid_max)
180 {
181 u_int nasids = 0;
182 for (size_t va_index = 0; va_index < 128; va_index++) {
183 for (size_t way = 0; way < 2; way++) {
184 armreg_tlbdataop_write(
185 __SHIFTIN(way, ARM_TLBDATAOP_WAY)
186 | __SHIFTIN(va_index, ARM_A7_TLBDATAOP_INDEX));
187 arm_isb();
188 const uint32_t d0 = armreg_tlbdata0_read();
189 const uint32_t d1 = armreg_tlbdata1_read();
190 if (!(d0 & ARM_TLBDATA_VALID)
191 || !(d1 & ARM_A7_TLBDATA1_nG))
192 continue;
193
194 const uint64_t d01 = ((uint64_t) d1)|d0;
195 const tlb_asid_t asid = __SHIFTOUT(d01,
196 ARM_A7_TLBDATA01_ASID);
197 const u_long mask = 1L << (asid & 31);
198 const size_t idx = asid >> 5;
199 if (mapp[idx] & mask)
200 continue;
201
202 mapp[idx] |= mask;
203 nasids++;
204 }
205 }
206 return nasids;
207 }
208 #endif
209
210 u_int
tlb_record_asids(u_long * mapp,tlb_asid_t asid_max)211 tlb_record_asids(u_long *mapp, tlb_asid_t asid_max)
212 {
213 #ifndef MULTIPROCESSOR
214 #ifdef CPU_CORTEXA5
215 if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
216 return tlb_cortex_a5_record_asids(mapp, asid_max);
217 #endif
218 #ifdef CPU_CORTEXA7
219 if (CPU_ID_CORTEX_A7_P(curcpu()->ci_arm_cpuid))
220 return tlb_cortex_a7_record_asids(mapp, asid_max);
221 #endif
222 #endif /* MULTIPROCESSOR */
223 #ifdef DIAGNOSTIC
224 mapp[0] = 0xfffffffe;
225 mapp[1] = 0xffffffff;
226 mapp[2] = 0xffffffff;
227 mapp[3] = 0xffffffff;
228 mapp[4] = 0xffffffff;
229 mapp[5] = 0xffffffff;
230 mapp[6] = 0xffffffff;
231 mapp[7] = 0xffffffff;
232 #endif
233 return 255;
234 }
235
236 void
tlb_walk(void * ctx,bool (* func)(void *,vaddr_t,tlb_asid_t,pt_entry_t))237 tlb_walk(void *ctx, bool (*func)(void *, vaddr_t, tlb_asid_t, pt_entry_t))
238 {
239 /* no way to view the TLB */
240 }
241