1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Contact Information :
28 * Rajesh Kumar <rajesh1.kumar@amd.com>
29 * Shreyank Amartya <Shreyank.Amartya@amd.com>
30 */
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/rman.h>
39 #include <sys/smp.h>
40 #include <sys/socket.h>
41 #include <sys/sysctl.h>
42 #include <sys/systm.h>
43
44 #include <net/if.h>
45 #include <net/if_media.h>
46
47 #include <dev/mii/mii.h>
48 #include <dev/mii/miivar.h>
49
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52
53 #include "xgbe.h"
54 #include "xgbe-common.h"
55
56 #include "miibus_if.h"
57 #include "ifdi_if.h"
58 #include "opt_inet.h"
59 #include "opt_inet6.h"
60 #include "opt_rss.h"
61
62 #ifdef RSS
63 #include <net/rss_config.h>
64 #include <netinet/in_rss.h>
65 #endif
66
67 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
68
69 extern struct if_txrx axgbe_txrx;
70 static int axgbe_sph_enable;
71
72 /* Function prototypes */
73 static void *axgbe_register(device_t);
74 static int axgbe_if_attach_pre(if_ctx_t);
75 static int axgbe_if_attach_post(if_ctx_t);
76 static int axgbe_if_detach(if_ctx_t);
77 static void axgbe_if_stop(if_ctx_t);
78 static void axgbe_if_init(if_ctx_t);
79
80 /* Queue related routines */
81 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
82 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
83 static int axgbe_alloc_channels(if_ctx_t);
84 static void axgbe_free_channels(struct axgbe_if_softc *);
85 static void axgbe_if_queues_free(if_ctx_t);
86 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
87 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
88
89 /* Interrupt related routines */
90 static void axgbe_if_disable_intr(if_ctx_t);
91 static void axgbe_if_enable_intr(if_ctx_t);
92 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
93 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
94
95 /* Init and Iflib routines */
96 static void axgbe_pci_init(struct xgbe_prv_data *);
97 static void axgbe_pci_stop(if_ctx_t);
98 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
99 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
100 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
101 static void axgbe_if_update_admin_status(if_ctx_t);
102 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
103 static int axgbe_if_media_change(if_ctx_t);
104 static int axgbe_if_promisc_set(if_ctx_t, int);
105 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
106 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
107 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
108 #if __FreeBSD_version >= 1300000
109 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
110 #endif
111 static void axgbe_set_counts(if_ctx_t);
112 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
113 static void axgbe_initialize_rss_mapping(struct xgbe_prv_data *);
114
115 /* MII interface registered functions */
116 static int axgbe_miibus_readreg(device_t, int, int);
117 static int axgbe_miibus_writereg(device_t, int, int, int);
118 static void axgbe_miibus_statchg(device_t);
119
120 /* ISR routines */
121 static int axgbe_dev_isr(void *);
122 static void axgbe_ecc_isr(void *);
123 static void axgbe_i2c_isr(void *);
124 static void axgbe_an_isr(void *);
125 static int axgbe_msix_que(void *);
126
127 /* Timer routines */
128 static void xgbe_service(void *, int);
129 static void xgbe_service_timer(void *);
130 static void xgbe_init_timers(struct xgbe_prv_data *);
131 static void xgbe_stop_timers(struct xgbe_prv_data *);
132
133 /* Dump routines */
134 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
135
136 /*
137 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
138 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
139 * table.
140 */
141 static struct resource_spec axgbe_pci_mac_spec[] = {
142 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
143 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
144 { -1, 0 }
145 };
146
147 static const pci_vendor_info_t axgbe_vendor_info_array[] =
148 {
149 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
150 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
151 PVID_END
152 };
153
154 static struct xgbe_version_data xgbe_v2a = {
155 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
156 .xpcs_access = XGBE_XPCS_ACCESS_V2,
157 .mmc_64bit = 1,
158 .tx_max_fifo_size = 229376,
159 .rx_max_fifo_size = 229376,
160 .tx_tstamp_workaround = 1,
161 .ecc_support = 1,
162 .i2c_support = 1,
163 .irq_reissue_support = 1,
164 .tx_desc_prefetch = 5,
165 .rx_desc_prefetch = 5,
166 .an_cdr_workaround = 1,
167 };
168
169 static struct xgbe_version_data xgbe_v2b = {
170 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
171 .xpcs_access = XGBE_XPCS_ACCESS_V2,
172 .mmc_64bit = 1,
173 .tx_max_fifo_size = 65536,
174 .rx_max_fifo_size = 65536,
175 .tx_tstamp_workaround = 1,
176 .ecc_support = 1,
177 .i2c_support = 1,
178 .irq_reissue_support = 1,
179 .tx_desc_prefetch = 5,
180 .rx_desc_prefetch = 5,
181 .an_cdr_workaround = 1,
182 };
183
184 /* Device Interface */
185 static device_method_t ax_methods[] = {
186 DEVMETHOD(device_register, axgbe_register),
187 DEVMETHOD(device_probe, iflib_device_probe),
188 DEVMETHOD(device_attach, iflib_device_attach),
189 DEVMETHOD(device_detach, iflib_device_detach),
190
191 /* MII interface */
192 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
193 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
194 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
195
196 DEVMETHOD_END
197 };
198
199 static driver_t ax_driver = {
200 "ax", ax_methods, sizeof(struct axgbe_if_softc),
201 };
202
203 DRIVER_MODULE(axp, pci, ax_driver, 0, 0);
204 DRIVER_MODULE(miibus, ax, miibus_driver, 0, 0);
205 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
206
207 MODULE_DEPEND(ax, pci, 1, 1, 1);
208 MODULE_DEPEND(ax, ether, 1, 1, 1);
209 MODULE_DEPEND(ax, iflib, 1, 1, 1);
210 MODULE_DEPEND(ax, miibus, 1, 1, 1);
211
212 /* Iflib Interface */
213 static device_method_t axgbe_if_methods[] = {
214 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
215 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
216 DEVMETHOD(ifdi_detach, axgbe_if_detach),
217 DEVMETHOD(ifdi_init, axgbe_if_init),
218 DEVMETHOD(ifdi_stop, axgbe_if_stop),
219 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
220 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
221 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
222 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
223 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
224 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
225 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
226 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
227 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
228 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
229 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
230 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
231 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
232 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
233 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
234 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
235 #if __FreeBSD_version >= 1300000
236 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
237 #endif
238 DEVMETHOD_END
239 };
240
241 static driver_t axgbe_if_driver = {
242 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
243 };
244
245 /* Iflib Shared Context */
246 static struct if_shared_ctx axgbe_sctx_init = {
247 .isc_magic = IFLIB_MAGIC,
248 .isc_driver = &axgbe_if_driver,
249 .isc_q_align = PAGE_SIZE,
250 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
251 .isc_tx_maxsegsize = PAGE_SIZE,
252 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
253 .isc_tso_maxsegsize = PAGE_SIZE,
254 .isc_rx_maxsize = MJUM9BYTES,
255 .isc_rx_maxsegsize = MJUM9BYTES,
256 .isc_rx_nsegments = 1,
257 .isc_admin_intrcnt = 4,
258
259 .isc_vendor_info = axgbe_vendor_info_array,
260 .isc_driver_version = XGBE_DRV_VERSION,
261
262 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
263 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
264 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
265
266 .isc_ntxqs = 1,
267 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
268 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
269 };
270
271 static void *
axgbe_register(device_t dev)272 axgbe_register(device_t dev)
273 {
274 int axgbe_nfl;
275 int axgbe_nrxqs;
276 int error, i;
277 char *value = NULL;
278
279 value = kern_getenv("dev.ax.sph_enable");
280 if (value) {
281 axgbe_sph_enable = strtol(value, NULL, 10);
282 freeenv(value);
283 } else {
284 /*
285 * No tunable found, generate one with default values
286 * Note: only a reboot will reveal the new kenv
287 */
288 error = kern_setenv("dev.ax.sph_enable", "0");
289 if (error) {
290 printf("Error setting tunable, using default driver values\n");
291 }
292 axgbe_sph_enable = 0;
293 }
294
295 if (!axgbe_sph_enable) {
296 axgbe_nfl = 1;
297 axgbe_nrxqs = 1;
298 } else {
299 axgbe_nfl = 2;
300 axgbe_nrxqs = 2;
301 }
302
303 axgbe_sctx_init.isc_nfl = axgbe_nfl;
304 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs;
305
306 for (i = 0 ; i < axgbe_nrxqs ; i++) {
307 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN;
308 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT;
309 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX;
310 }
311
312 return (&axgbe_sctx_init);
313 }
314
315 /* MII Interface Functions */
316 static int
axgbe_miibus_readreg(device_t dev,int phy,int reg)317 axgbe_miibus_readreg(device_t dev, int phy, int reg)
318 {
319 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
320 struct xgbe_prv_data *pdata = &sc->pdata;
321 int val;
322
323 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
324
325 val = xgbe_phy_mii_read(pdata, phy, reg);
326
327 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
328 return (val & 0xFFFF);
329 }
330
331 static int
axgbe_miibus_writereg(device_t dev,int phy,int reg,int val)332 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
333 {
334 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
335 struct xgbe_prv_data *pdata = &sc->pdata;
336
337 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
338
339 xgbe_phy_mii_write(pdata, phy, reg, val);
340
341 return(0);
342 }
343
344 static void
axgbe_miibus_statchg(device_t dev)345 axgbe_miibus_statchg(device_t dev)
346 {
347 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
348 struct xgbe_prv_data *pdata = &sc->pdata;
349 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
350 if_t ifp = pdata->netdev;
351 int bmsr;
352
353 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
354 pdata->phy_link);
355
356 if (mii == NULL || ifp == NULL ||
357 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
358 return;
359
360 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
361 (IFM_ACTIVE | IFM_AVALID)) {
362
363 switch (IFM_SUBTYPE(mii->mii_media_active)) {
364 case IFM_10_T:
365 case IFM_100_TX:
366 pdata->phy.link = 1;
367 break;
368 case IFM_1000_T:
369 case IFM_1000_SX:
370 case IFM_2500_SX:
371 pdata->phy.link = 1;
372 break;
373 default:
374 pdata->phy.link = 0;
375 break;
376 }
377 } else
378 pdata->phy_link = 0;
379
380 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
381 if (bmsr & BMSR_ANEG) {
382
383 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
384
385 /* Raise AN Interrupt */
386 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
387 XGBE_AN_CL73_INT_MASK);
388 }
389 }
390
391 static int
axgbe_if_attach_pre(if_ctx_t ctx)392 axgbe_if_attach_pre(if_ctx_t ctx)
393 {
394 struct axgbe_if_softc *sc;
395 struct xgbe_prv_data *pdata;
396 struct resource *mac_res[2];
397 if_softc_ctx_t scctx;
398 if_shared_ctx_t sctx;
399 device_t dev;
400 device_t rdev;
401 unsigned int ma_lo, ma_hi;
402 unsigned int reg;
403 int ret;
404
405 sc = iflib_get_softc(ctx);
406 sc->pdata.dev = dev = iflib_get_dev(ctx);
407 sc->sctx = sctx = iflib_get_sctx(ctx);
408 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
409 sc->media = iflib_get_media(ctx);
410 sc->ctx = ctx;
411 sc->link_status = LINK_STATE_DOWN;
412 pdata = &sc->pdata;
413 pdata->netdev = iflib_get_ifp(ctx);
414
415 spin_lock_init(&pdata->xpcs_lock);
416
417 /* Initialize locks */
418 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
419 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
420
421 /* Allocate VLAN bitmap */
422 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
423 pdata->num_active_vlans = 0;
424
425 /* Get the version data */
426 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
427 if (pci_get_device(dev) == 0x1458)
428 sc->pdata.vdata = &xgbe_v2a;
429 else if (pci_get_device(dev) == 0x1459)
430 sc->pdata.vdata = &xgbe_v2b;
431
432 /* PCI setup */
433 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) {
434 axgbe_error("Unable to allocate bus resources\n");
435 ret = ENXIO;
436 goto free_vlans;
437 }
438
439 sc->pdata.xgmac_res = mac_res[0];
440 sc->pdata.xpcs_res = mac_res[1];
441
442 /*
443 * Set the PCS indirect addressing definition registers.
444 * A newer version of the hardware is using the same PCI ids
445 * for the network device but has altered register definitions
446 * for determining the window settings for the indirect PCS access.
447 * This code checks hardware usage and uses the register values
448 * accordingly.
449 */
450 rdev = pci_find_dbsf(0, 0, 0, 0);
451 if (rdev && pci_get_device(rdev) == 0x15d0
452 && pci_get_vendor(rdev) == 0x1022) {
453 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
454 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
455 } else {
456 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
457 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
458 }
459
460 /* Configure the PCS indirect addressing support */
461 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
462 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
463 pdata->xpcs_window <<= 6;
464 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
465 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
466 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
467 DBGPR("xpcs window def : %#010x\n",
468 pdata->xpcs_window_def_reg);
469 DBGPR("xpcs window sel : %#010x\n",
470 pdata->xpcs_window_sel_reg);
471 DBGPR("xpcs window : %#010x\n",
472 pdata->xpcs_window);
473 DBGPR("xpcs window size : %#010x\n",
474 pdata->xpcs_window_size);
475 DBGPR("xpcs window mask : %#010x\n",
476 pdata->xpcs_window_mask);
477
478 /* Enable all interrupts in the hardware */
479 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
480
481 /* Retrieve the MAC address */
482 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
483 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
484 pdata->mac_addr[0] = ma_lo & 0xff;
485 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
486 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
487 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
488 pdata->mac_addr[4] = ma_hi & 0xff;
489 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
490 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
491 axgbe_error("Invalid mac address\n");
492 ret = EINVAL;
493 goto release_bus_resource;
494 }
495 iflib_set_mac(ctx, pdata->mac_addr);
496
497 /* Clock settings */
498 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
499 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
500
501 /* Set the DMA coherency values */
502 pdata->coherent = 1;
503 pdata->arcr = XGBE_DMA_PCI_ARCR;
504 pdata->awcr = XGBE_DMA_PCI_AWCR;
505 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
506
507 /* Read the port property registers */
508 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
509 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
510 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
511 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
512 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
513 DBGPR("port property 0 = %#010x\n", pdata->pp0);
514 DBGPR("port property 1 = %#010x\n", pdata->pp1);
515 DBGPR("port property 2 = %#010x\n", pdata->pp2);
516 DBGPR("port property 3 = %#010x\n", pdata->pp3);
517 DBGPR("port property 4 = %#010x\n", pdata->pp4);
518
519 /* Set the maximum channels and queues */
520 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
521 MAX_TX_DMA);
522 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
523 MAX_RX_DMA);
524 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
525 MAX_TX_QUEUES);
526 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
527 MAX_RX_QUEUES);
528 DBGPR("max tx/rx channel count = %u/%u\n",
529 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
530 DBGPR("max tx/rx hw queue count = %u/%u\n",
531 pdata->tx_max_q_count, pdata->rx_max_q_count);
532
533 axgbe_set_counts(ctx);
534
535 /* Set the maximum fifo amounts */
536 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
537 TX_FIFO_SIZE);
538 pdata->tx_max_fifo_size *= 16384;
539 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
540 pdata->vdata->tx_max_fifo_size);
541 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
542 RX_FIFO_SIZE);
543 pdata->rx_max_fifo_size *= 16384;
544 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
545 pdata->vdata->rx_max_fifo_size);
546 DBGPR("max tx/rx max fifo size = %u/%u\n",
547 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
548
549 /* Initialize IFLIB if_softc_ctx_t */
550 axgbe_init_iflib_softc_ctx(sc);
551
552 /* Alloc channels */
553 if (axgbe_alloc_channels(ctx)) {
554 axgbe_error("Unable to allocate channel memory\n");
555 ret = ENOMEM;
556 goto release_bus_resource;
557 }
558
559 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
560
561 /* create the workqueue */
562 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
563 taskqueue_thread_enqueue, &pdata->dev_workqueue);
564 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
565 "axgbe dev taskq");
566 if (ret) {
567 axgbe_error("Unable to start taskqueue\n");
568 ret = ENOMEM;
569 goto free_task_queue;
570 }
571
572 /* Init timers */
573 xgbe_init_timers(pdata);
574
575 return (0);
576
577 free_task_queue:
578 taskqueue_free(pdata->dev_workqueue);
579 axgbe_free_channels(sc);
580
581 release_bus_resource:
582 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res);
583
584 free_vlans:
585 free(pdata->active_vlans, M_AXGBE);
586
587 return (ret);
588 } /* axgbe_if_attach_pre */
589
590 static void
xgbe_init_all_fptrs(struct xgbe_prv_data * pdata)591 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
592 {
593 xgbe_init_function_ptrs_dev(&pdata->hw_if);
594 xgbe_init_function_ptrs_phy(&pdata->phy_if);
595 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
596 xgbe_init_function_ptrs_desc(&pdata->desc_if);
597
598 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
599 }
600
601 static void
axgbe_set_counts(if_ctx_t ctx)602 axgbe_set_counts(if_ctx_t ctx)
603 {
604 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
605 struct xgbe_prv_data *pdata = &sc->pdata;
606 cpuset_t lcpus;
607
608 /* Set all function pointers */
609 xgbe_init_all_fptrs(pdata);
610
611 /* Populate the hardware features */
612 xgbe_get_all_hw_features(pdata);
613
614 if (!pdata->tx_max_channel_count)
615 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
616 if (!pdata->rx_max_channel_count)
617 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
618
619 if (!pdata->tx_max_q_count)
620 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
621 if (!pdata->rx_max_q_count)
622 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
623
624 /*
625 * Calculate the number of Tx and Rx rings to be created
626 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
627 * the number of Tx queues to the number of Tx channels
628 * enabled
629 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
630 * number of Rx queues or maximum allowed
631 */
632
633 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
634 axgbe_error("Unable to fetch CPU list\n");
635 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
636 }
637
638 DBGPR("ncpu %d intrcpu %d\n", mp_ncpus, CPU_COUNT(&lcpus));
639
640 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
641 pdata->tx_ring_count = min(pdata->tx_ring_count,
642 pdata->tx_max_channel_count);
643 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
644
645 pdata->tx_q_count = pdata->tx_ring_count;
646
647 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
648 pdata->rx_ring_count = min(pdata->rx_ring_count,
649 pdata->rx_max_channel_count);
650
651 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
652
653 DBGPR("TX/RX max channel count = %u/%u\n",
654 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
655 DBGPR("TX/RX max queue count = %u/%u\n",
656 pdata->tx_max_q_count, pdata->rx_max_q_count);
657 DBGPR("TX/RX DMA ring count = %u/%u\n",
658 pdata->tx_ring_count, pdata->rx_ring_count);
659 DBGPR("TX/RX hardware queue count = %u/%u\n",
660 pdata->tx_q_count, pdata->rx_q_count);
661 } /* axgbe_set_counts */
662
663 static void
axgbe_init_iflib_softc_ctx(struct axgbe_if_softc * sc)664 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
665 {
666 struct xgbe_prv_data *pdata = &sc->pdata;
667 if_softc_ctx_t scctx = sc->scctx;
668 if_shared_ctx_t sctx = sc->sctx;
669 int i;
670
671 scctx->isc_nrxqsets = pdata->rx_q_count;
672 scctx->isc_ntxqsets = pdata->tx_q_count;
673 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
674 scctx->isc_tx_nsegments = 32;
675
676 for (i = 0; i < sctx->isc_ntxqs; i++) {
677 scctx->isc_txqsizes[i] =
678 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
679 128);
680 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
681 }
682
683 for (i = 0; i < sctx->isc_nrxqs; i++) {
684 scctx->isc_rxqsizes[i] =
685 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
686 128);
687 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
688 }
689
690 scctx->isc_tx_tso_segments_max = 32;
691 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
692 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
693
694 /*
695 * Set capabilities
696 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
697 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
698 * IFCAP_HWCSUM) is set
699 */
700 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
701 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
702 CSUM_TSO);
703 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
704 IFCAP_JUMBO_MTU |
705 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
706 IFCAP_VLAN_HWCSUM |
707 IFCAP_TSO | IFCAP_VLAN_HWTSO);
708 scctx->isc_capabilities = scctx->isc_capenable;
709
710 /*
711 * Set rss_table_size alone when adding RSS support. rss_table_mask
712 * will be set by IFLIB based on rss_table_size
713 */
714 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
715
716 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
717 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
718
719 scctx->isc_txrx = &axgbe_txrx;
720 }
721
722 static void
axgbe_initialize_rss_mapping(struct xgbe_prv_data * pdata)723 axgbe_initialize_rss_mapping(struct xgbe_prv_data *pdata)
724 {
725 int i;
726
727 /* Get RSS key */
728 #ifdef RSS
729 int qid;
730 uint32_t rss_hash_config = 0;
731
732 rss_getkey((uint8_t *)&pdata->rss_key);
733
734 rss_hash_config = rss_gethashconfig();
735
736 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
737 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
738 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
739 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
740 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
741 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
742 #else
743 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
744
745 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
746 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
747 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
748 #endif
749
750 /* Setup RSS lookup table */
751 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) {
752 #ifdef RSS
753 qid = rss_get_indirection_to_bucket(i) % pdata->rx_ring_count;
754 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, qid);
755 #else
756 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
757 i % pdata->rx_ring_count);
758 #endif
759 }
760
761 }
762
763 static int
axgbe_alloc_channels(if_ctx_t ctx)764 axgbe_alloc_channels(if_ctx_t ctx)
765 {
766 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
767 struct xgbe_prv_data *pdata = &sc->pdata;
768 struct xgbe_channel *channel;
769 int i, j, count;
770
771 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
772 pdata->rx_ring_count);
773
774 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
775 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
776
777 /* Allocate channel memory */
778 for (i = 0; i < count ; i++) {
779 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
780 M_AXGBE, M_NOWAIT | M_ZERO);
781
782 if (channel == NULL) {
783 for (j = 0; j < i; j++) {
784 free(pdata->channel[j], M_AXGBE);
785 pdata->channel[j] = NULL;
786 }
787 return (ENOMEM);
788 }
789
790 pdata->channel[i] = channel;
791 }
792
793 pdata->total_channel_count = count;
794 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
795
796 for (i = 0; i < count; i++) {
797
798 channel = pdata->channel[i];
799 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
800
801 channel->pdata = pdata;
802 channel->queue_index = i;
803 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
804 bus_space_subregion(channel->dma_tag,
805 rman_get_bushandle(pdata->xgmac_res),
806 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
807 &channel->dma_handle);
808 channel->tx_ring = NULL;
809 channel->rx_ring = NULL;
810 }
811
812 return (0);
813 } /* axgbe_alloc_channels */
814
815 static void
axgbe_free_channels(struct axgbe_if_softc * sc)816 axgbe_free_channels(struct axgbe_if_softc *sc)
817 {
818 struct xgbe_prv_data *pdata = &sc->pdata;
819 int i;
820
821 for (i = 0; i < pdata->total_channel_count ; i++) {
822 free(pdata->channel[i], M_AXGBE);
823 pdata->channel[i] = NULL;
824 }
825
826 pdata->total_channel_count = 0;
827 pdata->channel_count = 0;
828 }
829
830 static void
xgbe_service(void * ctx,int pending)831 xgbe_service(void *ctx, int pending)
832 {
833 struct xgbe_prv_data *pdata = ctx;
834 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
835 bool prev_state = false;
836
837 /* Get previous link status */
838 prev_state = pdata->phy.link;
839
840 pdata->phy_if.phy_status(pdata);
841
842 if (prev_state != pdata->phy.link) {
843 pdata->phy_link = pdata->phy.link;
844 axgbe_if_update_admin_status(sc->ctx);
845 }
846
847 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
848 }
849
850 static void
xgbe_service_timer(void * data)851 xgbe_service_timer(void *data)
852 {
853 struct xgbe_prv_data *pdata = data;
854
855 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
856 }
857
858 static void
xgbe_init_timers(struct xgbe_prv_data * pdata)859 xgbe_init_timers(struct xgbe_prv_data *pdata)
860 {
861 callout_init(&pdata->service_timer, 1);
862 }
863
864 static void
xgbe_start_timers(struct xgbe_prv_data * pdata)865 xgbe_start_timers(struct xgbe_prv_data *pdata)
866 {
867 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
868 }
869
870 static void
xgbe_stop_timers(struct xgbe_prv_data * pdata)871 xgbe_stop_timers(struct xgbe_prv_data *pdata)
872 {
873 callout_drain(&pdata->service_timer);
874 callout_stop(&pdata->service_timer);
875 }
876
877 static void
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)878 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
879 {
880 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
881
882 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
883 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
884 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
885 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
886 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
887 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
888 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
889 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
890 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
891 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
892 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
893 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
894 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
895 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
896 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
897 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
898 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
899 MDIO_AN_ADVERTISE,
900 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
901 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
902 MDIO_AN_ADVERTISE + 1,
903 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
904 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
905 MDIO_AN_ADVERTISE + 2,
906 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
907 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
908 MDIO_AN_COMP_STAT,
909 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
910
911 axgbe_printf(1, "\n************************************************\n");
912 }
913
914 static void
xgbe_dump_prop_registers(struct xgbe_prv_data * pdata)915 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
916 {
917 int i;
918
919 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
920
921 for (i = 0 ; i < 38 ; i++) {
922 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
923 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
924 (XP_PROP_0 + (i * 4))));
925 }
926 }
927
928 static void
xgbe_dump_dma_registers(struct xgbe_prv_data * pdata,int ch)929 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
930 {
931 struct xgbe_channel *channel;
932 int i;
933
934 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
935
936 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
937 XGMAC_IOREAD(pdata, DMA_MR));
938 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
939 XGMAC_IOREAD(pdata, DMA_SBMR));
940 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
941 XGMAC_IOREAD(pdata, DMA_ISR));
942 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
943 XGMAC_IOREAD(pdata, DMA_AXIARCR));
944 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
945 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
946 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
947 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
948 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
949 XGMAC_IOREAD(pdata, DMA_DSR0));
950 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
951 XGMAC_IOREAD(pdata, DMA_DSR1));
952 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
953 XGMAC_IOREAD(pdata, DMA_DSR2));
954 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
955 XGMAC_IOREAD(pdata, DMA_DSR3));
956 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
957 XGMAC_IOREAD(pdata, DMA_DSR4));
958 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
959 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
960 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
961 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
962
963 for (i = 0 ; i < 8 ; i++ ) {
964
965 if (ch >= 0) {
966 if (i != ch)
967 continue;
968 }
969
970 channel = pdata->channel[i];
971
972 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
973
974 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
975 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
976 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
977 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
978 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
979 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
980 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
981 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
982 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
983 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
984 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
985 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
986 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
987 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
988 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
989 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
990 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
991 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
992 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
993 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
994 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
995 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
996 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
997 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
998 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
999 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
1000 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
1001 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
1002 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
1003 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
1004 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
1005 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
1006 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
1007 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
1008 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
1009 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
1010 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
1011 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
1012 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
1013 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
1014 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
1015 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
1016 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
1017 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
1018 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
1019 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
1020 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
1021 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
1022 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
1023 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
1024 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
1025 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
1026 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
1027 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
1028 }
1029 }
1030
1031 static void
xgbe_dump_mtl_registers(struct xgbe_prv_data * pdata)1032 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
1033 {
1034 int i;
1035
1036 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
1037
1038 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
1039 XGMAC_IOREAD(pdata, MTL_OMR));
1040 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
1041 XGMAC_IOREAD(pdata, MTL_FDCR));
1042 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
1043 XGMAC_IOREAD(pdata, MTL_FDSR));
1044 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
1045 XGMAC_IOREAD(pdata, MTL_FDDR));
1046 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
1047 XGMAC_IOREAD(pdata, MTL_ISR));
1048 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
1049 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
1050 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
1051 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
1052 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
1053 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
1054 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
1055 XGMAC_IOREAD(pdata, MTL_TCPM0R));
1056 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
1057 XGMAC_IOREAD(pdata, MTL_TCPM1R));
1058
1059 for (i = 0 ; i < 8 ; i++ ) {
1060
1061 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
1062
1063 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
1064 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1065 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
1066 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1067 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
1068 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1069 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
1070 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1071 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
1072 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1073 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
1074 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1075
1076 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
1077 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1078 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
1079 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1080 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
1081 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1082 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
1083 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1084 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
1085 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1086 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
1087 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1088 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
1089 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1090 }
1091 }
1092
1093 static void
xgbe_dump_mac_registers(struct xgbe_prv_data * pdata)1094 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1095 {
1096 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
1097
1098 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
1099 XGMAC_IOREAD(pdata, MAC_TCR));
1100 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
1101 XGMAC_IOREAD(pdata, MAC_RCR));
1102 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
1103 XGMAC_IOREAD(pdata, MAC_PFR));
1104 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
1105 XGMAC_IOREAD(pdata, MAC_WTR));
1106 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
1107 XGMAC_IOREAD(pdata, MAC_HTR0));
1108 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
1109 XGMAC_IOREAD(pdata, MAC_HTR1));
1110 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
1111 XGMAC_IOREAD(pdata, MAC_HTR2));
1112 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
1113 XGMAC_IOREAD(pdata, MAC_HTR3));
1114 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
1115 XGMAC_IOREAD(pdata, MAC_HTR4));
1116 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
1117 XGMAC_IOREAD(pdata, MAC_HTR5));
1118 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
1119 XGMAC_IOREAD(pdata, MAC_HTR6));
1120 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
1121 XGMAC_IOREAD(pdata, MAC_HTR7));
1122 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1123 XGMAC_IOREAD(pdata, MAC_VLANTR));
1124 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1125 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1126 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1127 XGMAC_IOREAD(pdata, MAC_VLANIR));
1128 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1129 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1130 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1131 XGMAC_IOREAD(pdata, MAC_RETMR));
1132 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1133 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1134 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1135 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1136 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1137 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1138 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1139 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1140 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1141 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1142 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1143 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1144 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1145 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1146 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1147 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1148 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1149 XGMAC_IOREAD(pdata, MAC_RFCR));
1150 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1151 XGMAC_IOREAD(pdata, MAC_RQC0R));
1152 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1153 XGMAC_IOREAD(pdata, MAC_RQC1R));
1154 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1155 XGMAC_IOREAD(pdata, MAC_RQC2R));
1156 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1157 XGMAC_IOREAD(pdata, MAC_RQC3R));
1158 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1159 XGMAC_IOREAD(pdata, MAC_ISR));
1160 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1161 XGMAC_IOREAD(pdata, MAC_IER));
1162 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1163 XGMAC_IOREAD(pdata, MAC_RTSR));
1164 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1165 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1166 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1167 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1168 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1169 XGMAC_IOREAD(pdata, MAC_LPICSR));
1170 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1171 XGMAC_IOREAD(pdata, MAC_LPITCR));
1172 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1173 XGMAC_IOREAD(pdata, MAC_TIR));
1174 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1175 XGMAC_IOREAD(pdata, MAC_VR));
1176 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1177 XGMAC_IOREAD(pdata, MAC_DR));
1178 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1179 XGMAC_IOREAD(pdata, MAC_HWF0R));
1180 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1181 XGMAC_IOREAD(pdata, MAC_HWF1R));
1182 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1183 XGMAC_IOREAD(pdata, MAC_HWF2R));
1184 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1185 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1186 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1187 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1188 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1189 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1190 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1191 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1192 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1193 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1194 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1195 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1196 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1197 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1198 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1199 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1200 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1201 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1202 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1203 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1204 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1205 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1206 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1207 XGMAC_IOREAD(pdata, MAC_RSSCR));
1208 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1209 XGMAC_IOREAD(pdata, MAC_RSSDR));
1210 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1211 XGMAC_IOREAD(pdata, MAC_RSSAR));
1212 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1213 XGMAC_IOREAD(pdata, MAC_TSCR));
1214 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1215 XGMAC_IOREAD(pdata, MAC_SSIR));
1216 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1217 XGMAC_IOREAD(pdata, MAC_STSR));
1218 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1219 XGMAC_IOREAD(pdata, MAC_STNR));
1220 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1221 XGMAC_IOREAD(pdata, MAC_STSUR));
1222 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1223 XGMAC_IOREAD(pdata, MAC_STNUR));
1224 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1225 XGMAC_IOREAD(pdata, MAC_TSAR));
1226 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1227 XGMAC_IOREAD(pdata, MAC_TSSR));
1228 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1229 XGMAC_IOREAD(pdata, MAC_TXSNR));
1230 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1231 XGMAC_IOREAD(pdata, MAC_TXSSR));
1232 }
1233
1234 static void
xgbe_dump_rmon_counters(struct xgbe_prv_data * pdata)1235 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1236 {
1237 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1238
1239 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1240
1241 pdata->hw_if.read_mmc_stats(pdata);
1242
1243 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1244 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1245 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1246 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1247 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1248 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1249 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1250 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1251 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1252 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1253 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1254 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1255 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1256 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1257 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1258 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1259 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1260 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1261 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1262 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1263 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1264 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1265 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1266 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1267 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1268 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1269 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1270 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1271 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1272 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1273 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1274 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1275 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1276 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1277 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1278 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1279 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1280 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1281 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1282 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1283 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1284 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1285 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1286 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1287 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1288 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1289 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1290 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1291 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1292 MMC_RXRUNTERROR, stats->rxrunterror);
1293 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1294 MMC_RXJABBERERROR, stats->rxjabbererror);
1295 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1296 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1297 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1298 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1299 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1300 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1301 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1302 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1303 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1304 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1305 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1306 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1307 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1308 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1309 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1310 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1311 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1312 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1313 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1314 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1315 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1316 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1317 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1318 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1319 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1320 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1321 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1322 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1323 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1324 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1325 }
1326
1327 void
xgbe_dump_i2c_registers(struct xgbe_prv_data * pdata)1328 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1329 {
1330 axgbe_printf(1, "*************** I2C Registers **************\n");
1331 axgbe_printf(1, " IC_CON : %010x\n",
1332 XI2C_IOREAD(pdata, 0x00));
1333 axgbe_printf(1, " IC_TAR : %010x\n",
1334 XI2C_IOREAD(pdata, 0x04));
1335 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1336 XI2C_IOREAD(pdata, 0x0c));
1337 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1338 XI2C_IOREAD(pdata, 0x2c));
1339 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1340 XI2C_IOREAD(pdata, 0x30));
1341 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1342 XI2C_IOREAD(pdata, 0x34));
1343 axgbe_printf(1, " IC_RX_TL : %010x\n",
1344 XI2C_IOREAD(pdata, 0x38));
1345 axgbe_printf(1, " IC_TX_TL : %010x\n",
1346 XI2C_IOREAD(pdata, 0x3c));
1347 axgbe_printf(1, " IC_ENABLE : %010x\n",
1348 XI2C_IOREAD(pdata, 0x6c));
1349 axgbe_printf(1, " IC_STATUS : %010x\n",
1350 XI2C_IOREAD(pdata, 0x70));
1351 axgbe_printf(1, " IC_TXFLR : %010x\n",
1352 XI2C_IOREAD(pdata, 0x74));
1353 axgbe_printf(1, " IC_RXFLR : %010x\n",
1354 XI2C_IOREAD(pdata, 0x78));
1355 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1356 XI2C_IOREAD(pdata, 0x9c));
1357 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1358 XI2C_IOREAD(pdata, 0xf4));
1359 }
1360
1361 static void
xgbe_dump_active_vlans(struct xgbe_prv_data * pdata)1362 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1363 {
1364 int i;
1365
1366 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1367 if (i && (i%8 == 0))
1368 axgbe_printf(1, "\n");
1369 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1370 }
1371 axgbe_printf(1, "\n");
1372 }
1373
1374 static void
xgbe_default_config(struct xgbe_prv_data * pdata)1375 xgbe_default_config(struct xgbe_prv_data *pdata)
1376 {
1377 pdata->blen = DMA_SBMR_BLEN_64;
1378 pdata->pbl = DMA_PBL_128;
1379 pdata->aal = 1;
1380 pdata->rd_osr_limit = 8;
1381 pdata->wr_osr_limit = 8;
1382 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1383 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1384 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1385 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1386 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1387 pdata->pause_autoneg = 1;
1388 pdata->phy_speed = SPEED_UNKNOWN;
1389 pdata->power_down = 0;
1390 pdata->enable_rss = 1;
1391 }
1392
1393 static int
axgbe_if_attach_post(if_ctx_t ctx)1394 axgbe_if_attach_post(if_ctx_t ctx)
1395 {
1396 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1397 struct xgbe_prv_data *pdata = &sc->pdata;
1398 if_t ifp = pdata->netdev;
1399 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1400 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1401 if_softc_ctx_t scctx = sc->scctx;
1402 int ret;
1403
1404 /* set split header support based on tunable */
1405 pdata->sph_enable = axgbe_sph_enable;
1406
1407 /* Initialize ECC timestamps */
1408 pdata->tx_sec_period = ticks;
1409 pdata->tx_ded_period = ticks;
1410 pdata->rx_sec_period = ticks;
1411 pdata->rx_ded_period = ticks;
1412 pdata->desc_sec_period = ticks;
1413 pdata->desc_ded_period = ticks;
1414
1415 /* Reset the hardware */
1416 ret = hw_if->exit(&sc->pdata);
1417 if (ret)
1418 axgbe_error("%s: exit error %d\n", __func__, ret);
1419
1420 axgbe_sysctl_init(pdata);
1421
1422 /* Configure the defaults */
1423 xgbe_default_config(pdata);
1424
1425 /* Set default max values if not provided */
1426 if (!pdata->tx_max_fifo_size)
1427 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1428 if (!pdata->rx_max_fifo_size)
1429 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1430
1431 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1432 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1433
1434 /* Set and validate the number of descriptors for a ring */
1435 MPASS(powerof2(XGBE_TX_DESC_CNT));
1436 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1437 MPASS(powerof2(XGBE_RX_DESC_CNT));
1438 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1439
1440 /* Adjust the number of queues based on interrupts assigned */
1441 if (pdata->channel_irq_count) {
1442 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1443 pdata->channel_irq_count);
1444 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1445 pdata->channel_irq_count);
1446
1447 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1448 pdata->tx_ring_count, pdata->tx_q_count,
1449 pdata->rx_ring_count, pdata->rx_q_count);
1450 }
1451
1452 /* Set channel count based on interrupts assigned */
1453 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1454 scctx->isc_nrxqsets);
1455 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1456
1457 axgbe_initialize_rss_mapping(pdata);
1458
1459 /* Initialize the PHY device */
1460 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1461 phy_if->phy_init(pdata);
1462
1463 /* Set the coalescing */
1464 xgbe_init_rx_coalesce(&sc->pdata);
1465 xgbe_init_tx_coalesce(&sc->pdata);
1466
1467 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1468 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1469 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1470 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1471 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1472 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1473 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1474 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1475 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1476 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1477 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1478 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1479 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1480
1481 /* Initialize the phy */
1482 pdata->phy_link = -1;
1483 pdata->phy_speed = SPEED_UNKNOWN;
1484 ret = phy_if->phy_reset(pdata);
1485 if (ret)
1486 return (ret);
1487
1488 /* Calculate the Rx buffer size before allocating rings */
1489 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1490 pdata->rx_buf_size = ret;
1491 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1492
1493 /*
1494 * Mark the device down until it is initialized, which happens
1495 * when the device is accessed first (for configuring the iface,
1496 * eg: setting IP)
1497 */
1498 set_bit(XGBE_DOWN, &pdata->dev_state);
1499
1500 DBGPR("mtu %d\n", if_getmtu(ifp));
1501 scctx->isc_max_frame_size = if_getmtu(ifp) + 18;
1502 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1503
1504 axgbe_pci_init(pdata);
1505
1506 return (0);
1507 } /* axgbe_if_attach_post */
1508
1509 static void
xgbe_free_intr(struct xgbe_prv_data * pdata,struct resource * res,void * tag,int rid)1510 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1511 int rid)
1512 {
1513 if (tag)
1514 bus_teardown_intr(pdata->dev, res, tag);
1515
1516 if (res)
1517 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1518 }
1519
1520 static void
axgbe_interrupts_free(if_ctx_t ctx)1521 axgbe_interrupts_free(if_ctx_t ctx)
1522 {
1523 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1524 struct xgbe_prv_data *pdata = &sc->pdata;
1525 if_softc_ctx_t scctx = sc->scctx;
1526 struct xgbe_channel *channel;
1527 struct if_irq irq;
1528 int i;
1529
1530 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1531
1532 /* Free dev_irq */
1533 iflib_irq_free(ctx, &pdata->dev_irq);
1534
1535 /* Free ecc_irq */
1536 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1537 pdata->ecc_rid);
1538
1539 /* Free i2c_irq */
1540 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1541 pdata->i2c_rid);
1542
1543 /* Free an_irq */
1544 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1545 pdata->an_rid);
1546
1547 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1548
1549 channel = pdata->channel[i];
1550 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1551 irq.ii_res = channel->dma_irq_res;
1552 irq.ii_tag = channel->dma_irq_tag;
1553 iflib_irq_free(ctx, &irq);
1554 }
1555 }
1556
1557 static int
axgbe_if_detach(if_ctx_t ctx)1558 axgbe_if_detach(if_ctx_t ctx)
1559 {
1560 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1561 struct xgbe_prv_data *pdata = &sc->pdata;
1562 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1563 struct resource *mac_res[2];
1564
1565 mac_res[0] = pdata->xgmac_res;
1566 mac_res[1] = pdata->xpcs_res;
1567
1568 phy_if->phy_stop(pdata);
1569 phy_if->phy_exit(pdata);
1570
1571 /* Free Interrupts */
1572 axgbe_interrupts_free(ctx);
1573
1574 /* Free workqueues */
1575 taskqueue_free(pdata->dev_workqueue);
1576
1577 /* Release bus resources */
1578 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1579
1580 /* Free VLAN bitmap */
1581 free(pdata->active_vlans, M_AXGBE);
1582
1583 axgbe_sysctl_exit(pdata);
1584
1585 return (0);
1586 } /* axgbe_if_detach */
1587
1588 static void
axgbe_pci_init(struct xgbe_prv_data * pdata)1589 axgbe_pci_init(struct xgbe_prv_data *pdata)
1590 {
1591 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1592 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1593 int ret = 0;
1594
1595 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1596 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__);
1597 return;
1598 }
1599
1600 hw_if->init(pdata);
1601
1602 ret = phy_if->phy_start(pdata);
1603 if (ret) {
1604 axgbe_error("%s: phy start %d\n", __func__, ret);
1605 ret = hw_if->exit(pdata);
1606 if (ret)
1607 axgbe_error("%s: exit error %d\n", __func__, ret);
1608 return;
1609 }
1610
1611 hw_if->enable_tx(pdata);
1612 hw_if->enable_rx(pdata);
1613
1614 xgbe_start_timers(pdata);
1615
1616 clear_bit(XGBE_DOWN, &pdata->dev_state);
1617
1618 xgbe_dump_phy_registers(pdata);
1619 xgbe_dump_prop_registers(pdata);
1620 xgbe_dump_dma_registers(pdata, -1);
1621 xgbe_dump_mtl_registers(pdata);
1622 xgbe_dump_mac_registers(pdata);
1623 xgbe_dump_rmon_counters(pdata);
1624 }
1625
1626 static void
axgbe_if_init(if_ctx_t ctx)1627 axgbe_if_init(if_ctx_t ctx)
1628 {
1629 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1630 struct xgbe_prv_data *pdata = &sc->pdata;
1631
1632 axgbe_pci_init(pdata);
1633 }
1634
1635 static void
axgbe_pci_stop(if_ctx_t ctx)1636 axgbe_pci_stop(if_ctx_t ctx)
1637 {
1638 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1639 struct xgbe_prv_data *pdata = &sc->pdata;
1640 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1641 int ret;
1642
1643 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1644 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1645 return;
1646 }
1647
1648 xgbe_stop_timers(pdata);
1649 taskqueue_drain_all(pdata->dev_workqueue);
1650
1651 hw_if->disable_tx(pdata);
1652 hw_if->disable_rx(pdata);
1653
1654 ret = hw_if->exit(pdata);
1655 if (ret)
1656 axgbe_error("%s: exit error %d\n", __func__, ret);
1657
1658 set_bit(XGBE_DOWN, &pdata->dev_state);
1659 }
1660
1661 static void
axgbe_if_stop(if_ctx_t ctx)1662 axgbe_if_stop(if_ctx_t ctx)
1663 {
1664 axgbe_pci_stop(ctx);
1665 }
1666
1667 static void
axgbe_if_disable_intr(if_ctx_t ctx)1668 axgbe_if_disable_intr(if_ctx_t ctx)
1669 {
1670 /* TODO - implement */
1671 }
1672
1673 static void
axgbe_if_enable_intr(if_ctx_t ctx)1674 axgbe_if_enable_intr(if_ctx_t ctx)
1675 {
1676 /* TODO - implement */
1677 }
1678
1679 static int
axgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int ntxqs,int ntxqsets)1680 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1681 int ntxqsets)
1682 {
1683 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1684 struct xgbe_prv_data *pdata = &sc->pdata;
1685 if_softc_ctx_t scctx = sc->scctx;
1686 struct xgbe_channel *channel;
1687 struct xgbe_ring *tx_ring;
1688 int i, j, k;
1689
1690 MPASS(scctx->isc_ntxqsets > 0);
1691 MPASS(scctx->isc_ntxqsets == ntxqsets);
1692 MPASS(ntxqs == 1);
1693
1694 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1695 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1696
1697 for (i = 0 ; i < ntxqsets; i++) {
1698
1699 channel = pdata->channel[i];
1700
1701 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1702 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1703
1704 if (tx_ring == NULL) {
1705 axgbe_error("Unable to allocate TX ring memory\n");
1706 goto tx_ring_fail;
1707 }
1708
1709 channel->tx_ring = tx_ring;
1710
1711 for (j = 0; j < ntxqs; j++, tx_ring++) {
1712 tx_ring->rdata =
1713 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1714 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1715
1716 /* Get the virtual & physical address of hw queues */
1717 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1718 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1719 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1720 spin_lock_init(&tx_ring->lock);
1721 }
1722 }
1723
1724 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1725
1726 return (0);
1727
1728 tx_ring_fail:
1729
1730 for (j = 0; j < i ; j++) {
1731
1732 channel = pdata->channel[j];
1733
1734 tx_ring = channel->tx_ring;
1735 for (k = 0; k < ntxqs ; k++, tx_ring++) {
1736 if (tx_ring && tx_ring->rdata)
1737 free(tx_ring->rdata, M_AXGBE);
1738 }
1739 free(channel->tx_ring, M_AXGBE);
1740
1741 channel->tx_ring = NULL;
1742 }
1743
1744 return (ENOMEM);
1745
1746 } /* axgbe_if_tx_queues_alloc */
1747
1748 static int
axgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int nrxqs,int nrxqsets)1749 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1750 int nrxqsets)
1751 {
1752 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1753 struct xgbe_prv_data *pdata = &sc->pdata;
1754 if_softc_ctx_t scctx = sc->scctx;
1755 struct xgbe_channel *channel;
1756 struct xgbe_ring *rx_ring;
1757 int i, j, k;
1758
1759 MPASS(scctx->isc_nrxqsets > 0);
1760 MPASS(scctx->isc_nrxqsets == nrxqsets);
1761 if (!pdata->sph_enable) {
1762 MPASS(nrxqs == 1);
1763 } else {
1764 MPASS(nrxqs == 2);
1765 }
1766
1767 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1768 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1769
1770 for (i = 0 ; i < nrxqsets; i++) {
1771
1772 channel = pdata->channel[i];
1773
1774 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1775 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1776
1777 if (rx_ring == NULL) {
1778 axgbe_error("Unable to allocate RX ring memory\n");
1779 goto rx_ring_fail;
1780 }
1781
1782 channel->rx_ring = rx_ring;
1783
1784 for (j = 0; j < nrxqs; j++, rx_ring++) {
1785 rx_ring->rdata =
1786 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1787 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1788
1789 /* Get the virtual and physical address of the hw queues */
1790 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1791 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1792 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1793 spin_lock_init(&rx_ring->lock);
1794 }
1795 }
1796
1797 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1798
1799 return (0);
1800
1801 rx_ring_fail:
1802
1803 for (j = 0 ; j < i ; j++) {
1804
1805 channel = pdata->channel[j];
1806
1807 rx_ring = channel->rx_ring;
1808 for (k = 0; k < nrxqs ; k++, rx_ring++) {
1809 if (rx_ring && rx_ring->rdata)
1810 free(rx_ring->rdata, M_AXGBE);
1811 }
1812 free(channel->rx_ring, M_AXGBE);
1813
1814 channel->rx_ring = NULL;
1815 }
1816
1817 return (ENOMEM);
1818
1819 } /* axgbe_if_rx_queues_alloc */
1820
1821 static void
axgbe_if_queues_free(if_ctx_t ctx)1822 axgbe_if_queues_free(if_ctx_t ctx)
1823 {
1824 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1825 struct xgbe_prv_data *pdata = &sc->pdata;
1826 if_softc_ctx_t scctx = sc->scctx;
1827 if_shared_ctx_t sctx = sc->sctx;
1828 struct xgbe_channel *channel;
1829 struct xgbe_ring *tx_ring;
1830 struct xgbe_ring *rx_ring;
1831 int i, j;
1832
1833 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1834
1835 channel = pdata->channel[i];
1836
1837 tx_ring = channel->tx_ring;
1838 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1839 if (tx_ring && tx_ring->rdata)
1840 free(tx_ring->rdata, M_AXGBE);
1841 }
1842 free(channel->tx_ring, M_AXGBE);
1843 channel->tx_ring = NULL;
1844 }
1845
1846 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1847
1848 channel = pdata->channel[i];
1849
1850 rx_ring = channel->rx_ring;
1851 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1852 if (rx_ring && rx_ring->rdata)
1853 free(rx_ring->rdata, M_AXGBE);
1854 }
1855 free(channel->rx_ring, M_AXGBE);
1856 channel->rx_ring = NULL;
1857 }
1858
1859 axgbe_free_channels(sc);
1860 } /* axgbe_if_queues_free */
1861
1862 static void
axgbe_if_vlan_register(if_ctx_t ctx,uint16_t vtag)1863 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1864 {
1865 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1866 struct xgbe_prv_data *pdata = &sc->pdata;
1867 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1868
1869 if (!bit_test(pdata->active_vlans, vtag)) {
1870 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1871
1872 bit_set(pdata->active_vlans, vtag);
1873 hw_if->update_vlan_hash_table(pdata);
1874 pdata->num_active_vlans++;
1875
1876 axgbe_printf(1, "Total active vlans: %d\n",
1877 pdata->num_active_vlans);
1878 } else
1879 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1880
1881 xgbe_dump_active_vlans(pdata);
1882 }
1883
1884 static void
axgbe_if_vlan_unregister(if_ctx_t ctx,uint16_t vtag)1885 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1886 {
1887 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1888 struct xgbe_prv_data *pdata = &sc->pdata;
1889 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1890
1891 if (pdata->num_active_vlans == 0) {
1892 axgbe_printf(1, "No active VLANs to unregister\n");
1893 return;
1894 }
1895
1896 if (bit_test(pdata->active_vlans, vtag)){
1897 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1898
1899 bit_clear(pdata->active_vlans, vtag);
1900 hw_if->update_vlan_hash_table(pdata);
1901 pdata->num_active_vlans--;
1902
1903 axgbe_printf(1, "Total active vlans: %d\n",
1904 pdata->num_active_vlans);
1905 } else
1906 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1907
1908 xgbe_dump_active_vlans(pdata);
1909 }
1910
1911 #if __FreeBSD_version >= 1300000
1912 static bool
axgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1913 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1914 {
1915 switch (event) {
1916 case IFLIB_RESTART_VLAN_CONFIG:
1917 default:
1918 return (true);
1919 }
1920 }
1921 #endif
1922
1923 static int
axgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)1924 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1925 {
1926 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1927 struct xgbe_prv_data *pdata = &sc->pdata;
1928 if_softc_ctx_t scctx = sc->scctx;
1929 struct xgbe_channel *channel;
1930 struct if_irq irq;
1931 int i, error, rid = 0, flags;
1932 char buf[16];
1933
1934 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1935
1936 pdata->isr_as_tasklet = 1;
1937
1938 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1939 pdata->irq_count = 1;
1940 pdata->channel_irq_count = 1;
1941 return (0);
1942 }
1943
1944 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1945 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1946
1947 flags = RF_ACTIVE;
1948
1949 /* DEV INTR SETUP */
1950 rid++;
1951 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1952 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1953 if (error) {
1954 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1955 rid, "dev_irq");
1956 return (error);
1957 }
1958
1959 /* ECC INTR SETUP */
1960 rid++;
1961 pdata->ecc_rid = rid;
1962 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1963 &rid, flags);
1964 if (!pdata->ecc_irq_res) {
1965 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1966 rid, "ecc_irq");
1967 return (ENOMEM);
1968 }
1969
1970 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1971 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1972 if (error) {
1973 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1974 rid, "ecc_irq", error);
1975 return (error);
1976 }
1977
1978 /* I2C INTR SETUP */
1979 rid++;
1980 pdata->i2c_rid = rid;
1981 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1982 &rid, flags);
1983 if (!pdata->i2c_irq_res) {
1984 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1985 rid, "i2c_irq");
1986 return (ENOMEM);
1987 }
1988
1989 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1990 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1991 if (error) {
1992 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1993 rid, "i2c_irq", error);
1994 return (error);
1995 }
1996
1997 /* AN INTR SETUP */
1998 rid++;
1999 pdata->an_rid = rid;
2000 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
2001 &rid, flags);
2002 if (!pdata->an_irq_res) {
2003 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
2004 rid, "an_irq");
2005 return (ENOMEM);
2006 }
2007
2008 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
2009 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
2010 if (error) {
2011 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
2012 rid, "an_irq", error);
2013 return (error);
2014 }
2015
2016 pdata->per_channel_irq = 1;
2017 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
2018 rid++;
2019 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
2020
2021 channel = pdata->channel[i];
2022
2023 snprintf(buf, sizeof(buf), "rxq%d", i);
2024 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX,
2025 axgbe_msix_que, channel, channel->queue_index, buf);
2026
2027 if (error) {
2028 axgbe_error("Failed to allocated que int %d err: %d\n",
2029 i, error);
2030 return (error);
2031 }
2032
2033 channel->dma_irq_rid = rid;
2034 channel->dma_irq_res = irq.ii_res;
2035 channel->dma_irq_tag = irq.ii_tag;
2036 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
2037 __func__, scctx->isc_nrxqsets, i, rid);
2038 }
2039 pdata->irq_count = msix;
2040 pdata->channel_irq_count = scctx->isc_nrxqsets;
2041
2042 for (i = 0; i < scctx->isc_ntxqsets; i++) {
2043
2044 channel = pdata->channel[i];
2045
2046 snprintf(buf, sizeof(buf), "txq%d", i);
2047 irq.ii_res = channel->dma_irq_res;
2048 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2049 channel->queue_index, buf);
2050 }
2051
2052 return (0);
2053 } /* axgbe_if_msix_intr_assign */
2054
2055 static int
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2056 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2057 {
2058 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2059 enum xgbe_int int_id;
2060
2061 if (channel->tx_ring && channel->rx_ring)
2062 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2063 else if (channel->tx_ring)
2064 int_id = XGMAC_INT_DMA_CH_SR_TI;
2065 else if (channel->rx_ring)
2066 int_id = XGMAC_INT_DMA_CH_SR_RI;
2067 else
2068 return (-1);
2069
2070 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2071 __func__, channel->queue_index, int_id);
2072 return (hw_if->enable_int(channel, int_id));
2073 }
2074
2075 static void
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2076 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2077 {
2078 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2079 enum xgbe_int int_id;
2080
2081 if (channel->tx_ring && channel->rx_ring)
2082 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2083 else if (channel->tx_ring)
2084 int_id = XGMAC_INT_DMA_CH_SR_TI;
2085 else if (channel->rx_ring)
2086 int_id = XGMAC_INT_DMA_CH_SR_RI;
2087 else
2088 return;
2089
2090 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2091 __func__, channel->queue_index, int_id);
2092 hw_if->disable_int(channel, int_id);
2093 }
2094
2095 static void
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)2096 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2097 {
2098 unsigned int i;
2099
2100 for (i = 0; i < pdata->channel_count; i++)
2101 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2102 }
2103
2104 static int
axgbe_msix_que(void * arg)2105 axgbe_msix_que(void *arg)
2106 {
2107 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2108 struct xgbe_prv_data *pdata = channel->pdata;
2109 unsigned int dma_status;
2110
2111 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2112 __func__, channel->queue_index,
2113 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2114 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2115 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2116 XGMAC_IOREAD(pdata, DMA_ISR),
2117 XGMAC_IOREAD(pdata, MAC_ISR));
2118
2119 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2120
2121 /* Disable Tx and Rx channel interrupts */
2122 xgbe_disable_rx_tx_int(pdata, channel);
2123
2124 /* Clear the interrupts */
2125 dma_status = 0;
2126 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2127 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2128 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2129
2130 return (FILTER_SCHEDULE_THREAD);
2131 }
2132
2133 static int
axgbe_dev_isr(void * arg)2134 axgbe_dev_isr(void *arg)
2135 {
2136 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2137 struct xgbe_prv_data *pdata = &sc->pdata;
2138 struct xgbe_channel *channel;
2139 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2140 unsigned int i, dma_isr, dma_ch_isr;
2141 unsigned int mac_isr, mac_mdioisr;
2142 int ret = FILTER_HANDLED;
2143
2144 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2145 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2146
2147 if (!dma_isr)
2148 return (FILTER_HANDLED);
2149
2150 for (i = 0; i < pdata->channel_count; i++) {
2151
2152 if (!(dma_isr & (1 << i)))
2153 continue;
2154
2155 channel = pdata->channel[i];
2156
2157 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2158 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2159 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2160 DMA_CH_DSR));
2161
2162 /*
2163 * The TI or RI interrupt bits may still be set even if using
2164 * per channel DMA interrupts. Check to be sure those are not
2165 * enabled before using the private data napi structure.
2166 */
2167 if (!pdata->per_channel_irq &&
2168 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2169 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2170
2171 /* Disable Tx and Rx interrupts */
2172 xgbe_disable_rx_tx_ints(pdata);
2173 } else {
2174
2175 /*
2176 * Don't clear Rx/Tx status if doing per channel DMA
2177 * interrupts, these will be cleared by the ISR for
2178 * per channel DMA interrupts
2179 */
2180 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2181 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2182 }
2183
2184 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2185 pdata->ext_stats.rx_buffer_unavailable++;
2186
2187 /* Restart the device on a Fatal Bus Error */
2188 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2189 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2190 __func__, dma_ch_isr);
2191
2192 /* Clear all interrupt signals */
2193 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2194
2195 ret = FILTER_SCHEDULE_THREAD;
2196 }
2197
2198 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2199
2200 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2201 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2202
2203 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2204 hw_if->tx_mmc_int(pdata);
2205
2206 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2207 hw_if->rx_mmc_int(pdata);
2208
2209 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2210 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2211
2212 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2213 SNGLCOMPINT))
2214 wakeup_one(pdata);
2215 }
2216
2217 }
2218
2219 return (ret);
2220 } /* axgbe_dev_isr */
2221
2222 static void
axgbe_i2c_isr(void * arg)2223 axgbe_i2c_isr(void *arg)
2224 {
2225 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2226
2227 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2228 }
2229
2230 static void
axgbe_ecc_isr(void * arg)2231 axgbe_ecc_isr(void *arg)
2232 {
2233 /* TODO - implement */
2234 }
2235
2236 static void
axgbe_an_isr(void * arg)2237 axgbe_an_isr(void *arg)
2238 {
2239 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2240
2241 sc->pdata.phy_if.an_isr(&sc->pdata);
2242 }
2243
2244 static int
axgbe_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2245 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2246 {
2247 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2248 struct xgbe_prv_data *pdata = &sc->pdata;
2249 int ret;
2250
2251 if (qid < pdata->tx_q_count) {
2252 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2253 if (ret) {
2254 axgbe_error("Enable TX INT failed\n");
2255 return (ret);
2256 }
2257 } else
2258 axgbe_error("Queue ID exceed channel count\n");
2259
2260 return (0);
2261 }
2262
2263 static int
axgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2264 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2265 {
2266 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2267 struct xgbe_prv_data *pdata = &sc->pdata;
2268 int ret;
2269
2270 if (qid < pdata->rx_q_count) {
2271 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2272 if (ret) {
2273 axgbe_error("Enable RX INT failed\n");
2274 return (ret);
2275 }
2276 } else
2277 axgbe_error("Queue ID exceed channel count\n");
2278
2279 return (0);
2280 }
2281
2282 static void
axgbe_if_update_admin_status(if_ctx_t ctx)2283 axgbe_if_update_admin_status(if_ctx_t ctx)
2284 {
2285 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2286 struct xgbe_prv_data *pdata = &sc->pdata;
2287
2288 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2289 pdata->phy_link, sc->link_status, pdata->phy.speed);
2290
2291 if (pdata->phy_link < 0)
2292 return;
2293
2294 if (pdata->phy_link) {
2295 if (sc->link_status == LINK_STATE_DOWN) {
2296 sc->link_status = LINK_STATE_UP;
2297 if (pdata->phy.speed & SPEED_10000)
2298 iflib_link_state_change(ctx, LINK_STATE_UP,
2299 IF_Gbps(10));
2300 else if (pdata->phy.speed & SPEED_2500)
2301 iflib_link_state_change(ctx, LINK_STATE_UP,
2302 IF_Gbps(2.5));
2303 else if (pdata->phy.speed & SPEED_1000)
2304 iflib_link_state_change(ctx, LINK_STATE_UP,
2305 IF_Gbps(1));
2306 else if (pdata->phy.speed & SPEED_100)
2307 iflib_link_state_change(ctx, LINK_STATE_UP,
2308 IF_Mbps(100));
2309 else if (pdata->phy.speed & SPEED_10)
2310 iflib_link_state_change(ctx, LINK_STATE_UP,
2311 IF_Mbps(10));
2312 }
2313 } else {
2314 if (sc->link_status == LINK_STATE_UP) {
2315 sc->link_status = LINK_STATE_DOWN;
2316 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2317 }
2318 }
2319 }
2320
2321 static int
axgbe_if_media_change(if_ctx_t ctx)2322 axgbe_if_media_change(if_ctx_t ctx)
2323 {
2324 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2325 struct ifmedia *ifm = iflib_get_media(ctx);
2326
2327 sx_xlock(&sc->pdata.an_mutex);
2328 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2329 return (EINVAL);
2330
2331 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2332 case IFM_10G_KR:
2333 sc->pdata.phy.speed = SPEED_10000;
2334 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2335 break;
2336 case IFM_2500_KX:
2337 sc->pdata.phy.speed = SPEED_2500;
2338 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2339 break;
2340 case IFM_1000_KX:
2341 sc->pdata.phy.speed = SPEED_1000;
2342 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2343 break;
2344 case IFM_100_TX:
2345 sc->pdata.phy.speed = SPEED_100;
2346 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2347 break;
2348 case IFM_AUTO:
2349 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2350 break;
2351 }
2352 sx_xunlock(&sc->pdata.an_mutex);
2353
2354 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2355 }
2356
2357 static int
axgbe_if_promisc_set(if_ctx_t ctx,int flags)2358 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2359 {
2360 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2361 struct xgbe_prv_data *pdata = &sc->pdata;
2362 if_t ifp = pdata->netdev;
2363
2364 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n",
2365 __func__, XGMAC_IOREAD(pdata, MAC_PFR), if_getdrvflags(ifp),
2366 flags);
2367
2368 if (flags & IFF_PROMISC) {
2369
2370 axgbe_printf(1, "Requested to enter promisc mode\n");
2371
2372 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2373 axgbe_printf(1, "Already in promisc mode\n");
2374 return (0);
2375 }
2376
2377 axgbe_printf(1, "Entering promisc mode\n");
2378 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2379 /* Disable VLAN filtering */
2380 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2381 } else {
2382
2383 axgbe_printf(1, "Requested to leave promisc mode\n");
2384
2385 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2386 axgbe_printf(1, "Already not in promisc mode\n");
2387 return (0);
2388 }
2389
2390 axgbe_printf(1, "Leaving promisc mode\n");
2391 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2392 /* Enable VLAN filtering */
2393 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2394 }
2395
2396 return (0);
2397 }
2398
2399 static uint64_t
axgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)2400 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2401 {
2402 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2403 if_t ifp = iflib_get_ifp(ctx);
2404 struct xgbe_prv_data *pdata = &sc->pdata;
2405 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2406
2407 pdata->hw_if.read_mmc_stats(pdata);
2408
2409 switch(cnt) {
2410 case IFCOUNTER_IPACKETS:
2411 return (pstats->rxframecount_gb);
2412 case IFCOUNTER_IERRORS:
2413 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2414 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2415 case IFCOUNTER_OPACKETS:
2416 return (pstats->txframecount_gb);
2417 case IFCOUNTER_OERRORS:
2418 return (pstats->txframecount_gb - pstats->txframecount_g);
2419 case IFCOUNTER_IBYTES:
2420 return (pstats->rxoctetcount_gb);
2421 case IFCOUNTER_OBYTES:
2422 return (pstats->txoctetcount_gb);
2423 default:
2424 return (if_get_counter_default(ifp, cnt));
2425 }
2426 }
2427
2428 static int
axgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)2429 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2430 {
2431 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2432 struct xgbe_prv_data *pdata = &sc->pdata;
2433 int ret;
2434
2435 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2436 return (EINVAL);
2437
2438 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2439 pdata->rx_buf_size = ret;
2440 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2441
2442 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2443 return (0);
2444 }
2445
2446 static void
axgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2447 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2448 {
2449 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2450 struct xgbe_prv_data *pdata = &sc->pdata;
2451
2452 ifmr->ifm_status = IFM_AVALID;
2453 if (!sc->pdata.phy.link)
2454 return;
2455
2456 ifmr->ifm_active = IFM_ETHER;
2457 ifmr->ifm_status |= IFM_ACTIVE;
2458
2459 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2460 pdata->phy_if.phy_impl.cur_mode(pdata));
2461 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2462
2463 ifmr->ifm_active |= IFM_FDX;
2464 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2465 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2466 }
2467