1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Contact Information :
28 * Rajesh Kumar <rajesh1.kumar@amd.com>
29 * Shreyank Amartya <Shreyank.Amartya@amd.com>
30 */
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/rman.h>
39 #include <sys/smp.h>
40 #include <sys/socket.h>
41 #include <sys/sysctl.h>
42 #include <sys/systm.h>
43
44 #include <net/if.h>
45 #include <net/if_media.h>
46
47 #include <dev/mii/mii.h>
48 #include <dev/mii/miivar.h>
49
50 #include <dev/pci/pcireg.h>
51 #include <dev/pci/pcivar.h>
52
53 #include "xgbe.h"
54 #include "xgbe-common.h"
55
56 #include "miibus_if.h"
57 #include "ifdi_if.h"
58 #include "opt_inet.h"
59 #include "opt_inet6.h"
60 #include "opt_rss.h"
61
62 #ifdef RSS
63 #include <net/rss_config.h>
64 #include <netinet/in_rss.h>
65 #endif
66
67 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
68
69 extern struct if_txrx axgbe_txrx;
70 static int axgbe_sph_enable;
71
72 /* Function prototypes */
73 static void *axgbe_register(device_t);
74 static int axgbe_if_attach_pre(if_ctx_t);
75 static int axgbe_if_attach_post(if_ctx_t);
76 static int axgbe_if_detach(if_ctx_t);
77 static void axgbe_if_stop(if_ctx_t);
78 static void axgbe_if_init(if_ctx_t);
79
80 /* Queue related routines */
81 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
82 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
83 static int axgbe_alloc_channels(if_ctx_t);
84 static void axgbe_free_channels(struct axgbe_if_softc *);
85 static void axgbe_if_queues_free(if_ctx_t);
86 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
87 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
88
89 /* Interrupt related routines */
90 static void axgbe_if_disable_intr(if_ctx_t);
91 static void axgbe_if_enable_intr(if_ctx_t);
92 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
93 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
94
95 /* Init and Iflib routines */
96 static void axgbe_pci_init(struct xgbe_prv_data *);
97 static void axgbe_pci_stop(if_ctx_t);
98 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
99 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
100 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
101 static void axgbe_if_update_admin_status(if_ctx_t);
102 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
103 static int axgbe_if_media_change(if_ctx_t);
104 static int axgbe_if_promisc_set(if_ctx_t, int);
105 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
106 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
107 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
108 #if __FreeBSD_version >= 1300000
109 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
110 #endif
111 static void axgbe_set_counts(if_ctx_t);
112 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
113 static void axgbe_initialize_rss_mapping(struct xgbe_prv_data *);
114
115 /* MII interface registered functions */
116 static int axgbe_miibus_readreg(device_t, int, int);
117 static int axgbe_miibus_writereg(device_t, int, int, int);
118 static void axgbe_miibus_statchg(device_t);
119
120 /* ISR routines */
121 static int axgbe_dev_isr(void *);
122 static void axgbe_ecc_isr(void *);
123 static void axgbe_i2c_isr(void *);
124 static void axgbe_an_isr(void *);
125 static int axgbe_msix_que(void *);
126
127 /* Timer routines */
128 static void xgbe_service(void *, int);
129 static void xgbe_service_timer(void *);
130 static void xgbe_init_timers(struct xgbe_prv_data *);
131 static void xgbe_stop_timers(struct xgbe_prv_data *);
132
133 /* Dump routines */
134 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
135
136 /*
137 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
138 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
139 * table.
140 */
141 static struct resource_spec axgbe_pci_mac_spec[] = {
142 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
143 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
144 { -1, 0 }
145 };
146
147 static const pci_vendor_info_t axgbe_vendor_info_array[] =
148 {
149 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
150 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
151 PVID_END
152 };
153
154 static struct xgbe_version_data xgbe_v2a = {
155 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
156 .xpcs_access = XGBE_XPCS_ACCESS_V2,
157 .mmc_64bit = 1,
158 .tx_max_fifo_size = 229376,
159 .rx_max_fifo_size = 229376,
160 .tx_tstamp_workaround = 1,
161 .ecc_support = 1,
162 .i2c_support = 1,
163 .irq_reissue_support = 1,
164 .tx_desc_prefetch = 5,
165 .rx_desc_prefetch = 5,
166 .an_cdr_workaround = 1,
167 };
168
169 static struct xgbe_version_data xgbe_v2b = {
170 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
171 .xpcs_access = XGBE_XPCS_ACCESS_V2,
172 .mmc_64bit = 1,
173 .tx_max_fifo_size = 65536,
174 .rx_max_fifo_size = 65536,
175 .tx_tstamp_workaround = 1,
176 .ecc_support = 1,
177 .i2c_support = 1,
178 .irq_reissue_support = 1,
179 .tx_desc_prefetch = 5,
180 .rx_desc_prefetch = 5,
181 .an_cdr_workaround = 1,
182 };
183
184 /* Device Interface */
185 static device_method_t ax_methods[] = {
186 DEVMETHOD(device_register, axgbe_register),
187 DEVMETHOD(device_probe, iflib_device_probe),
188 DEVMETHOD(device_attach, iflib_device_attach),
189 DEVMETHOD(device_detach, iflib_device_detach),
190
191 /* MII interface */
192 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
193 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
194 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
195
196 DEVMETHOD_END
197 };
198
199 static driver_t ax_driver = {
200 "ax", ax_methods, sizeof(struct axgbe_if_softc),
201 };
202
203 DRIVER_MODULE(axp, pci, ax_driver, 0, 0);
204 DRIVER_MODULE(miibus, ax, miibus_driver, 0, 0);
205 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
206
207 MODULE_DEPEND(ax, pci, 1, 1, 1);
208 MODULE_DEPEND(ax, ether, 1, 1, 1);
209 MODULE_DEPEND(ax, iflib, 1, 1, 1);
210 MODULE_DEPEND(ax, miibus, 1, 1, 1);
211
212 /* Iflib Interface */
213 static device_method_t axgbe_if_methods[] = {
214 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
215 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
216 DEVMETHOD(ifdi_detach, axgbe_if_detach),
217 DEVMETHOD(ifdi_init, axgbe_if_init),
218 DEVMETHOD(ifdi_stop, axgbe_if_stop),
219 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
220 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
221 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
222 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
223 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
224 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
225 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
226 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
227 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
228 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
229 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
230 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
231 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
232 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
233 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
234 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
235 #if __FreeBSD_version >= 1300000
236 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
237 #endif
238 DEVMETHOD_END
239 };
240
241 static driver_t axgbe_if_driver = {
242 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
243 };
244
245 /* Iflib Shared Context */
246 static struct if_shared_ctx axgbe_sctx_init = {
247 .isc_magic = IFLIB_MAGIC,
248 .isc_driver = &axgbe_if_driver,
249 .isc_q_align = PAGE_SIZE,
250 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
251 .isc_tx_maxsegsize = PAGE_SIZE,
252 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
253 .isc_tso_maxsegsize = PAGE_SIZE,
254 .isc_rx_maxsize = MJUM9BYTES,
255 .isc_rx_maxsegsize = MJUM9BYTES,
256 .isc_rx_nsegments = 1,
257 .isc_admin_intrcnt = 4,
258
259 .isc_vendor_info = axgbe_vendor_info_array,
260 .isc_driver_version = XGBE_DRV_VERSION,
261
262 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
263 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
264 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
265
266 .isc_ntxqs = 1,
267 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
268 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
269 };
270
271 static void *
axgbe_register(device_t dev)272 axgbe_register(device_t dev)
273 {
274 int axgbe_nfl;
275 int axgbe_nrxqs;
276 int error, i;
277 char *value = NULL;
278
279 value = kern_getenv("dev.ax.sph_enable");
280 if (value) {
281 axgbe_sph_enable = strtol(value, NULL, 10);
282 freeenv(value);
283 } else {
284 /*
285 * No tunable found, generate one with default values
286 * Note: only a reboot will reveal the new kenv
287 */
288 error = kern_setenv("dev.ax.sph_enable", "0");
289 if (error) {
290 printf("Error setting tunable, using default driver values\n");
291 }
292 axgbe_sph_enable = 0;
293 }
294
295 if (!axgbe_sph_enable) {
296 axgbe_nfl = 1;
297 axgbe_nrxqs = 1;
298 } else {
299 axgbe_nfl = 2;
300 axgbe_nrxqs = 2;
301 }
302
303 axgbe_sctx_init.isc_nfl = axgbe_nfl;
304 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs;
305
306 for (i = 0 ; i < axgbe_nrxqs ; i++) {
307 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN;
308 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT;
309 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX;
310 }
311
312 return (&axgbe_sctx_init);
313 }
314
315 /* MII Interface Functions */
316 static int
axgbe_miibus_readreg(device_t dev,int phy,int reg)317 axgbe_miibus_readreg(device_t dev, int phy, int reg)
318 {
319 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
320 struct xgbe_prv_data *pdata = &sc->pdata;
321 int val;
322
323 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
324
325 val = xgbe_phy_mii_read(pdata, phy, reg);
326
327 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
328 return (val & 0xFFFF);
329 }
330
331 static int
axgbe_miibus_writereg(device_t dev,int phy,int reg,int val)332 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
333 {
334 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
335 struct xgbe_prv_data *pdata = &sc->pdata;
336
337 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
338
339 xgbe_phy_mii_write(pdata, phy, reg, val);
340
341 return(0);
342 }
343
344 static void
axgbe_miibus_statchg(device_t dev)345 axgbe_miibus_statchg(device_t dev)
346 {
347 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
348 struct xgbe_prv_data *pdata = &sc->pdata;
349 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
350 if_t ifp = pdata->netdev;
351 int bmsr;
352
353 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
354 pdata->phy_link);
355
356 if (mii == NULL || ifp == NULL ||
357 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
358 return;
359
360 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
361 (IFM_ACTIVE | IFM_AVALID)) {
362
363 switch (IFM_SUBTYPE(mii->mii_media_active)) {
364 case IFM_10_T:
365 case IFM_100_TX:
366 pdata->phy.link = 1;
367 break;
368 case IFM_1000_T:
369 case IFM_1000_SX:
370 case IFM_2500_SX:
371 pdata->phy.link = 1;
372 break;
373 default:
374 pdata->phy.link = 0;
375 break;
376 }
377 } else
378 pdata->phy_link = 0;
379
380 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
381 if (bmsr & BMSR_ANEG) {
382
383 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
384
385 /* Raise AN Interrupt */
386 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
387 XGBE_AN_CL73_INT_MASK);
388 }
389 }
390
391 static int
axgbe_if_attach_pre(if_ctx_t ctx)392 axgbe_if_attach_pre(if_ctx_t ctx)
393 {
394 struct axgbe_if_softc *sc;
395 struct xgbe_prv_data *pdata;
396 struct resource *mac_res[2];
397 if_softc_ctx_t scctx;
398 if_shared_ctx_t sctx;
399 device_t dev;
400 device_t rdev;
401 unsigned int ma_lo, ma_hi;
402 unsigned int reg;
403 int ret;
404
405 sc = iflib_get_softc(ctx);
406 sc->pdata.dev = dev = iflib_get_dev(ctx);
407 sc->sctx = sctx = iflib_get_sctx(ctx);
408 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
409 sc->media = iflib_get_media(ctx);
410 sc->ctx = ctx;
411 sc->link_status = LINK_STATE_DOWN;
412 pdata = &sc->pdata;
413 pdata->netdev = iflib_get_ifp(ctx);
414
415 spin_lock_init(&pdata->xpcs_lock);
416
417 /* Initialize locks */
418 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
419 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
420
421 /* Allocate VLAN bitmap */
422 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
423 pdata->num_active_vlans = 0;
424
425 /* Get the version data */
426 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
427 if (pci_get_device(dev) == 0x1458)
428 sc->pdata.vdata = &xgbe_v2a;
429 else if (pci_get_device(dev) == 0x1459)
430 sc->pdata.vdata = &xgbe_v2b;
431
432 /* PCI setup */
433 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) {
434 axgbe_error("Unable to allocate bus resources\n");
435 ret = ENXIO;
436 goto free_vlans;
437 }
438
439 sc->pdata.xgmac_res = mac_res[0];
440 sc->pdata.xpcs_res = mac_res[1];
441
442 /*
443 * Set the PCS indirect addressing definition registers.
444 * A newer version of the hardware is using the same PCI ids
445 * for the network device but has altered register definitions
446 * for determining the window settings for the indirect PCS access.
447 * This code checks hardware usage and uses the register values
448 * accordingly.
449 */
450 rdev = pci_find_dbsf(0, 0, 0, 0);
451 if (rdev && pci_get_device(rdev) == 0x15d0
452 && pci_get_vendor(rdev) == 0x1022) {
453 pdata->xpcs_window_def_reg = PCS_V2_RV_WINDOW_DEF;
454 pdata->xpcs_window_sel_reg = PCS_V2_RV_WINDOW_SELECT;
455 } else {
456 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
457 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
458 }
459
460 /* Configure the PCS indirect addressing support */
461 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
462 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
463 pdata->xpcs_window <<= 6;
464 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
465 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
466 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
467 DBGPR("xpcs window def : %#010x\n",
468 pdata->xpcs_window_def_reg);
469 DBGPR("xpcs window sel : %#010x\n",
470 pdata->xpcs_window_sel_reg);
471 DBGPR("xpcs window : %#010x\n",
472 pdata->xpcs_window);
473 DBGPR("xpcs window size : %#010x\n",
474 pdata->xpcs_window_size);
475 DBGPR("xpcs window mask : %#010x\n",
476 pdata->xpcs_window_mask);
477
478 /* Enable all interrupts in the hardware */
479 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
480
481 /* Retrieve the MAC address */
482 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
483 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
484 pdata->mac_addr[0] = ma_lo & 0xff;
485 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
486 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
487 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
488 pdata->mac_addr[4] = ma_hi & 0xff;
489 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
490 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
491 axgbe_error("Invalid mac address\n");
492 ret = EINVAL;
493 goto release_bus_resource;
494 }
495 iflib_set_mac(ctx, pdata->mac_addr);
496
497 /* Clock settings */
498 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
499 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
500
501 /* Set the DMA coherency values */
502 pdata->coherent = 1;
503 pdata->arcr = XGBE_DMA_PCI_ARCR;
504 pdata->awcr = XGBE_DMA_PCI_AWCR;
505 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
506
507 /* Read the port property registers */
508 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
509 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
510 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
511 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
512 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
513 DBGPR("port property 0 = %#010x\n", pdata->pp0);
514 DBGPR("port property 1 = %#010x\n", pdata->pp1);
515 DBGPR("port property 2 = %#010x\n", pdata->pp2);
516 DBGPR("port property 3 = %#010x\n", pdata->pp3);
517 DBGPR("port property 4 = %#010x\n", pdata->pp4);
518
519 /* Set the maximum channels and queues */
520 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
521 MAX_TX_DMA);
522 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
523 MAX_RX_DMA);
524 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
525 MAX_TX_QUEUES);
526 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
527 MAX_RX_QUEUES);
528 DBGPR("max tx/rx channel count = %u/%u\n",
529 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
530 DBGPR("max tx/rx hw queue count = %u/%u\n",
531 pdata->tx_max_q_count, pdata->rx_max_q_count);
532
533 axgbe_set_counts(ctx);
534
535 /* Set the maximum fifo amounts */
536 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
537 TX_FIFO_SIZE);
538 pdata->tx_max_fifo_size *= 16384;
539 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
540 pdata->vdata->tx_max_fifo_size);
541 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
542 RX_FIFO_SIZE);
543 pdata->rx_max_fifo_size *= 16384;
544 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
545 pdata->vdata->rx_max_fifo_size);
546 DBGPR("max tx/rx max fifo size = %u/%u\n",
547 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
548
549 /* Initialize IFLIB if_softc_ctx_t */
550 axgbe_init_iflib_softc_ctx(sc);
551
552 /* Alloc channels */
553 if (axgbe_alloc_channels(ctx)) {
554 axgbe_error("Unable to allocate channel memory\n");
555 ret = ENOMEM;
556 goto release_bus_resource;
557 }
558
559 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
560
561 /* create the workqueue */
562 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
563 taskqueue_thread_enqueue, &pdata->dev_workqueue);
564 if (pdata->dev_workqueue == NULL) {
565 axgbe_error("Unable to allocate workqueue\n");
566 ret = ENOMEM;
567 goto free_channels;
568 }
569 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
570 "axgbe dev taskq");
571 if (ret) {
572 axgbe_error("Unable to start taskqueue\n");
573 ret = ENOMEM;
574 goto free_task_queue;
575 }
576
577 /* Init timers */
578 xgbe_init_timers(pdata);
579
580 return (0);
581
582 free_task_queue:
583 taskqueue_free(pdata->dev_workqueue);
584
585 free_channels:
586 axgbe_free_channels(sc);
587
588 release_bus_resource:
589 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res);
590
591 free_vlans:
592 free(pdata->active_vlans, M_AXGBE);
593
594 return (ret);
595 } /* axgbe_if_attach_pre */
596
597 static void
xgbe_init_all_fptrs(struct xgbe_prv_data * pdata)598 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
599 {
600 xgbe_init_function_ptrs_dev(&pdata->hw_if);
601 xgbe_init_function_ptrs_phy(&pdata->phy_if);
602 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
603 xgbe_init_function_ptrs_desc(&pdata->desc_if);
604
605 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
606 }
607
608 static void
axgbe_set_counts(if_ctx_t ctx)609 axgbe_set_counts(if_ctx_t ctx)
610 {
611 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
612 struct xgbe_prv_data *pdata = &sc->pdata;
613 cpuset_t lcpus;
614
615 /* Set all function pointers */
616 xgbe_init_all_fptrs(pdata);
617
618 /* Populate the hardware features */
619 xgbe_get_all_hw_features(pdata);
620
621 if (!pdata->tx_max_channel_count)
622 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
623 if (!pdata->rx_max_channel_count)
624 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
625
626 if (!pdata->tx_max_q_count)
627 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
628 if (!pdata->rx_max_q_count)
629 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
630
631 /*
632 * Calculate the number of Tx and Rx rings to be created
633 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
634 * the number of Tx queues to the number of Tx channels
635 * enabled
636 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
637 * number of Rx queues or maximum allowed
638 */
639
640 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
641 axgbe_error("Unable to fetch CPU list\n");
642 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
643 }
644
645 DBGPR("ncpu %d intrcpu %d\n", mp_ncpus, CPU_COUNT(&lcpus));
646
647 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
648 pdata->tx_ring_count = min(pdata->tx_ring_count,
649 pdata->tx_max_channel_count);
650 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
651
652 pdata->tx_q_count = pdata->tx_ring_count;
653
654 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
655 pdata->rx_ring_count = min(pdata->rx_ring_count,
656 pdata->rx_max_channel_count);
657
658 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
659
660 DBGPR("TX/RX max channel count = %u/%u\n",
661 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
662 DBGPR("TX/RX max queue count = %u/%u\n",
663 pdata->tx_max_q_count, pdata->rx_max_q_count);
664 DBGPR("TX/RX DMA ring count = %u/%u\n",
665 pdata->tx_ring_count, pdata->rx_ring_count);
666 DBGPR("TX/RX hardware queue count = %u/%u\n",
667 pdata->tx_q_count, pdata->rx_q_count);
668 } /* axgbe_set_counts */
669
670 static void
axgbe_init_iflib_softc_ctx(struct axgbe_if_softc * sc)671 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
672 {
673 struct xgbe_prv_data *pdata = &sc->pdata;
674 if_softc_ctx_t scctx = sc->scctx;
675 if_shared_ctx_t sctx = sc->sctx;
676 int i;
677
678 scctx->isc_nrxqsets = pdata->rx_q_count;
679 scctx->isc_ntxqsets = pdata->tx_q_count;
680 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
681 scctx->isc_tx_nsegments = 32;
682
683 for (i = 0; i < sctx->isc_ntxqs; i++) {
684 scctx->isc_txqsizes[i] =
685 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
686 128);
687 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
688 }
689
690 for (i = 0; i < sctx->isc_nrxqs; i++) {
691 scctx->isc_rxqsizes[i] =
692 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
693 128);
694 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
695 }
696
697 scctx->isc_tx_tso_segments_max = 32;
698 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
699 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
700
701 /*
702 * Set capabilities
703 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
704 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
705 * IFCAP_HWCSUM) is set
706 */
707 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
708 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
709 CSUM_TSO);
710 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
711 IFCAP_JUMBO_MTU |
712 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
713 IFCAP_VLAN_HWCSUM |
714 IFCAP_TSO | IFCAP_VLAN_HWTSO);
715 scctx->isc_capabilities = scctx->isc_capenable;
716
717 /*
718 * Set rss_table_size alone when adding RSS support. rss_table_mask
719 * will be set by IFLIB based on rss_table_size
720 */
721 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
722
723 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
724 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
725
726 scctx->isc_txrx = &axgbe_txrx;
727 }
728
729 static void
axgbe_initialize_rss_mapping(struct xgbe_prv_data * pdata)730 axgbe_initialize_rss_mapping(struct xgbe_prv_data *pdata)
731 {
732 int i;
733
734 /* Get RSS key */
735 #ifdef RSS
736 int qid;
737 uint32_t rss_hash_config = 0;
738
739 rss_getkey((uint8_t *)&pdata->rss_key);
740
741 rss_hash_config = rss_gethashconfig();
742
743 if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
744 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
745 if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
746 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
747 if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
748 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
749 #else
750 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
751
752 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
753 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
754 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
755 #endif
756
757 /* Setup RSS lookup table */
758 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++) {
759 #ifdef RSS
760 qid = rss_get_indirection_to_bucket(i) % pdata->rx_ring_count;
761 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, qid);
762 #else
763 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
764 i % pdata->rx_ring_count);
765 #endif
766 }
767
768 }
769
770 static int
axgbe_alloc_channels(if_ctx_t ctx)771 axgbe_alloc_channels(if_ctx_t ctx)
772 {
773 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
774 struct xgbe_prv_data *pdata = &sc->pdata;
775 struct xgbe_channel *channel;
776 int i, j, count;
777
778 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
779 pdata->rx_ring_count);
780
781 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
782 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
783
784 /* Allocate channel memory */
785 for (i = 0; i < count ; i++) {
786 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
787 M_AXGBE, M_NOWAIT | M_ZERO);
788
789 if (channel == NULL) {
790 for (j = 0; j < i; j++) {
791 free(pdata->channel[j], M_AXGBE);
792 pdata->channel[j] = NULL;
793 }
794 return (ENOMEM);
795 }
796
797 pdata->channel[i] = channel;
798 }
799
800 pdata->total_channel_count = count;
801 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
802
803 for (i = 0; i < count; i++) {
804
805 channel = pdata->channel[i];
806 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
807
808 channel->pdata = pdata;
809 channel->queue_index = i;
810 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
811 bus_space_subregion(channel->dma_tag,
812 rman_get_bushandle(pdata->xgmac_res),
813 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
814 &channel->dma_handle);
815 channel->tx_ring = NULL;
816 channel->rx_ring = NULL;
817 }
818
819 return (0);
820 } /* axgbe_alloc_channels */
821
822 static void
axgbe_free_channels(struct axgbe_if_softc * sc)823 axgbe_free_channels(struct axgbe_if_softc *sc)
824 {
825 struct xgbe_prv_data *pdata = &sc->pdata;
826 int i;
827
828 for (i = 0; i < pdata->total_channel_count ; i++) {
829 free(pdata->channel[i], M_AXGBE);
830 pdata->channel[i] = NULL;
831 }
832
833 pdata->total_channel_count = 0;
834 pdata->channel_count = 0;
835 }
836
837 static void
xgbe_service(void * ctx,int pending)838 xgbe_service(void *ctx, int pending)
839 {
840 struct xgbe_prv_data *pdata = ctx;
841 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
842 bool prev_state = false;
843
844 /* Get previous link status */
845 prev_state = pdata->phy.link;
846
847 pdata->phy_if.phy_status(pdata);
848
849 if (prev_state != pdata->phy.link) {
850 pdata->phy_link = pdata->phy.link;
851 axgbe_if_update_admin_status(sc->ctx);
852 }
853
854 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
855 }
856
857 static void
xgbe_service_timer(void * data)858 xgbe_service_timer(void *data)
859 {
860 struct xgbe_prv_data *pdata = data;
861
862 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
863 }
864
865 static void
xgbe_init_timers(struct xgbe_prv_data * pdata)866 xgbe_init_timers(struct xgbe_prv_data *pdata)
867 {
868 callout_init(&pdata->service_timer, 1);
869 }
870
871 static void
xgbe_start_timers(struct xgbe_prv_data * pdata)872 xgbe_start_timers(struct xgbe_prv_data *pdata)
873 {
874 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
875 }
876
877 static void
xgbe_stop_timers(struct xgbe_prv_data * pdata)878 xgbe_stop_timers(struct xgbe_prv_data *pdata)
879 {
880 callout_drain(&pdata->service_timer);
881 callout_stop(&pdata->service_timer);
882 }
883
884 static void
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)885 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
886 {
887 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
888
889 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
890 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
891 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
892 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
893 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
894 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
895 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
896 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
897 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
898 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
899 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
900 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
901 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
902 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
903 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
904 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
905 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
906 MDIO_AN_ADVERTISE,
907 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
908 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
909 MDIO_AN_ADVERTISE + 1,
910 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
911 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
912 MDIO_AN_ADVERTISE + 2,
913 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
914 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
915 MDIO_AN_COMP_STAT,
916 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
917
918 axgbe_printf(1, "\n************************************************\n");
919 }
920
921 static void
xgbe_dump_prop_registers(struct xgbe_prv_data * pdata)922 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
923 {
924 int i;
925
926 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
927
928 for (i = 0 ; i < 38 ; i++) {
929 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
930 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
931 (XP_PROP_0 + (i * 4))));
932 }
933 }
934
935 static void
xgbe_dump_dma_registers(struct xgbe_prv_data * pdata,int ch)936 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
937 {
938 struct xgbe_channel *channel;
939 int i;
940
941 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
942
943 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
944 XGMAC_IOREAD(pdata, DMA_MR));
945 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
946 XGMAC_IOREAD(pdata, DMA_SBMR));
947 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
948 XGMAC_IOREAD(pdata, DMA_ISR));
949 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
950 XGMAC_IOREAD(pdata, DMA_AXIARCR));
951 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
952 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
953 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
954 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
955 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
956 XGMAC_IOREAD(pdata, DMA_DSR0));
957 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
958 XGMAC_IOREAD(pdata, DMA_DSR1));
959 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
960 XGMAC_IOREAD(pdata, DMA_DSR2));
961 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
962 XGMAC_IOREAD(pdata, DMA_DSR3));
963 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
964 XGMAC_IOREAD(pdata, DMA_DSR4));
965 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
966 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
967 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
968 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
969
970 for (i = 0 ; i < 8 ; i++ ) {
971
972 if (ch >= 0) {
973 if (i != ch)
974 continue;
975 }
976
977 channel = pdata->channel[i];
978
979 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
980
981 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
982 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
983 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
984 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
985 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
986 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
987 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
988 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
989 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
990 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
991 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
992 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
993 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
994 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
995 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
996 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
997 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
998 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
999 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
1000 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
1001 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
1002 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
1003 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
1004 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
1005 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
1006 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
1007 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
1008 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
1009 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
1010 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
1011 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
1012 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
1013 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
1014 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
1015 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
1016 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
1017 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
1018 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
1019 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
1020 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
1021 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
1022 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
1023 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
1024 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
1025 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
1026 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
1027 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
1028 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
1029 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
1030 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
1031 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
1032 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
1033 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
1034 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
1035 }
1036 }
1037
1038 static void
xgbe_dump_mtl_registers(struct xgbe_prv_data * pdata)1039 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
1040 {
1041 int i;
1042
1043 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
1044
1045 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
1046 XGMAC_IOREAD(pdata, MTL_OMR));
1047 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
1048 XGMAC_IOREAD(pdata, MTL_FDCR));
1049 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
1050 XGMAC_IOREAD(pdata, MTL_FDSR));
1051 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
1052 XGMAC_IOREAD(pdata, MTL_FDDR));
1053 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
1054 XGMAC_IOREAD(pdata, MTL_ISR));
1055 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
1056 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
1057 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
1058 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
1059 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
1060 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
1061 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
1062 XGMAC_IOREAD(pdata, MTL_TCPM0R));
1063 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
1064 XGMAC_IOREAD(pdata, MTL_TCPM1R));
1065
1066 for (i = 0 ; i < 8 ; i++ ) {
1067
1068 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
1069
1070 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
1071 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1072 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
1073 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1074 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
1075 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1076 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
1077 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1078 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
1079 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1080 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
1081 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1082
1083 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
1084 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1085 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
1086 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1087 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
1088 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1089 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
1090 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1091 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
1092 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1093 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
1094 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1095 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
1096 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1097 }
1098 }
1099
1100 static void
xgbe_dump_mac_registers(struct xgbe_prv_data * pdata)1101 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1102 {
1103 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
1104
1105 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
1106 XGMAC_IOREAD(pdata, MAC_TCR));
1107 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
1108 XGMAC_IOREAD(pdata, MAC_RCR));
1109 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
1110 XGMAC_IOREAD(pdata, MAC_PFR));
1111 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
1112 XGMAC_IOREAD(pdata, MAC_WTR));
1113 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
1114 XGMAC_IOREAD(pdata, MAC_HTR0));
1115 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
1116 XGMAC_IOREAD(pdata, MAC_HTR1));
1117 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
1118 XGMAC_IOREAD(pdata, MAC_HTR2));
1119 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
1120 XGMAC_IOREAD(pdata, MAC_HTR3));
1121 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
1122 XGMAC_IOREAD(pdata, MAC_HTR4));
1123 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
1124 XGMAC_IOREAD(pdata, MAC_HTR5));
1125 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
1126 XGMAC_IOREAD(pdata, MAC_HTR6));
1127 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
1128 XGMAC_IOREAD(pdata, MAC_HTR7));
1129 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1130 XGMAC_IOREAD(pdata, MAC_VLANTR));
1131 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1132 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1133 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1134 XGMAC_IOREAD(pdata, MAC_VLANIR));
1135 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1136 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1137 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1138 XGMAC_IOREAD(pdata, MAC_RETMR));
1139 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1140 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1141 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1142 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1143 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1144 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1145 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1146 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1147 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1148 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1149 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1150 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1151 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1152 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1153 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1154 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1155 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1156 XGMAC_IOREAD(pdata, MAC_RFCR));
1157 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1158 XGMAC_IOREAD(pdata, MAC_RQC0R));
1159 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1160 XGMAC_IOREAD(pdata, MAC_RQC1R));
1161 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1162 XGMAC_IOREAD(pdata, MAC_RQC2R));
1163 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1164 XGMAC_IOREAD(pdata, MAC_RQC3R));
1165 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1166 XGMAC_IOREAD(pdata, MAC_ISR));
1167 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1168 XGMAC_IOREAD(pdata, MAC_IER));
1169 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1170 XGMAC_IOREAD(pdata, MAC_RTSR));
1171 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1172 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1173 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1174 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1175 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1176 XGMAC_IOREAD(pdata, MAC_LPICSR));
1177 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1178 XGMAC_IOREAD(pdata, MAC_LPITCR));
1179 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1180 XGMAC_IOREAD(pdata, MAC_TIR));
1181 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1182 XGMAC_IOREAD(pdata, MAC_VR));
1183 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1184 XGMAC_IOREAD(pdata, MAC_DR));
1185 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1186 XGMAC_IOREAD(pdata, MAC_HWF0R));
1187 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1188 XGMAC_IOREAD(pdata, MAC_HWF1R));
1189 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1190 XGMAC_IOREAD(pdata, MAC_HWF2R));
1191 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1192 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1193 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1194 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1195 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1196 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1197 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1198 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1199 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1200 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1201 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1202 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1203 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1204 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1205 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1206 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1207 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1208 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1209 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1210 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1211 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1212 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1213 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1214 XGMAC_IOREAD(pdata, MAC_RSSCR));
1215 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1216 XGMAC_IOREAD(pdata, MAC_RSSDR));
1217 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1218 XGMAC_IOREAD(pdata, MAC_RSSAR));
1219 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1220 XGMAC_IOREAD(pdata, MAC_TSCR));
1221 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1222 XGMAC_IOREAD(pdata, MAC_SSIR));
1223 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1224 XGMAC_IOREAD(pdata, MAC_STSR));
1225 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1226 XGMAC_IOREAD(pdata, MAC_STNR));
1227 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1228 XGMAC_IOREAD(pdata, MAC_STSUR));
1229 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1230 XGMAC_IOREAD(pdata, MAC_STNUR));
1231 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1232 XGMAC_IOREAD(pdata, MAC_TSAR));
1233 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1234 XGMAC_IOREAD(pdata, MAC_TSSR));
1235 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1236 XGMAC_IOREAD(pdata, MAC_TXSNR));
1237 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1238 XGMAC_IOREAD(pdata, MAC_TXSSR));
1239 }
1240
1241 static void
xgbe_dump_rmon_counters(struct xgbe_prv_data * pdata)1242 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1243 {
1244 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1245
1246 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1247
1248 pdata->hw_if.read_mmc_stats(pdata);
1249
1250 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1251 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1252 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1253 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1254 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1255 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1256 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1257 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1258 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1259 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1260 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1261 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1262 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1263 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1264 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1265 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1266 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1267 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1268 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1269 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1270 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1271 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1272 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1273 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1274 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1275 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1276 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1277 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1278 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1279 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1280 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1281 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1282 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1283 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1284 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1285 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1286 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1287 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1288 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1289 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1290 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1291 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1292 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1293 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1294 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1295 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1296 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1297 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1298 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1299 MMC_RXRUNTERROR, stats->rxrunterror);
1300 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1301 MMC_RXJABBERERROR, stats->rxjabbererror);
1302 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1303 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1304 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1305 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1306 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1307 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1308 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1309 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1310 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1311 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1312 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1313 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1314 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1315 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1316 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1317 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1318 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1319 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1320 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1321 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1322 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1323 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1324 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1325 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1326 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1327 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1328 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1329 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1330 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1331 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1332 }
1333
1334 void
xgbe_dump_i2c_registers(struct xgbe_prv_data * pdata)1335 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1336 {
1337 axgbe_printf(1, "*************** I2C Registers **************\n");
1338 axgbe_printf(1, " IC_CON : %010x\n",
1339 XI2C_IOREAD(pdata, 0x00));
1340 axgbe_printf(1, " IC_TAR : %010x\n",
1341 XI2C_IOREAD(pdata, 0x04));
1342 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1343 XI2C_IOREAD(pdata, 0x0c));
1344 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1345 XI2C_IOREAD(pdata, 0x2c));
1346 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1347 XI2C_IOREAD(pdata, 0x30));
1348 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1349 XI2C_IOREAD(pdata, 0x34));
1350 axgbe_printf(1, " IC_RX_TL : %010x\n",
1351 XI2C_IOREAD(pdata, 0x38));
1352 axgbe_printf(1, " IC_TX_TL : %010x\n",
1353 XI2C_IOREAD(pdata, 0x3c));
1354 axgbe_printf(1, " IC_ENABLE : %010x\n",
1355 XI2C_IOREAD(pdata, 0x6c));
1356 axgbe_printf(1, " IC_STATUS : %010x\n",
1357 XI2C_IOREAD(pdata, 0x70));
1358 axgbe_printf(1, " IC_TXFLR : %010x\n",
1359 XI2C_IOREAD(pdata, 0x74));
1360 axgbe_printf(1, " IC_RXFLR : %010x\n",
1361 XI2C_IOREAD(pdata, 0x78));
1362 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1363 XI2C_IOREAD(pdata, 0x9c));
1364 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1365 XI2C_IOREAD(pdata, 0xf4));
1366 }
1367
1368 static void
xgbe_dump_active_vlans(struct xgbe_prv_data * pdata)1369 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1370 {
1371 int i;
1372
1373 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1374 if (i && (i%8 == 0))
1375 axgbe_printf(1, "\n");
1376 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1377 }
1378 axgbe_printf(1, "\n");
1379 }
1380
1381 static void
xgbe_default_config(struct xgbe_prv_data * pdata)1382 xgbe_default_config(struct xgbe_prv_data *pdata)
1383 {
1384 pdata->blen = DMA_SBMR_BLEN_64;
1385 pdata->pbl = DMA_PBL_128;
1386 pdata->aal = 1;
1387 pdata->rd_osr_limit = 8;
1388 pdata->wr_osr_limit = 8;
1389 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1390 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1391 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1392 pdata->rx_sf_mode = MTL_RSF_ENABLE;
1393 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1394 pdata->pause_autoneg = 1;
1395 pdata->phy_speed = SPEED_UNKNOWN;
1396 pdata->power_down = 0;
1397 pdata->enable_rss = 1;
1398 }
1399
1400 static int
axgbe_if_attach_post(if_ctx_t ctx)1401 axgbe_if_attach_post(if_ctx_t ctx)
1402 {
1403 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1404 struct xgbe_prv_data *pdata = &sc->pdata;
1405 if_t ifp = pdata->netdev;
1406 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1407 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1408 if_softc_ctx_t scctx = sc->scctx;
1409 int ret;
1410
1411 /* set split header support based on tunable */
1412 pdata->sph_enable = axgbe_sph_enable;
1413
1414 /* Initialize ECC timestamps */
1415 pdata->tx_sec_period = ticks;
1416 pdata->tx_ded_period = ticks;
1417 pdata->rx_sec_period = ticks;
1418 pdata->rx_ded_period = ticks;
1419 pdata->desc_sec_period = ticks;
1420 pdata->desc_ded_period = ticks;
1421
1422 /* Reset the hardware */
1423 ret = hw_if->exit(&sc->pdata);
1424 if (ret)
1425 axgbe_error("%s: exit error %d\n", __func__, ret);
1426
1427 axgbe_sysctl_init(pdata);
1428
1429 /* Configure the defaults */
1430 xgbe_default_config(pdata);
1431
1432 /* Set default max values if not provided */
1433 if (!pdata->tx_max_fifo_size)
1434 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1435 if (!pdata->rx_max_fifo_size)
1436 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1437
1438 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1439 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1440
1441 /* Set and validate the number of descriptors for a ring */
1442 MPASS(powerof2(XGBE_TX_DESC_CNT));
1443 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1444 MPASS(powerof2(XGBE_RX_DESC_CNT));
1445 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1446
1447 /* Adjust the number of queues based on interrupts assigned */
1448 if (pdata->channel_irq_count) {
1449 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1450 pdata->channel_irq_count);
1451 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1452 pdata->channel_irq_count);
1453
1454 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1455 pdata->tx_ring_count, pdata->tx_q_count,
1456 pdata->rx_ring_count, pdata->rx_q_count);
1457 }
1458
1459 /* Set channel count based on interrupts assigned */
1460 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1461 scctx->isc_nrxqsets);
1462 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1463
1464 axgbe_initialize_rss_mapping(pdata);
1465
1466 /* Initialize the PHY device */
1467 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1468 phy_if->phy_init(pdata);
1469
1470 /* Set the coalescing */
1471 xgbe_init_rx_coalesce(&sc->pdata);
1472 xgbe_init_tx_coalesce(&sc->pdata);
1473
1474 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1475 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1476 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1477 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1478 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1479 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1480 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1481 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1482 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1483 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1484 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1485 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1486 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1487
1488 /* Initialize the phy */
1489 pdata->phy_link = -1;
1490 pdata->phy_speed = SPEED_UNKNOWN;
1491 ret = phy_if->phy_reset(pdata);
1492 if (ret)
1493 return (ret);
1494
1495 /* Calculate the Rx buffer size before allocating rings */
1496 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1497 pdata->rx_buf_size = ret;
1498 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1499
1500 /*
1501 * Mark the device down until it is initialized, which happens
1502 * when the device is accessed first (for configuring the iface,
1503 * eg: setting IP)
1504 */
1505 set_bit(XGBE_DOWN, &pdata->dev_state);
1506
1507 DBGPR("mtu %d\n", if_getmtu(ifp));
1508 scctx->isc_max_frame_size = if_getmtu(ifp) + 18;
1509 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1510
1511 axgbe_pci_init(pdata);
1512
1513 return (0);
1514 } /* axgbe_if_attach_post */
1515
1516 static void
xgbe_free_intr(struct xgbe_prv_data * pdata,struct resource * res,void * tag,int rid)1517 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1518 int rid)
1519 {
1520 if (tag)
1521 bus_teardown_intr(pdata->dev, res, tag);
1522
1523 if (res)
1524 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1525 }
1526
1527 static void
axgbe_interrupts_free(if_ctx_t ctx)1528 axgbe_interrupts_free(if_ctx_t ctx)
1529 {
1530 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1531 struct xgbe_prv_data *pdata = &sc->pdata;
1532 if_softc_ctx_t scctx = sc->scctx;
1533 struct xgbe_channel *channel;
1534 struct if_irq irq;
1535 int i;
1536
1537 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1538
1539 /* Free dev_irq */
1540 iflib_irq_free(ctx, &pdata->dev_irq);
1541
1542 /* Free ecc_irq */
1543 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1544 pdata->ecc_rid);
1545
1546 /* Free i2c_irq */
1547 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1548 pdata->i2c_rid);
1549
1550 /* Free an_irq */
1551 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1552 pdata->an_rid);
1553
1554 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1555
1556 channel = pdata->channel[i];
1557 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1558 irq.ii_res = channel->dma_irq_res;
1559 irq.ii_tag = channel->dma_irq_tag;
1560 iflib_irq_free(ctx, &irq);
1561 }
1562 }
1563
1564 static int
axgbe_if_detach(if_ctx_t ctx)1565 axgbe_if_detach(if_ctx_t ctx)
1566 {
1567 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1568 struct xgbe_prv_data *pdata = &sc->pdata;
1569 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1570 struct resource *mac_res[2];
1571
1572 mac_res[0] = pdata->xgmac_res;
1573 mac_res[1] = pdata->xpcs_res;
1574
1575 phy_if->phy_stop(pdata);
1576 phy_if->phy_exit(pdata);
1577
1578 /* Free Interrupts */
1579 axgbe_interrupts_free(ctx);
1580
1581 /* Free workqueues */
1582 taskqueue_free(pdata->dev_workqueue);
1583
1584 /* Release bus resources */
1585 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1586
1587 /* Free VLAN bitmap */
1588 free(pdata->active_vlans, M_AXGBE);
1589
1590 axgbe_sysctl_exit(pdata);
1591
1592 return (0);
1593 } /* axgbe_if_detach */
1594
1595 static void
axgbe_pci_init(struct xgbe_prv_data * pdata)1596 axgbe_pci_init(struct xgbe_prv_data *pdata)
1597 {
1598 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1599 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1600 int ret = 0;
1601
1602 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1603 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__);
1604 return;
1605 }
1606
1607 hw_if->init(pdata);
1608
1609 ret = phy_if->phy_start(pdata);
1610 if (ret) {
1611 axgbe_error("%s: phy start %d\n", __func__, ret);
1612 ret = hw_if->exit(pdata);
1613 if (ret)
1614 axgbe_error("%s: exit error %d\n", __func__, ret);
1615 return;
1616 }
1617
1618 hw_if->enable_tx(pdata);
1619 hw_if->enable_rx(pdata);
1620
1621 xgbe_start_timers(pdata);
1622
1623 clear_bit(XGBE_DOWN, &pdata->dev_state);
1624
1625 xgbe_dump_phy_registers(pdata);
1626 xgbe_dump_prop_registers(pdata);
1627 xgbe_dump_dma_registers(pdata, -1);
1628 xgbe_dump_mtl_registers(pdata);
1629 xgbe_dump_mac_registers(pdata);
1630 xgbe_dump_rmon_counters(pdata);
1631 }
1632
1633 static void
axgbe_if_init(if_ctx_t ctx)1634 axgbe_if_init(if_ctx_t ctx)
1635 {
1636 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1637 struct xgbe_prv_data *pdata = &sc->pdata;
1638
1639 axgbe_pci_init(pdata);
1640 }
1641
1642 static void
axgbe_pci_stop(if_ctx_t ctx)1643 axgbe_pci_stop(if_ctx_t ctx)
1644 {
1645 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1646 struct xgbe_prv_data *pdata = &sc->pdata;
1647 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1648 int ret;
1649
1650 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1651 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1652 return;
1653 }
1654
1655 xgbe_stop_timers(pdata);
1656 taskqueue_drain_all(pdata->dev_workqueue);
1657
1658 hw_if->disable_tx(pdata);
1659 hw_if->disable_rx(pdata);
1660
1661 ret = hw_if->exit(pdata);
1662 if (ret)
1663 axgbe_error("%s: exit error %d\n", __func__, ret);
1664
1665 set_bit(XGBE_DOWN, &pdata->dev_state);
1666 }
1667
1668 static void
axgbe_if_stop(if_ctx_t ctx)1669 axgbe_if_stop(if_ctx_t ctx)
1670 {
1671 axgbe_pci_stop(ctx);
1672 }
1673
1674 static void
axgbe_if_disable_intr(if_ctx_t ctx)1675 axgbe_if_disable_intr(if_ctx_t ctx)
1676 {
1677 /* TODO - implement */
1678 }
1679
1680 static void
axgbe_if_enable_intr(if_ctx_t ctx)1681 axgbe_if_enable_intr(if_ctx_t ctx)
1682 {
1683 /* TODO - implement */
1684 }
1685
1686 static int
axgbe_if_tx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int ntxqs,int ntxqsets)1687 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1688 int ntxqsets)
1689 {
1690 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1691 struct xgbe_prv_data *pdata = &sc->pdata;
1692 if_softc_ctx_t scctx = sc->scctx;
1693 struct xgbe_channel *channel;
1694 struct xgbe_ring *tx_ring;
1695 int i, j, k;
1696
1697 MPASS(scctx->isc_ntxqsets > 0);
1698 MPASS(scctx->isc_ntxqsets == ntxqsets);
1699 MPASS(ntxqs == 1);
1700
1701 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1702 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1703
1704 for (i = 0 ; i < ntxqsets; i++) {
1705
1706 channel = pdata->channel[i];
1707
1708 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1709 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1710
1711 if (tx_ring == NULL) {
1712 axgbe_error("Unable to allocate TX ring memory\n");
1713 goto tx_ring_fail;
1714 }
1715
1716 channel->tx_ring = tx_ring;
1717
1718 for (j = 0; j < ntxqs; j++, tx_ring++) {
1719 tx_ring->rdata =
1720 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1721 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1722
1723 /* Get the virtual & physical address of hw queues */
1724 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1725 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1726 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1727 spin_lock_init(&tx_ring->lock);
1728 }
1729 }
1730
1731 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1732
1733 return (0);
1734
1735 tx_ring_fail:
1736
1737 for (j = 0; j < i ; j++) {
1738
1739 channel = pdata->channel[j];
1740
1741 tx_ring = channel->tx_ring;
1742 for (k = 0; k < ntxqs ; k++, tx_ring++) {
1743 if (tx_ring && tx_ring->rdata)
1744 free(tx_ring->rdata, M_AXGBE);
1745 }
1746 free(channel->tx_ring, M_AXGBE);
1747
1748 channel->tx_ring = NULL;
1749 }
1750
1751 return (ENOMEM);
1752
1753 } /* axgbe_if_tx_queues_alloc */
1754
1755 static int
axgbe_if_rx_queues_alloc(if_ctx_t ctx,caddr_t * va,uint64_t * pa,int nrxqs,int nrxqsets)1756 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1757 int nrxqsets)
1758 {
1759 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1760 struct xgbe_prv_data *pdata = &sc->pdata;
1761 if_softc_ctx_t scctx = sc->scctx;
1762 struct xgbe_channel *channel;
1763 struct xgbe_ring *rx_ring;
1764 int i, j, k;
1765
1766 MPASS(scctx->isc_nrxqsets > 0);
1767 MPASS(scctx->isc_nrxqsets == nrxqsets);
1768 if (!pdata->sph_enable) {
1769 MPASS(nrxqs == 1);
1770 } else {
1771 MPASS(nrxqs == 2);
1772 }
1773
1774 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1775 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1776
1777 for (i = 0 ; i < nrxqsets; i++) {
1778
1779 channel = pdata->channel[i];
1780
1781 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1782 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1783
1784 if (rx_ring == NULL) {
1785 axgbe_error("Unable to allocate RX ring memory\n");
1786 goto rx_ring_fail;
1787 }
1788
1789 channel->rx_ring = rx_ring;
1790
1791 for (j = 0; j < nrxqs; j++, rx_ring++) {
1792 rx_ring->rdata =
1793 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1794 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1795
1796 /* Get the virtual and physical address of the hw queues */
1797 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1798 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1799 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1800 spin_lock_init(&rx_ring->lock);
1801 }
1802 }
1803
1804 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1805
1806 return (0);
1807
1808 rx_ring_fail:
1809
1810 for (j = 0 ; j < i ; j++) {
1811
1812 channel = pdata->channel[j];
1813
1814 rx_ring = channel->rx_ring;
1815 for (k = 0; k < nrxqs ; k++, rx_ring++) {
1816 if (rx_ring && rx_ring->rdata)
1817 free(rx_ring->rdata, M_AXGBE);
1818 }
1819 free(channel->rx_ring, M_AXGBE);
1820
1821 channel->rx_ring = NULL;
1822 }
1823
1824 return (ENOMEM);
1825
1826 } /* axgbe_if_rx_queues_alloc */
1827
1828 static void
axgbe_if_queues_free(if_ctx_t ctx)1829 axgbe_if_queues_free(if_ctx_t ctx)
1830 {
1831 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1832 struct xgbe_prv_data *pdata = &sc->pdata;
1833 if_softc_ctx_t scctx = sc->scctx;
1834 if_shared_ctx_t sctx = sc->sctx;
1835 struct xgbe_channel *channel;
1836 struct xgbe_ring *tx_ring;
1837 struct xgbe_ring *rx_ring;
1838 int i, j;
1839
1840 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1841
1842 channel = pdata->channel[i];
1843
1844 tx_ring = channel->tx_ring;
1845 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1846 if (tx_ring && tx_ring->rdata)
1847 free(tx_ring->rdata, M_AXGBE);
1848 }
1849 free(channel->tx_ring, M_AXGBE);
1850 channel->tx_ring = NULL;
1851 }
1852
1853 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1854
1855 channel = pdata->channel[i];
1856
1857 rx_ring = channel->rx_ring;
1858 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1859 if (rx_ring && rx_ring->rdata)
1860 free(rx_ring->rdata, M_AXGBE);
1861 }
1862 free(channel->rx_ring, M_AXGBE);
1863 channel->rx_ring = NULL;
1864 }
1865
1866 axgbe_free_channels(sc);
1867 } /* axgbe_if_queues_free */
1868
1869 static void
axgbe_if_vlan_register(if_ctx_t ctx,uint16_t vtag)1870 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1871 {
1872 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1873 struct xgbe_prv_data *pdata = &sc->pdata;
1874 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1875
1876 if (!bit_test(pdata->active_vlans, vtag)) {
1877 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1878
1879 bit_set(pdata->active_vlans, vtag);
1880 hw_if->update_vlan_hash_table(pdata);
1881 pdata->num_active_vlans++;
1882
1883 axgbe_printf(1, "Total active vlans: %d\n",
1884 pdata->num_active_vlans);
1885 } else
1886 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1887
1888 xgbe_dump_active_vlans(pdata);
1889 }
1890
1891 static void
axgbe_if_vlan_unregister(if_ctx_t ctx,uint16_t vtag)1892 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1893 {
1894 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1895 struct xgbe_prv_data *pdata = &sc->pdata;
1896 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1897
1898 if (pdata->num_active_vlans == 0) {
1899 axgbe_printf(1, "No active VLANs to unregister\n");
1900 return;
1901 }
1902
1903 if (bit_test(pdata->active_vlans, vtag)){
1904 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1905
1906 bit_clear(pdata->active_vlans, vtag);
1907 hw_if->update_vlan_hash_table(pdata);
1908 pdata->num_active_vlans--;
1909
1910 axgbe_printf(1, "Total active vlans: %d\n",
1911 pdata->num_active_vlans);
1912 } else
1913 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1914
1915 xgbe_dump_active_vlans(pdata);
1916 }
1917
1918 #if __FreeBSD_version >= 1300000
1919 static bool
axgbe_if_needs_restart(if_ctx_t ctx __unused,enum iflib_restart_event event)1920 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1921 {
1922 switch (event) {
1923 case IFLIB_RESTART_VLAN_CONFIG:
1924 default:
1925 return (true);
1926 }
1927 }
1928 #endif
1929
1930 static int
axgbe_if_msix_intr_assign(if_ctx_t ctx,int msix)1931 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1932 {
1933 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1934 struct xgbe_prv_data *pdata = &sc->pdata;
1935 if_softc_ctx_t scctx = sc->scctx;
1936 struct xgbe_channel *channel;
1937 struct if_irq irq;
1938 int i, error, rid = 0, flags;
1939 char buf[16];
1940
1941 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1942
1943 pdata->isr_as_tasklet = 1;
1944
1945 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1946 pdata->irq_count = 1;
1947 pdata->channel_irq_count = 1;
1948 return (0);
1949 }
1950
1951 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1952 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1953
1954 flags = RF_ACTIVE;
1955
1956 /* DEV INTR SETUP */
1957 rid++;
1958 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1959 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1960 if (error) {
1961 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1962 rid, "dev_irq");
1963 return (error);
1964 }
1965
1966 /* ECC INTR SETUP */
1967 rid++;
1968 pdata->ecc_rid = rid;
1969 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1970 &rid, flags);
1971 if (!pdata->ecc_irq_res) {
1972 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1973 rid, "ecc_irq");
1974 return (ENOMEM);
1975 }
1976
1977 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1978 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1979 if (error) {
1980 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1981 rid, "ecc_irq", error);
1982 return (error);
1983 }
1984
1985 /* I2C INTR SETUP */
1986 rid++;
1987 pdata->i2c_rid = rid;
1988 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1989 &rid, flags);
1990 if (!pdata->i2c_irq_res) {
1991 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1992 rid, "i2c_irq");
1993 return (ENOMEM);
1994 }
1995
1996 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1997 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1998 if (error) {
1999 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
2000 rid, "i2c_irq", error);
2001 return (error);
2002 }
2003
2004 /* AN INTR SETUP */
2005 rid++;
2006 pdata->an_rid = rid;
2007 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
2008 &rid, flags);
2009 if (!pdata->an_irq_res) {
2010 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
2011 rid, "an_irq");
2012 return (ENOMEM);
2013 }
2014
2015 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
2016 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
2017 if (error) {
2018 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
2019 rid, "an_irq", error);
2020 return (error);
2021 }
2022
2023 pdata->per_channel_irq = 1;
2024 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
2025 rid++;
2026 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
2027
2028 channel = pdata->channel[i];
2029
2030 snprintf(buf, sizeof(buf), "rxq%d", i);
2031 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX,
2032 axgbe_msix_que, channel, channel->queue_index, buf);
2033
2034 if (error) {
2035 axgbe_error("Failed to allocated que int %d err: %d\n",
2036 i, error);
2037 return (error);
2038 }
2039
2040 channel->dma_irq_rid = rid;
2041 channel->dma_irq_res = irq.ii_res;
2042 channel->dma_irq_tag = irq.ii_tag;
2043 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
2044 __func__, scctx->isc_nrxqsets, i, rid);
2045 }
2046 pdata->irq_count = msix;
2047 pdata->channel_irq_count = scctx->isc_nrxqsets;
2048
2049 for (i = 0; i < scctx->isc_ntxqsets; i++) {
2050
2051 channel = pdata->channel[i];
2052
2053 snprintf(buf, sizeof(buf), "txq%d", i);
2054 irq.ii_res = channel->dma_irq_res;
2055 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2056 channel->queue_index, buf);
2057 }
2058
2059 return (0);
2060 } /* axgbe_if_msix_intr_assign */
2061
2062 static int
xgbe_enable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2063 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2064 {
2065 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2066 enum xgbe_int int_id;
2067
2068 if (channel->tx_ring && channel->rx_ring)
2069 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2070 else if (channel->tx_ring)
2071 int_id = XGMAC_INT_DMA_CH_SR_TI;
2072 else if (channel->rx_ring)
2073 int_id = XGMAC_INT_DMA_CH_SR_RI;
2074 else
2075 return (-1);
2076
2077 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2078 __func__, channel->queue_index, int_id);
2079 return (hw_if->enable_int(channel, int_id));
2080 }
2081
2082 static void
xgbe_disable_rx_tx_int(struct xgbe_prv_data * pdata,struct xgbe_channel * channel)2083 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2084 {
2085 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2086 enum xgbe_int int_id;
2087
2088 if (channel->tx_ring && channel->rx_ring)
2089 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2090 else if (channel->tx_ring)
2091 int_id = XGMAC_INT_DMA_CH_SR_TI;
2092 else if (channel->rx_ring)
2093 int_id = XGMAC_INT_DMA_CH_SR_RI;
2094 else
2095 return;
2096
2097 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2098 __func__, channel->queue_index, int_id);
2099 hw_if->disable_int(channel, int_id);
2100 }
2101
2102 static void
xgbe_disable_rx_tx_ints(struct xgbe_prv_data * pdata)2103 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2104 {
2105 unsigned int i;
2106
2107 for (i = 0; i < pdata->channel_count; i++)
2108 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2109 }
2110
2111 static int
axgbe_msix_que(void * arg)2112 axgbe_msix_que(void *arg)
2113 {
2114 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2115 struct xgbe_prv_data *pdata = channel->pdata;
2116 unsigned int dma_status;
2117
2118 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2119 __func__, channel->queue_index,
2120 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2121 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2122 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2123 XGMAC_IOREAD(pdata, DMA_ISR),
2124 XGMAC_IOREAD(pdata, MAC_ISR));
2125
2126 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2127
2128 /* Disable Tx and Rx channel interrupts */
2129 xgbe_disable_rx_tx_int(pdata, channel);
2130
2131 /* Clear the interrupts */
2132 dma_status = 0;
2133 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2134 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2135 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2136
2137 return (FILTER_SCHEDULE_THREAD);
2138 }
2139
2140 static int
axgbe_dev_isr(void * arg)2141 axgbe_dev_isr(void *arg)
2142 {
2143 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2144 struct xgbe_prv_data *pdata = &sc->pdata;
2145 struct xgbe_channel *channel;
2146 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2147 unsigned int i, dma_isr, dma_ch_isr;
2148 unsigned int mac_isr, mac_mdioisr;
2149 int ret = FILTER_HANDLED;
2150
2151 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2152 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2153
2154 if (!dma_isr)
2155 return (FILTER_HANDLED);
2156
2157 for (i = 0; i < pdata->channel_count; i++) {
2158
2159 if (!(dma_isr & (1 << i)))
2160 continue;
2161
2162 channel = pdata->channel[i];
2163
2164 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2165 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2166 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2167 DMA_CH_DSR));
2168
2169 /*
2170 * The TI or RI interrupt bits may still be set even if using
2171 * per channel DMA interrupts. Check to be sure those are not
2172 * enabled before using the private data napi structure.
2173 */
2174 if (!pdata->per_channel_irq &&
2175 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2176 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2177
2178 /* Disable Tx and Rx interrupts */
2179 xgbe_disable_rx_tx_ints(pdata);
2180 } else {
2181
2182 /*
2183 * Don't clear Rx/Tx status if doing per channel DMA
2184 * interrupts, these will be cleared by the ISR for
2185 * per channel DMA interrupts
2186 */
2187 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2188 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2189 }
2190
2191 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2192 pdata->ext_stats.rx_buffer_unavailable++;
2193
2194 /* Restart the device on a Fatal Bus Error */
2195 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2196 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2197 __func__, dma_ch_isr);
2198
2199 /* Clear all interrupt signals */
2200 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2201
2202 ret = FILTER_SCHEDULE_THREAD;
2203 }
2204
2205 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2206
2207 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2208 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2209
2210 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2211 hw_if->tx_mmc_int(pdata);
2212
2213 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2214 hw_if->rx_mmc_int(pdata);
2215
2216 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2217 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2218
2219 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2220 SNGLCOMPINT))
2221 wakeup_one(pdata);
2222 }
2223
2224 }
2225
2226 return (ret);
2227 } /* axgbe_dev_isr */
2228
2229 static void
axgbe_i2c_isr(void * arg)2230 axgbe_i2c_isr(void *arg)
2231 {
2232 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2233
2234 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2235 }
2236
2237 static void
axgbe_ecc_isr(void * arg)2238 axgbe_ecc_isr(void *arg)
2239 {
2240 /* TODO - implement */
2241 }
2242
2243 static void
axgbe_an_isr(void * arg)2244 axgbe_an_isr(void *arg)
2245 {
2246 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2247
2248 sc->pdata.phy_if.an_isr(&sc->pdata);
2249 }
2250
2251 static int
axgbe_if_tx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2252 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2253 {
2254 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2255 struct xgbe_prv_data *pdata = &sc->pdata;
2256 int ret;
2257
2258 if (qid < pdata->tx_q_count) {
2259 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2260 if (ret) {
2261 axgbe_error("Enable TX INT failed\n");
2262 return (ret);
2263 }
2264 } else
2265 axgbe_error("Queue ID exceed channel count\n");
2266
2267 return (0);
2268 }
2269
2270 static int
axgbe_if_rx_queue_intr_enable(if_ctx_t ctx,uint16_t qid)2271 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2272 {
2273 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2274 struct xgbe_prv_data *pdata = &sc->pdata;
2275 int ret;
2276
2277 if (qid < pdata->rx_q_count) {
2278 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2279 if (ret) {
2280 axgbe_error("Enable RX INT failed\n");
2281 return (ret);
2282 }
2283 } else
2284 axgbe_error("Queue ID exceed channel count\n");
2285
2286 return (0);
2287 }
2288
2289 static void
axgbe_if_update_admin_status(if_ctx_t ctx)2290 axgbe_if_update_admin_status(if_ctx_t ctx)
2291 {
2292 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2293 struct xgbe_prv_data *pdata = &sc->pdata;
2294
2295 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2296 pdata->phy_link, sc->link_status, pdata->phy.speed);
2297
2298 if (pdata->phy_link < 0)
2299 return;
2300
2301 if (pdata->phy_link) {
2302 if (sc->link_status == LINK_STATE_DOWN) {
2303 sc->link_status = LINK_STATE_UP;
2304 if (pdata->phy.speed & SPEED_10000)
2305 iflib_link_state_change(ctx, LINK_STATE_UP,
2306 IF_Gbps(10));
2307 else if (pdata->phy.speed & SPEED_2500)
2308 iflib_link_state_change(ctx, LINK_STATE_UP,
2309 IF_Gbps(2.5));
2310 else if (pdata->phy.speed & SPEED_1000)
2311 iflib_link_state_change(ctx, LINK_STATE_UP,
2312 IF_Gbps(1));
2313 else if (pdata->phy.speed & SPEED_100)
2314 iflib_link_state_change(ctx, LINK_STATE_UP,
2315 IF_Mbps(100));
2316 else if (pdata->phy.speed & SPEED_10)
2317 iflib_link_state_change(ctx, LINK_STATE_UP,
2318 IF_Mbps(10));
2319 }
2320 } else {
2321 if (sc->link_status == LINK_STATE_UP) {
2322 sc->link_status = LINK_STATE_DOWN;
2323 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2324 }
2325 }
2326 }
2327
2328 static int
axgbe_if_media_change(if_ctx_t ctx)2329 axgbe_if_media_change(if_ctx_t ctx)
2330 {
2331 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2332 struct ifmedia *ifm = iflib_get_media(ctx);
2333
2334 sx_xlock(&sc->pdata.an_mutex);
2335 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2336 return (EINVAL);
2337
2338 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2339 case IFM_10G_KR:
2340 sc->pdata.phy.speed = SPEED_10000;
2341 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2342 break;
2343 case IFM_2500_KX:
2344 sc->pdata.phy.speed = SPEED_2500;
2345 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2346 break;
2347 case IFM_1000_KX:
2348 sc->pdata.phy.speed = SPEED_1000;
2349 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2350 break;
2351 case IFM_100_TX:
2352 sc->pdata.phy.speed = SPEED_100;
2353 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2354 break;
2355 case IFM_AUTO:
2356 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2357 break;
2358 }
2359 sx_xunlock(&sc->pdata.an_mutex);
2360
2361 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2362 }
2363
2364 static int
axgbe_if_promisc_set(if_ctx_t ctx,int flags)2365 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2366 {
2367 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2368 struct xgbe_prv_data *pdata = &sc->pdata;
2369 if_t ifp = pdata->netdev;
2370
2371 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n",
2372 __func__, XGMAC_IOREAD(pdata, MAC_PFR), if_getdrvflags(ifp),
2373 if_getflags(ifp));
2374
2375 if (if_getflags(ifp) & IFF_PPROMISC) {
2376
2377 axgbe_printf(1, "User requested to enter promisc mode\n");
2378
2379 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2380 axgbe_printf(1, "Already in promisc mode\n");
2381 return (0);
2382 }
2383
2384 axgbe_printf(1, "Entering promisc mode\n");
2385 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2386 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2387 } else {
2388
2389 axgbe_printf(1, "User requested to leave promisc mode\n");
2390
2391 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2392 axgbe_printf(1, "Already not in promisc mode\n");
2393 return (0);
2394 }
2395
2396 axgbe_printf(1, "Leaving promisc mode\n");
2397 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2398 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2399 }
2400
2401 return (0);
2402 }
2403
2404 static uint64_t
axgbe_if_get_counter(if_ctx_t ctx,ift_counter cnt)2405 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2406 {
2407 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2408 if_t ifp = iflib_get_ifp(ctx);
2409 struct xgbe_prv_data *pdata = &sc->pdata;
2410 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2411
2412 pdata->hw_if.read_mmc_stats(pdata);
2413
2414 switch(cnt) {
2415 case IFCOUNTER_IPACKETS:
2416 return (pstats->rxframecount_gb);
2417 case IFCOUNTER_IERRORS:
2418 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2419 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2420 case IFCOUNTER_OPACKETS:
2421 return (pstats->txframecount_gb);
2422 case IFCOUNTER_OERRORS:
2423 return (pstats->txframecount_gb - pstats->txframecount_g);
2424 case IFCOUNTER_IBYTES:
2425 return (pstats->rxoctetcount_gb);
2426 case IFCOUNTER_OBYTES:
2427 return (pstats->txoctetcount_gb);
2428 default:
2429 return (if_get_counter_default(ifp, cnt));
2430 }
2431 }
2432
2433 static int
axgbe_if_mtu_set(if_ctx_t ctx,uint32_t mtu)2434 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2435 {
2436 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2437 struct xgbe_prv_data *pdata = &sc->pdata;
2438 int ret;
2439
2440 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2441 return (EINVAL);
2442
2443 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2444 pdata->rx_buf_size = ret;
2445 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2446
2447 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2448 return (0);
2449 }
2450
2451 static void
axgbe_if_media_status(if_ctx_t ctx,struct ifmediareq * ifmr)2452 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2453 {
2454 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2455 struct xgbe_prv_data *pdata = &sc->pdata;
2456
2457 ifmr->ifm_status = IFM_AVALID;
2458 if (!sc->pdata.phy.link)
2459 return;
2460
2461 ifmr->ifm_active = IFM_ETHER;
2462 ifmr->ifm_status |= IFM_ACTIVE;
2463
2464 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2465 pdata->phy_if.phy_impl.cur_mode(pdata));
2466 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2467
2468 ifmr->ifm_active |= IFM_FDX;
2469 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2470 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2471 }
2472