1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Midhunchandra Kodiyath <midhunchandra.kodiyath@intel.com> 26 * 27 */ 28 29 #ifndef _MEDIA__DRIVER_HW_H 30 #define _MEDIA__DRIVER_HW_H 31 #include "media_drv_util.h" 32 #include <stddef.h> 33 #include <stdbool.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include <i915_drm.h> 40 #include <xf86drm.h> 41 42 #ifdef __cplusplus 43 } 44 #endif 45 46 #include "media_drv_gpe_utils.h" 47 48 #define STATUS_QUERY_END_FLAG 0xFF 49 50 typedef struct generic_kernel_params 51 { 52 UINT idrt_kernel_offset; 53 }GENERIC_KERNEL_PARAMS; 54 55 typedef struct _MEDIA_FRAME_UPDATE 56 { 57 UINT prev_frame_size; 58 BOOL two_prev_frame_flag; 59 UINT16 ref_frame_cost[4]; 60 UINT16 intra_mode_cost[4]; 61 UINT16 inter_mode_cost[4]; 62 UINT16 intra_non_dc_penalty_16x16; 63 UINT16 intra_non_dc_penalty_4x4; 64 BYTE ref_q_index[3]; 65 } MEDIA_FRAME_UPDATE; 66 67 typedef struct _mbenc_constant_buffer_params_vp8 68 { 69 MEDIA_RESOURCE *mb_mode_cost_luma_buffer; 70 MEDIA_RESOURCE *block_mode_cost_buffer; 71 MEDIA_RESOURCE *mode_cost_update_surface; 72 } MBENC_CONSTANT_BUFFER_PARAMS_VP8; 73 74 typedef struct _media_mbpak_curbe_params_vp8 75 { 76 UINT updated; 77 UINT pak_phase_type; 78 VOID *curbe_cmd_buff; 79 } MEDIA_MBPAK_CURBE_PARAMS_VP8; 80 typedef struct _media_mbenc_curbe_params_vp8 81 { 82 UINT kernel_mode; 83 UINT mb_enc_iframe_dist_in_use; 84 UINT updated; 85 UINT hme_enabled; 86 UINT ref_frame_ctrl; 87 UINT brc_enabled; 88 MEDIA_FRAME_UPDATE *frame_update; 89 VOID *curbe_cmd_buff; 90 } MEDIA_MBENC_CURBE_PARAMS_VP8; 91 92 typedef struct _media_brc_init_reset_params_vp8 93 { 94 UINT frame_width; 95 UINT frame_height; 96 UINT avbr_accuracy; 97 UINT avbr_convergence; 98 DOUBLE *brc_init_current_target_buf_full_in_bits; 99 DOUBLE *brc_init_reset_input_bits_per_frame; 100 UINT *brc_init_reset_buf_size_in_bits; 101 BOOL brc_initted; 102 BOOL brc_mb_enabled; 103 UINT frame_rate; 104 UINT rate_control_mode; 105 UINT target_bit_rate; 106 UINT max_bit_rate; 107 UINT min_bit_rate; 108 ULONG init_vbv_buffer_fullness_in_bit; 109 ULONG vbv_buffer_size_in_bit; 110 UINT gop_pic_size; 111 VOID *curbe_cmd_buff; 112 } MEDIA_BRC_INIT_RESET_PARAMS_VP8; 113 114 typedef struct _media_brc_distortion_params_vp8 115 { 116 UINT frame_width_in_mbs; 117 UINT frame_height_in_mbs; 118 UINT avbr_accuracy; 119 UINT avbr_convergence; 120 UINT hme_enabled; 121 UINT brc_initted; 122 UINT kernel_mode; 123 UINT pic_coding_type; 124 UINT frame_number; 125 DOUBLE *brc_init_current_target_buf_full_in_bits; 126 DOUBLE brc_init_reset_input_bits_per_frame; 127 UINT brc_init_reset_buf_size_in_bits; 128 MEDIA_FRAME_UPDATE *frame_update; 129 VOID *curbe_cmd_buff; 130 } MEDIA_BRC_UPDATE_PARAMS_VP8; 131 132 typedef struct _brc_update_constant_data_params_vp8 133 { 134 MEDIA_RESOURCE *brc_update_constant_data; 135 } BRC_UPDATE_CONSTANT_DATA_PARAMS_VP8; 136 137 typedef struct surface_set_params 138 { 139 140 UINT vert_line_stride_offset; 141 UINT vert_line_stride; 142 UINT pitch; 143 UINT tiling; 144 UINT format; 145 UINT offset; 146 UINT size; 147 BOOL surface_is_2d; 148 BOOL surface_is_uv_2d; 149 BOOL surface_is_raw; 150 BOOL media_block_raw; 151 BOOL advance_state; 152 BOOL writable; 153 UINT uv_direction; 154 UINT cacheability_control; 155 unsigned long binding_table_offset; 156 unsigned long surface_state_offset; 157 MEDIA_RESOURCE binding_surface_state; 158 MEDIA_RESOURCE *surface_2d; 159 MEDIA_RESOURCE buf_object; 160 } SURFACE_SET_PARAMS; 161 162 typedef struct mbpak_surface_set_params_vp8 163 { 164 UINT orig_frame_width; 165 UINT orig_frame_height; 166 UINT mbpak_phase_type; 167 BOOL kernel_dump; 168 MEDIA_RESOURCE kernel_dump_buffer; 169 UINT cacheability_control; 170 } MBPAK_SURFACE_PARAMS_VP8; 171 typedef struct mbenc_surface_set_params_vp8 172 { 173 UINT orig_frame_width; 174 UINT orig_frame_height; 175 UINT pic_coding; 176 BOOL kernel_dump; 177 BOOL seg_enabled; 178 BOOL hme_enabled; 179 BOOL iframe_dist_in_use; 180 UINT cacheability_control; 181 } MBENC_SURFACE_PARAMS_VP8; 182 183 typedef struct me_surface_set_params_vp8 184 { 185 BOOL me_16x_in_use; 186 BOOL me_16x_enabled; 187 SURFACE_STATE_BINDING_TABLE *me_surface_state_binding_table; 188 } ME_SURFACE_PARAMS_VP8; 189 typedef struct scaling_surface_set_params 190 { 191 MEDIA_RESOURCE scaling_input_surface; 192 MEDIA_RESOURCE scaling_output_surface; 193 SURFACE_STATE_BINDING_TABLE surface_state_binding_table_scaling; 194 UINT input_width; 195 UINT input_height; 196 UINT output_width; 197 UINT output_height; 198 } SCALING_SURFACE_PARAMS; 199 200 typedef struct brc_init_reset_surface_set_params_vp8 201 { 202 UINT cacheability_control; 203 } BRC_INIT_RESET_SURFACE_PARAMS_VP8; 204 205 typedef struct brc_distortion_surface_set_params_vp8 206 { 207 UINT cacheability_control; 208 } BRC_UPDATE_SURFACE_PARAMS_VP8; 209 210 struct hw_codec_info 211 { 212 INT max_width; 213 INT max_height; 214 UINT tiled_surface:1; 215 UINT vp8_enc_hybrid_support:1; 216 UINT vp9_dec_hybrid_support:1; 217 UINT ratecontrol; 218 bool (*render_init)(VADriverContextP); 219 }; 220 221 typedef struct mi_store_data_imm_params 222 { 223 MEDIA_RESOURCE status_buffer; 224 UINT value; 225 } MI_STORE_DATA_IMM_PARAMS; 226 typedef struct media_object_walker_params 227 { 228 BOOL use_scoreboard; 229 UINT walker_mode; 230 UINT pic_coding_type; 231 UINT direct_spatial_mv_pred; 232 BOOL me_in_use; 233 BOOL mb_enc_iframe_dist_en; 234 BOOL force_26_degree; 235 BOOL hybrid_pak2_pattern_enabled_45_deg; 236 UINT frmfield_h_in_mb; 237 UINT frm_w_in_mb; 238 UINT walker_degree; 239 UINT scoreboard_mask; 240 } MEDIA_OBJ_WALKER_PARAMS; 241 242 typedef struct media_object_params 243 { 244 BOOL use_scoreboard; 245 UINT interface_offset; 246 } MEDIA_OBJECT_PARAMS; 247 248 enum MI_SET_PREDICATE_ENABLE 249 { 250 MI_SET_PREDICATE_ENABLE_ALWAYS = 0x0, 251 MI_SET_PREDICATE_ENABLE_ON_CLEAR = 0x1, 252 MI_SET_PREDICATE_ENABLE_ON_SET = 0x2, 253 MI_SET_PREDICATE_DISABLE = 0x3, 254 }; 255 typedef struct mi_set_predicate_params 256 { 257 UINT predicate_en; 258 } MI_SET_PREDICATE_PARAMS; 259 260 typedef struct media_idt_params 261 { 262 UINT idrt_size; 263 UINT idrt_offset; 264 265 } ID_LOAD_PARAMS; 266 267 typedef struct media_curbe_load_params 268 { 269 UINT curbe_size; 270 UINT curbe_offset; 271 272 } CURBE_LOAD_PARAMS; 273 typedef struct media_vfe_state_params 274 { 275 UINT gpgpu_mode; 276 UINT max_num_threads; 277 UINT num_urb_entries; 278 UINT urb_entry_size; 279 UINT curbe_allocation_size; 280 UINT scoreboard_enable; 281 UINT scoreboard_type; 282 UINT scoreboard_mask; 283 UINT scoreboardDW5; 284 UINT scoreboardDW6; 285 UINT scoreboardDW7; 286 287 } VFE_STATE_PARAMS; 288 289 typedef struct state_base_addr_params 290 { 291 MEDIA_RESOURCE general_state; 292 MEDIA_RESOURCE surface_state; 293 MEDIA_RESOURCE dynamic_state; 294 MEDIA_RESOURCE indirect_object; 295 MEDIA_RESOURCE instruction_buffer; 296 } STATE_BASE_ADDR_PARAMS; 297 298 typedef struct pipe_control_params 299 { 300 MEDIA_RESOURCE status_buffer; 301 UINT flush_mode; 302 UINT immediate_data; 303 } PIPE_CONTROL_PARAMS; 304 305 typedef struct scaling_curbe_params 306 { 307 UINT input_pic_height; 308 UINT input_pic_width; 309 } SCALING_CURBE_PARAMS; 310 311 typedef struct _media_hw_context 312 { 313 UINT vp8_me_mv_data_size_multiplier; 314 } MEDIA_HW_CONTEXT; 315 316 typedef struct _vp8_me_curbe_params 317 { 318 UINT kernel_mode; 319 UINT frame_width; 320 UINT frame_field_height; 321 UINT me_16x_enabled; 322 UINT me_16x; 323 UINT picture_coding_type; 324 VOID *curbe_cmd_buff; 325 } VP8_ME_CURBE_PARAMS; 326 327 VOID 328 media_hw_context_init(VADriverContextP ctx); 329 330 #endif 331