1 /* $OpenBSD: if_bnxreg.h,v 1.51 2024/09/01 03:14:48 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Broadcom Corporation 5 * David Christensen <davidch@broadcom.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written consent. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: src/sys/dev/bce/if_bcereg.h,v 1.4 2006/05/04 00:34:07 mjacob Exp $ 32 */ 33 34 #ifndef _BNX_H_DEFINED 35 #define _BNX_H_DEFINED 36 37 #ifdef _KERNEL 38 #include "bpfilter.h" 39 #include "vlan.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/device.h> 48 #include <sys/socket.h> 49 #include <sys/timeout.h> 50 #include <sys/pool.h> 51 #include <sys/rwlock.h> 52 #include <sys/task.h> 53 #include <sys/atomic.h> 54 55 #include <net/if.h> 56 #include <net/if_media.h> 57 58 #include <netinet/in.h> 59 #include <netinet/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcidevs.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/miidevs.h> 72 #include <dev/mii/brgphyreg.h> 73 74 /****************************************************************************/ 75 /* Debugging macros and definitions. */ 76 /****************************************************************************/ 77 #define BNX_CP_LOAD 0x00000001 78 #define BNX_CP_SEND 0x00000002 79 #define BNX_CP_RECV 0x00000004 80 #define BNX_CP_INTR 0x00000008 81 #define BNX_CP_UNLOAD 0x00000010 82 #define BNX_CP_RESET 0x00000020 83 #define BNX_CP_ALL 0x00FFFFFF 84 85 #define BNX_CP_MASK 0x00FFFFFF 86 87 #define BNX_LEVEL_FATAL 0x00000000 88 #define BNX_LEVEL_WARN 0x01000000 89 #define BNX_LEVEL_INFO 0x02000000 90 #define BNX_LEVEL_VERBOSE 0x03000000 91 #define BNX_LEVEL_EXCESSIVE 0x04000000 92 93 #define BNX_LEVEL_MASK 0xFF000000 94 95 #define BNX_WARN_LOAD (BNX_CP_LOAD | BNX_LEVEL_WARN) 96 #define BNX_INFO_LOAD (BNX_CP_LOAD | BNX_LEVEL_INFO) 97 #define BNX_VERBOSE_LOAD (BNX_CP_LOAD | BNX_LEVEL_VERBOSE) 98 #define BNX_EXCESSIVE_LOAD (BNX_CP_LOAD | BNX_LEVEL_EXCESSIVE) 99 100 #define BNX_WARN_SEND (BNX_CP_SEND | BNX_LEVEL_WARN) 101 #define BNX_INFO_SEND (BNX_CP_SEND | BNX_LEVEL_INFO) 102 #define BNX_VERBOSE_SEND (BNX_CP_SEND | BNX_LEVEL_VERBOSE) 103 #define BNX_EXCESSIVE_SEND (BNX_CP_SEND | BNX_LEVEL_EXCESSIVE) 104 105 #define BNX_WARN_RECV (BNX_CP_RECV | BNX_LEVEL_WARN) 106 #define BNX_INFO_RECV (BNX_CP_RECV | BNX_LEVEL_INFO) 107 #define BNX_VERBOSE_RECV (BNX_CP_RECV | BNX_LEVEL_VERBOSE) 108 #define BNX_EXCESSIVE_RECV (BNX_CP_RECV | BNX_LEVEL_EXCESSIVE) 109 110 #define BNX_WARN_INTR (BNX_CP_INTR | BNX_LEVEL_WARN) 111 #define BNX_INFO_INTR (BNX_CP_INTR | BNX_LEVEL_INFO) 112 #define BNX_VERBOSE_INTR (BNX_CP_INTR | BNX_LEVEL_VERBOSE) 113 #define BNX_EXCESSIVE_INTR (BNX_CP_INTR | BNX_LEVEL_EXCESSIVE) 114 115 #define BNX_WARN_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_WARN) 116 #define BNX_INFO_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_INFO) 117 #define BNX_VERBOSE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_VERBOSE) 118 #define BNX_EXCESSIVE_UNLOAD (BNX_CP_UNLOAD | BNX_LEVEL_EXCESSIVE) 119 120 #define BNX_WARN_RESET (BNX_CP_RESET | BNX_LEVEL_WARN) 121 #define BNX_INFO_RESET (BNX_CP_RESET | BNX_LEVEL_INFO) 122 #define BNX_VERBOSE_RESET (BNX_CP_RESET | BNX_LEVEL_VERBOSE) 123 #define BNX_EXCESSIVE_RESET (BNX_CP_RESET | BNX_LEVEL_EXCESSIVE) 124 125 #define BNX_FATAL (BNX_CP_ALL | BNX_LEVEL_FATAL) 126 #define BNX_WARN (BNX_CP_ALL | BNX_LEVEL_WARN) 127 #define BNX_INFO (BNX_CP_ALL | BNX_LEVEL_INFO) 128 #define BNX_VERBOSE (BNX_CP_ALL | BNX_LEVEL_VERBOSE) 129 #define BNX_EXCESSIVE (BNX_CP_ALL | BNX_LEVEL_EXCESSIVE) 130 131 #define BNX_CODE_PATH(cp) ((cp & BNX_CP_MASK) & bnx_debug) 132 #define BNX_MSG_LEVEL(lv) ((lv & BNX_LEVEL_MASK) <= (bnx_debug & BNX_LEVEL_MASK)) 133 #define BNX_LOG_MSG(m) (BNX_CODE_PATH(m) && BNX_MSG_LEVEL(m)) 134 135 #ifdef BNX_DEBUG 136 137 /* Print a message based on the logging level and code path. */ 138 #define DBPRINT(sc, level, format, args...) \ 139 if (BNX_LOG_MSG(level)) { \ 140 printf("%s: " format, sc->bnx_dev.dv_xname, ## args); \ 141 } 142 143 /* Runs a particular command based on the logging level and code path. */ 144 #define DBRUN(m, args...) \ 145 if (BNX_LOG_MSG(m)) { \ 146 args; \ 147 } 148 149 /* Runs a particular command based on the logging level. */ 150 #define DBRUNLV(level, args...) \ 151 if (BNX_MSG_LEVEL(level)) { \ 152 args; \ 153 } 154 155 /* Runs a particular command based on the code path. */ 156 #define DBRUNCP(cp, args...) \ 157 if (BNX_CODE_PATH(cp)) { \ 158 args; \ 159 } 160 161 /* Runs a particular command based on a condition. */ 162 #define DBRUNIF(cond, args...) \ 163 if (cond) { \ 164 args; \ 165 } 166 #if 0 167 /* Needed for random() function which is only used in debugging. */ 168 #include <sys/random.h> 169 #endif 170 171 /* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */ 172 #define DB_RANDOMFALSE(defects) (random() > defects) 173 #define DB_OR_RANDOMFALSE(defects) || (random() > defects) 174 #define DB_AND_RANDOMFALSE(defects) && (random() > defects) 175 176 /* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */ 177 #define DB_RANDOMTRUE(defects) (random() < defects) 178 #define DB_OR_RANDOMTRUE(defects) || (random() < defects) 179 #define DB_AND_RANDOMTRUE(defects) && (random() < defects) 180 181 #else 182 183 #define DBPRINT(level, format, args...) 184 #define DBRUN(m, args...) 185 #define DBRUNLV(level, args...) 186 #define DBRUNCP(cp, args...) 187 #define DBRUNIF(cond, args...) 188 #define DB_RANDOMFALSE(defects) 189 #define DB_OR_RANDOMFALSE(percent) 190 #define DB_AND_RANDOMFALSE(percent) 191 #define DB_RANDOMTRUE(defects) 192 #define DB_OR_RANDOMTRUE(percent) 193 #define DB_AND_RANDOMTRUE(percent) 194 195 #endif /* BNX_DEBUG */ 196 197 198 /****************************************************************************/ 199 /* Device identification definitions. */ 200 /****************************************************************************/ 201 #define BRCM_VENDORID 0x14E4 202 #define BRCM_DEVICEID_BCM5706 0x164A 203 #define BRCM_DEVICEID_BCM5706S 0x16AA 204 #define BRCM_DEVICEID_BCM5708 0x164C 205 #define BRCM_DEVICEID_BCM5708S 0x16AC 206 207 #define HP_VENDORID 0x103C 208 209 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 210 211 #define BNX_CHIP_NUM(sc) (((sc)->bnx_chipid) & 0xffff0000) 212 #define BNX_CHIP_NUM_5706 0x57060000 213 #define BNX_CHIP_NUM_5708 0x57080000 214 #define BNX_CHIP_NUM_5709 0x57090000 215 #define BNX_CHIP_NUM_5716 0x57160000 216 217 #define BNX_CHIP_REV(sc) (((sc)->bnx_chipid) & 0x0000f000) 218 #define BNX_CHIP_REV_Ax 0x00000000 219 #define BNX_CHIP_REV_Bx 0x00001000 220 #define BNX_CHIP_REV_Cx 0x00002000 221 222 #define BNX_CHIP_METAL(sc) (((sc)->bnx_chipid) & 0x00000ff0) 223 #define BNX_CHIP_BOND(bp) (((sc)->bnx_chipid) & 0x0000000f) 224 225 #define BNX_CHIP_ID(sc) (((sc)->bnx_chipid) & 0xfffffff0) 226 #define BNX_CHIP_ID_5706_A0 0x57060000 227 #define BNX_CHIP_ID_5706_A1 0x57060010 228 #define BNX_CHIP_ID_5706_A2 0x57060020 229 #define BNX_CHIP_ID_5706_A3 0x57060030 230 #define BNX_CHIP_ID_5708_A0 0x57080000 231 #define BNX_CHIP_ID_5708_B0 0x57081000 232 #define BNX_CHIP_ID_5708_B1 0x57081010 233 #define BNX_CHIP_ID_5708_B2 0x57081020 234 #define BNX_CHIP_ID_5709_A0 0x57090000 235 #define BNX_CHIP_ID_5709_A1 0x57090010 236 #define BNX_CHIP_ID_5709_B0 0x57091000 237 #define BNX_CHIP_ID_5709_B1 0x57091010 238 #define BNX_CHIP_ID_5709_B2 0x57091020 239 #define BNX_CHIP_ID_5709_C0 0x57092000 240 #define BNX_CHIP_ID_5716_C0 0x57162000 241 242 #define BNX_CHIP_BOND_ID(sc) (((sc)->bnx_chipid) & 0xf) 243 244 /* A serdes chip will have the first bit of the bond id set. */ 245 #define BNX_CHIP_BOND_ID_SERDES_BIT 0x01 246 247 248 /* shorthand one */ 249 #define BNX_ASICREV(x) ((x) >> 28) 250 #define BNX_ASICREV_BCM5700 0x06 251 252 /* chip revisions */ 253 #define BNX_CHIPREV(x) ((x) >> 24) 254 #define BNX_CHIPREV_5700_AX 0x70 255 #define BNX_CHIPREV_5700_BX 0x71 256 #define BNX_CHIPREV_5700_CX 0x72 257 #define BNX_CHIPREV_5701_AX 0x00 258 259 struct bnx_type { 260 u_int16_t bnx_vid; 261 u_int16_t bnx_did; 262 u_int16_t bnx_svid; 263 u_int16_t bnx_sdid; 264 char *bnx_name; 265 }; 266 267 /****************************************************************************/ 268 /* Byte order conversions. */ 269 /****************************************************************************/ 270 #define bnx_htobe16(x) htobe16(x) 271 #define bnx_htobe32(x) htobe32(x) 272 #define bnx_htobe64(x) htobe64(x) 273 #define bnx_htole16(x) htole16(x) 274 #define bnx_htole32(x) htole32(x) 275 #define bnx_htole64(x) htole64(x) 276 277 #define bnx_be16toh(x) betoh16(x) 278 #define bnx_be32toh(x) betoh32(x) 279 #define bnx_be64toh(x) betoh64(x) 280 #define bnx_le16toh(x) letoh16(x) 281 #define bnx_le32toh(x) letoh32(x) 282 #define bnx_le64toh(x) letoh64(x) 283 284 285 /****************************************************************************/ 286 /* NVRAM Access */ 287 /****************************************************************************/ 288 289 /* Buffered flash (Atmel: AT45DB011B) specific information */ 290 #define SEEPROM_PAGE_BITS 2 291 #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) 292 #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) 293 #define SEEPROM_PAGE_SIZE 4 294 #define SEEPROM_TOTAL_SIZE 65536 295 296 #define BUFFERED_FLASH_PAGE_BITS 9 297 #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) 298 #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) 299 #define BUFFERED_FLASH_PAGE_SIZE 264 300 #define BUFFERED_FLASH_TOTAL_SIZE 0x21000 301 302 #define SAIFUN_FLASH_PAGE_BITS 8 303 #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) 304 #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) 305 #define SAIFUN_FLASH_PAGE_SIZE 256 306 #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536 307 308 #define ST_MICRO_FLASH_PAGE_BITS 8 309 #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) 310 #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) 311 #define ST_MICRO_FLASH_PAGE_SIZE 256 312 #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 313 314 #define BCM5709_FLASH_PAGE_BITS 8 315 #define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS) 316 #define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1) 317 #define BCM5709_FLASH_PAGE_SIZE 256 318 319 #define NVRAM_TIMEOUT_COUNT 30000 320 #define BNX_FLASHDESC_MAX 64 321 322 #define FLASH_STRAP_MASK (BNX_NVM_CFG1_FLASH_MODE | \ 323 BNX_NVM_CFG1_BUFFER_MODE | \ 324 BNX_NVM_CFG1_PROTECT_MODE | \ 325 BNX_NVM_CFG1_FLASH_SIZE) 326 327 #define FLASH_BACKUP_STRAP_MASK (0xf << 26) 328 329 struct flash_spec { 330 u_int32_t strapping; 331 u_int32_t config1; 332 u_int32_t config2; 333 u_int32_t config3; 334 u_int32_t write1; 335 #define BNX_NV_BUFFERED 0x00000001 336 #define BNX_NV_TRANSLATE 0x00000002 337 #define BNX_NV_WREN 0x00000004 338 u_int32_t flags; 339 u_int32_t page_bits; 340 u_int32_t page_size; 341 u_int32_t addr_mask; 342 u_int32_t total_size; 343 u_int8_t *name; 344 }; 345 346 347 /****************************************************************************/ 348 /* Shared Memory layout */ 349 /* The BNX bootcode will initialize this data area with port configuration */ 350 /* information which can be accessed by the driver. */ 351 /****************************************************************************/ 352 353 /* 354 * This value (in milliseconds) determines the frequency of the driver 355 * issuing the PULSE message code. The firmware monitors this periodic 356 * pulse to determine when to switch to an OS-absent mode. 357 */ 358 #define DRV_PULSE_PERIOD_MS 250 359 360 /* 361 * This value (in milliseconds) determines how long the driver should 362 * wait for an acknowledgement from the firmware before timing out. Once 363 * the firmware has timed out, the driver will assume there is no firmware 364 * running and there won't be any firmware-driver synchronization during a 365 * driver reset. 366 */ 367 #define FW_ACK_TIME_OUT_MS 1000 368 369 370 #define BNX_DRV_RESET_SIGNATURE 0x00000000 371 #define BNX_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */ 372 373 #define BNX_DRV_MB 0x00000004 374 #define BNX_DRV_MSG_CODE 0xff000000 375 #define BNX_DRV_MSG_CODE_RESET 0x01000000 376 #define BNX_DRV_MSG_CODE_UNLOAD 0x02000000 377 #define BNX_DRV_MSG_CODE_SHUTDOWN 0x03000000 378 #define BNX_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 379 #define BNX_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 380 #define BNX_DRV_MSG_CODE_PULSE 0x06000000 381 #define BNX_DRV_MSG_CODE_DIAG 0x07000000 382 #define BNX_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000 383 384 #define BNX_DRV_MSG_DATA 0x00ff0000 385 #define BNX_DRV_MSG_DATA_WAIT0 0x00010000 386 #define BNX_DRV_MSG_DATA_WAIT1 0x00020000 387 #define BNX_DRV_MSG_DATA_WAIT2 0x00030000 388 #define BNX_DRV_MSG_DATA_WAIT3 0x00040000 389 390 #define BNX_DRV_MSG_SEQ 0x0000ffff 391 392 #define BNX_FW_MB 0x00000008 393 #define BNX_FW_MSG_ACK 0x0000ffff 394 #define BNX_FW_MSG_STATUS_MASK 0x00ff0000 395 #define BNX_FW_MSG_STATUS_OK 0x00000000 396 #define BNX_FW_MSG_STATUS_FAILURE 0x00ff0000 397 398 #define BNX_LINK_STATUS 0x0000000c 399 #define BNX_LINK_STATUS_INIT_VALUE 0xffffffff 400 #define BNX_LINK_STATUS_LINK_UP 0x1 401 #define BNX_LINK_STATUS_LINK_DOWN 0x0 402 #define BNX_LINK_STATUS_SPEED_MASK 0x1e 403 #define BNX_LINK_STATUS_AN_INCOMPLETE (0<<1) 404 #define BNX_LINK_STATUS_10HALF (1<<1) 405 #define BNX_LINK_STATUS_10FULL (2<<1) 406 #define BNX_LINK_STATUS_100HALF (3<<1) 407 #define BNX_LINK_STATUS_100BASE_T4 (4<<1) 408 #define BNX_LINK_STATUS_100FULL (5<<1) 409 #define BNX_LINK_STATUS_1000HALF (6<<1) 410 #define BNX_LINK_STATUS_1000FULL (7<<1) 411 #define BNX_LINK_STATUS_2500HALF (8<<1) 412 #define BNX_LINK_STATUS_2500FULL (9<<1) 413 #define BNX_LINK_STATUS_AN_ENABLED (1<<5) 414 #define BNX_LINK_STATUS_AN_COMPLETE (1<<6) 415 #define BNX_LINK_STATUS_PARALLEL_DET (1<<7) 416 #define BNX_LINK_STATUS_RESERVED (1<<8) 417 #define BNX_LINK_STATUS_PARTNER_AD_1000FULL (1<<9) 418 #define BNX_LINK_STATUS_PARTNER_AD_1000HALF (1<<10) 419 #define BNX_LINK_STATUS_PARTNER_AD_100BT4 (1<<11) 420 #define BNX_LINK_STATUS_PARTNER_AD_100FULL (1<<12) 421 #define BNX_LINK_STATUS_PARTNER_AD_100HALF (1<<13) 422 #define BNX_LINK_STATUS_PARTNER_AD_10FULL (1<<14) 423 #define BNX_LINK_STATUS_PARTNER_AD_10HALF (1<<15) 424 #define BNX_LINK_STATUS_TX_FC_ENABLED (1<<16) 425 #define BNX_LINK_STATUS_RX_FC_ENABLED (1<<17) 426 #define BNX_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18) 427 #define BNX_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19) 428 #define BNX_LINK_STATUS_SERDES_LINK (1<<20) 429 #define BNX_LINK_STATUS_PARTNER_AD_2500FULL (1<<21) 430 #define BNX_LINK_STATUS_PARTNER_AD_2500HALF (1<<22) 431 432 #define BNX_DRV_PULSE_MB 0x00000010 433 #define BNX_DRV_PULSE_SEQ_MASK 0x00007fff 434 435 #define BNX_MB_ARGS_0 0x00000014 436 #define BNX_MB_ARGS_1 0x00000018 437 438 /* Indicate to the firmware not to go into the 439 * OS absent when it is not getting driver pulse. 440 * This is used for debugging. */ 441 #define BNX_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000 442 443 #define BNX_DEV_INFO_SIGNATURE 0x00000020 444 #define BNX_DEV_INFO_SIGNATURE_MAGIC 0x44564900 445 #define BNX_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00 446 #define BNX_DEV_INFO_FEATURE_CFG_VALID 0x01 447 #define BNX_DEV_INFO_SECONDARY_PORT 0x80 448 #define BNX_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 449 450 #define BNX_SHARED_HW_CFG_PART_NUM 0x00000024 451 452 #define BNX_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034 453 #define BNX_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000 454 #define BNX_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000 455 #define BNX_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00 456 #define BNX_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff 457 458 #define BNX_SHARED_HW_CFG_POWER_CONSUMED 0x00000038 459 #define BNX_SHARED_HW_CFG_CONFIG 0x0000003c 460 #define BNX_SHARED_HW_CFG_DESIGN_NIC 0 461 #define BNX_SHARED_HW_CFG_DESIGN_LOM 0x1 462 #define BNX_SHARED_HW_CFG_PHY_COPPER 0 463 #define BNX_SHARED_HW_CFG_PHY_FIBER 0x2 464 #define BNX_SHARED_HW_CFG_PHY_2_5G 0x20 465 #define BNX_SHARED_HW_CFG_PHY_BACKPLANE 0x40 466 #define BNX_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8 467 #define BNX_SHARED_HW_CFG_LED_MODE_MASK 0x300 468 #define BNX_SHARED_HW_CFG_LED_MODE_MAC 0 469 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY1 0x100 470 #define BNX_SHARED_HW_CFG_LED_MODE_GPHY2 0x200 471 472 #define BNX_SHARED_HW_CFG_CONFIG2 0x00000040 473 #define BNX_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000 474 475 #define BNX_DEV_INFO_BC_REV 0x0000004c 476 477 #define BNX_PORT_HW_CFG_MAC_UPPER 0x00000050 478 #define BNX_PORT_HW_CFG_UPPERMAC_MASK 0xffff 479 480 #define BNX_PORT_HW_CFG_MAC_LOWER 0x00000054 481 #define BNX_PORT_HW_CFG_CONFIG 0x00000058 482 #define BNX_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff 483 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000 484 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000 485 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000 486 #define BNX_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000 487 488 #define BNX_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068 489 #define BNX_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c 490 #define BNX_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070 491 #define BNX_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074 492 #define BNX_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078 493 #define BNX_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c 494 495 #define BNX_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4 496 497 #define BNX_DEV_INFO_FORMAT_REV 0x000000c4 498 #define BNX_DEV_INFO_FORMAT_REV_MASK 0xff000000 499 #define BNX_DEV_INFO_FORMAT_REV_ID ('A' << 24) 500 501 #define BNX_SHARED_FEATURE 0x000000c8 502 #define BNX_SHARED_FEATURE_MASK 0xffffffff 503 504 #define BNX_PORT_FEATURE 0x000000d8 505 #define BNX_PORT2_FEATURE 0x00000014c 506 #define BNX_PORT_FEATURE_WOL_ENABLED 0x01000000 507 #define BNX_PORT_FEATURE_MBA_ENABLED 0x02000000 508 #define BNX_PORT_FEATURE_ASF_ENABLED 0x04000000 509 #define BNX_PORT_FEATURE_IMD_ENABLED 0x08000000 510 #define BNX_PORT_FEATURE_BAR1_SIZE_MASK 0xf 511 #define BNX_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0 512 #define BNX_PORT_FEATURE_BAR1_SIZE_64K 0x1 513 #define BNX_PORT_FEATURE_BAR1_SIZE_128K 0x2 514 #define BNX_PORT_FEATURE_BAR1_SIZE_256K 0x3 515 #define BNX_PORT_FEATURE_BAR1_SIZE_512K 0x4 516 #define BNX_PORT_FEATURE_BAR1_SIZE_1M 0x5 517 #define BNX_PORT_FEATURE_BAR1_SIZE_2M 0x6 518 #define BNX_PORT_FEATURE_BAR1_SIZE_4M 0x7 519 #define BNX_PORT_FEATURE_BAR1_SIZE_8M 0x8 520 #define BNX_PORT_FEATURE_BAR1_SIZE_16M 0x9 521 #define BNX_PORT_FEATURE_BAR1_SIZE_32M 0xa 522 #define BNX_PORT_FEATURE_BAR1_SIZE_64M 0xb 523 #define BNX_PORT_FEATURE_BAR1_SIZE_128M 0xc 524 #define BNX_PORT_FEATURE_BAR1_SIZE_256M 0xd 525 #define BNX_PORT_FEATURE_BAR1_SIZE_512M 0xe 526 #define BNX_PORT_FEATURE_BAR1_SIZE_1G 0xf 527 528 #define BNX_PORT_FEATURE_WOL 0xdc 529 #define BNX_PORT2_FEATURE_WOL 0x150 530 #define BNX_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4 531 #define BNX_PORT_FEATURE_WOL_DEFAULT_MASK 0x30 532 #define BNX_PORT_FEATURE_WOL_DEFAULT_DISABLE 0 533 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10 534 #define BNX_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20 535 #define BNX_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30 536 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf 537 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0 538 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1 539 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2 540 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3 541 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4 542 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5 543 #define BNX_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6 544 #define BNX_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40 545 #define BNX_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400 546 #define BNX_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800 547 548 #define BNX_PORT_FEATURE_MBA 0xe0 549 #define BNX_PORT2_FEATURE_MBA 0x154 550 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0 551 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3 552 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0 553 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1 554 #define BNX_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2 555 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2 556 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c 557 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0 558 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4 559 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8 560 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc 561 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10 562 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14 563 #define BNX_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18 564 #define BNX_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40 565 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0 566 #define BNX_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80 567 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8 568 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00 569 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0 570 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100 571 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200 572 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300 573 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400 574 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500 575 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600 576 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700 577 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800 578 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900 579 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00 580 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00 581 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00 582 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00 583 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00 584 #define BNX_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00 585 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16 586 #define BNX_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000 587 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20 588 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000 589 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0 590 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000 591 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000 592 #define BNX_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000 593 594 #define BNX_PORT_FEATURE_IMD 0xe4 595 #define BNX_PORT2_FEATURE_IMD 0x158 596 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0 597 #define BNX_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1 598 599 #define BNX_PORT_FEATURE_VLAN 0xe8 600 #define BNX_PORT2_FEATURE_VLAN 0x15c 601 #define BNX_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff 602 #define BNX_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000 603 604 #define BNX_BC_STATE_RESET_TYPE 0x000001c0 605 #define BNX_BC_STATE_RESET_TYPE_SIG 0x00005254 606 #define BNX_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff 607 #define BNX_BC_STATE_RESET_TYPE_NONE (BNX_BC_STATE_RESET_TYPE_SIG | \ 608 0x00010000) 609 #define BNX_BC_STATE_RESET_TYPE_PCI (BNX_BC_STATE_RESET_TYPE_SIG | \ 610 0x00020000) 611 #define BNX_BC_STATE_RESET_TYPE_VAUX (BNX_BC_STATE_RESET_TYPE_SIG | \ 612 0x00030000) 613 #define BNX_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE 614 #define BNX_BC_STATE_RESET_TYPE_DRV_RESET (BNX_BC_STATE_RESET_TYPE_SIG | \ 615 DRV_MSG_CODE_RESET) 616 #define BNX_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX_BC_STATE_RESET_TYPE_SIG | \ 617 DRV_MSG_CODE_UNLOAD) 618 #define BNX_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX_BC_STATE_RESET_TYPE_SIG | \ 619 DRV_MSG_CODE_SHUTDOWN) 620 #define BNX_BC_STATE_RESET_TYPE_DRV_WOL (BNX_BC_STATE_RESET_TYPE_SIG | \ 621 DRV_MSG_CODE_WOL) 622 #define BNX_BC_STATE_RESET_TYPE_DRV_DIAG (BNX_BC_STATE_RESET_TYPE_SIG | \ 623 DRV_MSG_CODE_DIAG) 624 #define BNX_BC_STATE_RESET_TYPE_VALUE(msg) (BNX_BC_STATE_RESET_TYPE_SIG | \ 625 (msg)) 626 627 #define BNX_BC_STATE 0x000001c4 628 #define BNX_BC_STATE_ERR_MASK 0x0000ff00 629 #define BNX_BC_STATE_SIGN 0x42530000 630 #define BNX_BC_STATE_SIGN_MASK 0xffff0000 631 #define BNX_BC_STATE_BC1_START (BNX_BC_STATE_SIGN | 0x1) 632 #define BNX_BC_STATE_GET_NVM_CFG1 (BNX_BC_STATE_SIGN | 0x2) 633 #define BNX_BC_STATE_PROG_BAR (BNX_BC_STATE_SIGN | 0x3) 634 #define BNX_BC_STATE_INIT_VID (BNX_BC_STATE_SIGN | 0x4) 635 #define BNX_BC_STATE_GET_NVM_CFG2 (BNX_BC_STATE_SIGN | 0x5) 636 #define BNX_BC_STATE_APPLY_WKARND (BNX_BC_STATE_SIGN | 0x6) 637 #define BNX_BC_STATE_LOAD_BC2 (BNX_BC_STATE_SIGN | 0x7) 638 #define BNX_BC_STATE_GOING_BC2 (BNX_BC_STATE_SIGN | 0x8) 639 #define BNX_BC_STATE_GOING_DIAG (BNX_BC_STATE_SIGN | 0x9) 640 #define BNX_BC_STATE_RT_FINAL_INIT (BNX_BC_STATE_SIGN | 0x81) 641 #define BNX_BC_STATE_RT_WKARND (BNX_BC_STATE_SIGN | 0x82) 642 #define BNX_BC_STATE_RT_DRV_PULSE (BNX_BC_STATE_SIGN | 0x83) 643 #define BNX_BC_STATE_RT_FIOEVTS (BNX_BC_STATE_SIGN | 0x84) 644 #define BNX_BC_STATE_RT_DRV_CMD (BNX_BC_STATE_SIGN | 0x85) 645 #define BNX_BC_STATE_RT_LOW_POWER (BNX_BC_STATE_SIGN | 0x86) 646 #define BNX_BC_STATE_RT_SET_WOL (BNX_BC_STATE_SIGN | 0x87) 647 #define BNX_BC_STATE_RT_OTHER_FW (BNX_BC_STATE_SIGN | 0x88) 648 #define BNX_BC_STATE_RT_GOING_D3 (BNX_BC_STATE_SIGN | 0x89) 649 #define BNX_BC_STATE_ERR_BAD_VERSION (BNX_BC_STATE_SIGN | 0x0100) 650 #define BNX_BC_STATE_ERR_BAD_BC2_CRC (BNX_BC_STATE_SIGN | 0x0200) 651 #define BNX_BC_STATE_ERR_BC1_LOOP (BNX_BC_STATE_SIGN | 0x0300) 652 #define BNX_BC_STATE_ERR_UNKNOWN_CMD (BNX_BC_STATE_SIGN | 0x0400) 653 #define BNX_BC_STATE_ERR_DRV_DEAD (BNX_BC_STATE_SIGN | 0x0500) 654 #define BNX_BC_STATE_ERR_NO_RXP (BNX_BC_STATE_SIGN | 0x0600) 655 #define BNX_BC_STATE_ERR_TOO_MANY_RBUF (BNX_BC_STATE_SIGN | 0x0700) 656 657 #define BNX_BC_STATE_DEBUG_CMD 0x1dc 658 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000 659 #define BNX_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000 660 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff 661 #define BNX_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff 662 663 #define HOST_VIEW_SHMEM_BASE 0x167c00 664 665 /* 666 * PCI registers defined in the PCI 2.2 spec. 667 */ 668 #define BNX_PCI_BAR0 0x10 669 #define BNX_PCI_PCIX_CMD 0x40 670 671 /****************************************************************************/ 672 /* Convenience definitions. */ 673 /****************************************************************************/ 674 #define BNX_PRINTF(sc, fmt, args...) printf("%s: " fmt, sc->bnx_dev.dv_xname, ##args) 675 676 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 677 #define REG_WR16(sc, reg, val) bus_space_write_2(sc->bnx_btag, sc->bnx_bhandle, reg, val) 678 #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 679 #define REG_RD_IND(sc, offset) bnx_reg_rd_ind(sc, offset) 680 #define REG_WR_IND(sc, offset, val) bnx_reg_wr_ind(sc, offset, val) 681 #define CTX_WR(sc, cid_addr, offset, val) bnx_ctx_wr(sc, cid_addr, offset, val) 682 #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 683 #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x))) 684 #define PCI_SETBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) | (x))) 685 #define PCI_CLRBIT(pc, tag, reg, x) pci_conf_write(pc, tag, reg, (pci_conf_read(pc, tag, reg) & ~(x))) 686 687 #define BNX_STATS(x) (u_long) stats->stat_ ## x ## _lo 688 689 /* 690 * The following data structures are generated from RTL code. 691 * Do not modify any values below this line. 692 */ 693 694 /****************************************************************************/ 695 /* Do not modify any of the following data structures, they are generated */ 696 /* from RTL code. */ 697 /* */ 698 /* Begin machine generated definitions. */ 699 /****************************************************************************/ 700 701 /* 702 * tx_bd definition 703 */ 704 struct tx_bd { 705 u_int32_t tx_bd_haddr_hi; 706 u_int32_t tx_bd_haddr_lo; 707 u_int32_t tx_bd_mss_nbytes; 708 #if BYTE_ORDER == BIG_ENDIAN 709 u_int16_t tx_bd_vlan_tag; 710 u_int16_t tx_bd_flags; 711 #else 712 u_int16_t tx_bd_flags; 713 u_int16_t tx_bd_vlan_tag; 714 #endif 715 #define TX_BD_FLAGS_CONN_FAULT (1<<0) 716 #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1) 717 #define TX_BD_FLAGS_IP_CKSUM (1<<2) 718 #define TX_BD_FLAGS_VLAN_TAG (1<<3) 719 #define TX_BD_FLAGS_COAL_NOW (1<<4) 720 #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5) 721 #define TX_BD_FLAGS_END (1<<6) 722 #define TX_BD_FLAGS_START (1<<7) 723 #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8) 724 #define TX_BD_FLAGS_SW_FLAGS (1<<13) 725 #define TX_BD_FLAGS_SW_SNAP (1<<14) 726 #define TX_BD_FLAGS_SW_LSO (1<<15) 727 728 }; 729 730 731 /* 732 * rx_bd definition 733 */ 734 struct rx_bd { 735 u_int32_t rx_bd_haddr_hi; 736 u_int32_t rx_bd_haddr_lo; 737 u_int32_t rx_bd_len; 738 u_int32_t rx_bd_flags; 739 #define RX_BD_FLAGS_NOPUSH (1<<0) 740 #define RX_BD_FLAGS_DUMMY (1<<1) 741 #define RX_BD_FLAGS_END (1<<2) 742 #define RX_BD_FLAGS_START (1<<3) 743 744 }; 745 746 747 /* 748 * status_block definition 749 */ 750 struct status_block { 751 u_int32_t status_attn_bits; 752 #define STATUS_ATTN_BITS_LINK_STATE (1L<<0) 753 #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1) 754 #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2) 755 #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3) 756 #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4) 757 #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5) 758 #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6) 759 #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7) 760 #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8) 761 #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9) 762 #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10) 763 #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11) 764 #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12) 765 #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13) 766 #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14) 767 #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15) 768 #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16) 769 #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17) 770 #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18) 771 #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19) 772 #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20) 773 #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21) 774 #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22) 775 #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23) 776 #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24) 777 #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25) 778 #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26) 779 #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27) 780 #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31) 781 782 u_int32_t status_attn_bits_ack; 783 #if BYTE_ORDER == BIG_ENDIAN 784 u_int16_t status_tx_quick_consumer_index0; 785 u_int16_t status_tx_quick_consumer_index1; 786 u_int16_t status_tx_quick_consumer_index2; 787 u_int16_t status_tx_quick_consumer_index3; 788 u_int16_t status_rx_quick_consumer_index0; 789 u_int16_t status_rx_quick_consumer_index1; 790 u_int16_t status_rx_quick_consumer_index2; 791 u_int16_t status_rx_quick_consumer_index3; 792 u_int16_t status_rx_quick_consumer_index4; 793 u_int16_t status_rx_quick_consumer_index5; 794 u_int16_t status_rx_quick_consumer_index6; 795 u_int16_t status_rx_quick_consumer_index7; 796 u_int16_t status_rx_quick_consumer_index8; 797 u_int16_t status_rx_quick_consumer_index9; 798 u_int16_t status_rx_quick_consumer_index10; 799 u_int16_t status_rx_quick_consumer_index11; 800 u_int16_t status_rx_quick_consumer_index12; 801 u_int16_t status_rx_quick_consumer_index13; 802 u_int16_t status_rx_quick_consumer_index14; 803 u_int16_t status_rx_quick_consumer_index15; 804 u_int16_t status_completion_producer_index; 805 u_int16_t status_cmd_consumer_index; 806 u_int16_t status_idx; 807 u_int16_t status_unused; 808 #elif BYTE_ORDER == LITTLE_ENDIAN 809 u_int16_t status_tx_quick_consumer_index1; 810 u_int16_t status_tx_quick_consumer_index0; 811 u_int16_t status_tx_quick_consumer_index3; 812 u_int16_t status_tx_quick_consumer_index2; 813 u_int16_t status_rx_quick_consumer_index1; 814 u_int16_t status_rx_quick_consumer_index0; 815 u_int16_t status_rx_quick_consumer_index3; 816 u_int16_t status_rx_quick_consumer_index2; 817 u_int16_t status_rx_quick_consumer_index5; 818 u_int16_t status_rx_quick_consumer_index4; 819 u_int16_t status_rx_quick_consumer_index7; 820 u_int16_t status_rx_quick_consumer_index6; 821 u_int16_t status_rx_quick_consumer_index9; 822 u_int16_t status_rx_quick_consumer_index8; 823 u_int16_t status_rx_quick_consumer_index11; 824 u_int16_t status_rx_quick_consumer_index10; 825 u_int16_t status_rx_quick_consumer_index13; 826 u_int16_t status_rx_quick_consumer_index12; 827 u_int16_t status_rx_quick_consumer_index15; 828 u_int16_t status_rx_quick_consumer_index14; 829 u_int16_t status_cmd_consumer_index; 830 u_int16_t status_completion_producer_index; 831 u_int16_t status_unused; 832 u_int16_t status_idx; 833 #endif 834 }; 835 836 837 /* 838 * statistics_block definition 839 */ 840 struct statistics_block { 841 u_int32_t stat_IfHCInOctets_hi; 842 u_int32_t stat_IfHCInOctets_lo; 843 u_int32_t stat_IfHCInBadOctets_hi; 844 u_int32_t stat_IfHCInBadOctets_lo; 845 u_int32_t stat_IfHCOutOctets_hi; 846 u_int32_t stat_IfHCOutOctets_lo; 847 u_int32_t stat_IfHCOutBadOctets_hi; 848 u_int32_t stat_IfHCOutBadOctets_lo; 849 u_int32_t stat_IfHCInUcastPkts_hi; 850 u_int32_t stat_IfHCInUcastPkts_lo; 851 u_int32_t stat_IfHCInMulticastPkts_hi; 852 u_int32_t stat_IfHCInMulticastPkts_lo; 853 u_int32_t stat_IfHCInBroadcastPkts_hi; 854 u_int32_t stat_IfHCInBroadcastPkts_lo; 855 u_int32_t stat_IfHCOutUcastPkts_hi; 856 u_int32_t stat_IfHCOutUcastPkts_lo; 857 u_int32_t stat_IfHCOutMulticastPkts_hi; 858 u_int32_t stat_IfHCOutMulticastPkts_lo; 859 u_int32_t stat_IfHCOutBroadcastPkts_hi; 860 u_int32_t stat_IfHCOutBroadcastPkts_lo; 861 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 862 u_int32_t stat_Dot3StatsCarrierSenseErrors; 863 u_int32_t stat_Dot3StatsFCSErrors; 864 u_int32_t stat_Dot3StatsAlignmentErrors; 865 u_int32_t stat_Dot3StatsSingleCollisionFrames; 866 u_int32_t stat_Dot3StatsMultipleCollisionFrames; 867 u_int32_t stat_Dot3StatsDeferredTransmissions; 868 u_int32_t stat_Dot3StatsExcessiveCollisions; 869 u_int32_t stat_Dot3StatsLateCollisions; 870 u_int32_t stat_EtherStatsCollisions; 871 u_int32_t stat_EtherStatsFragments; 872 u_int32_t stat_EtherStatsJabbers; 873 u_int32_t stat_EtherStatsUndersizePkts; 874 u_int32_t stat_EtherStatsOverrsizePkts; 875 u_int32_t stat_EtherStatsPktsRx64Octets; 876 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; 877 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; 878 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; 879 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 880 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 881 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 882 u_int32_t stat_EtherStatsPktsTx64Octets; 883 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; 884 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; 885 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; 886 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 887 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 888 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 889 u_int32_t stat_XonPauseFramesReceived; 890 u_int32_t stat_XoffPauseFramesReceived; 891 u_int32_t stat_OutXonSent; 892 u_int32_t stat_OutXoffSent; 893 u_int32_t stat_FlowControlDone; 894 u_int32_t stat_MacControlFramesReceived; 895 u_int32_t stat_XoffStateEntered; 896 u_int32_t stat_IfInFramesL2FilterDiscards; 897 u_int32_t stat_IfInRuleCheckerDiscards; 898 u_int32_t stat_IfInFTQDiscards; 899 u_int32_t stat_IfInMBUFDiscards; 900 u_int32_t stat_IfInRuleCheckerP4Hit; 901 u_int32_t stat_CatchupInRuleCheckerDiscards; 902 u_int32_t stat_CatchupInFTQDiscards; 903 u_int32_t stat_CatchupInMBUFDiscards; 904 u_int32_t stat_CatchupInRuleCheckerP4Hit; 905 u_int32_t stat_GenStat00; 906 u_int32_t stat_GenStat01; 907 u_int32_t stat_GenStat02; 908 u_int32_t stat_GenStat03; 909 u_int32_t stat_GenStat04; 910 u_int32_t stat_GenStat05; 911 u_int32_t stat_GenStat06; 912 u_int32_t stat_GenStat07; 913 u_int32_t stat_GenStat08; 914 u_int32_t stat_GenStat09; 915 u_int32_t stat_GenStat10; 916 u_int32_t stat_GenStat11; 917 u_int32_t stat_GenStat12; 918 u_int32_t stat_GenStat13; 919 u_int32_t stat_GenStat14; 920 u_int32_t stat_GenStat15; 921 }; 922 923 924 /* 925 * l2_fhdr definition 926 */ 927 struct l2_fhdr { 928 u_int32_t l2_fhdr_status; 929 #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0) 930 #define L2_FHDR_STATUS_RULE_P2 (1<<3) 931 #define L2_FHDR_STATUS_RULE_P3 (1<<4) 932 #define L2_FHDR_STATUS_RULE_P4 (1<<5) 933 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6) 934 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7) 935 #define L2_FHDR_STATUS_RSS_HASH (1<<8) 936 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13) 937 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14) 938 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15) 939 940 #define L2_FHDR_ERRORS_BAD_CRC (1<<17) 941 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18) 942 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19) 943 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20) 944 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21) 945 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28) 946 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31) 947 948 u_int32_t l2_fhdr_hash; 949 #if BYTE_ORDER == BIG_ENDIAN 950 u_int16_t l2_fhdr_pkt_len; 951 u_int16_t l2_fhdr_vlan_tag; 952 u_int16_t l2_fhdr_ip_xsum; 953 u_int16_t l2_fhdr_tcp_udp_xsum; 954 #elif BYTE_ORDER == LITTLE_ENDIAN 955 u_int16_t l2_fhdr_vlan_tag; 956 u_int16_t l2_fhdr_pkt_len; 957 u_int16_t l2_fhdr_tcp_udp_xsum; 958 u_int16_t l2_fhdr_ip_xsum; 959 #endif 960 }; 961 962 963 /* 964 * l2_context definition 965 */ 966 #define BNX_L2CTX_TYPE 0x00000000 967 #define BNX_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) 968 #define BNX_L2CTX_TYPE_TYPE (0xf<<28) 969 #define BNX_L2CTX_TYPE_TYPE_EMPTY (0<<28) 970 #define BNX_L2CTX_TYPE_TYPE_L2 (1<<28) 971 972 #define BNX_L2CTX_TYPE_XI 0x00000080 973 #define BNX_L2CTX_TX_HOST_BIDX 0x00000088 974 #define BNX_L2CTX_EST_NBD 0x00000088 975 #define BNX_L2CTX_CMD_TYPE 0x00000088 976 #define BNX_L2CTX_CMD_TYPE_TYPE (0xf<<24) 977 #define BNX_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) 978 #define BNX_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) 979 980 #define BNX_L2CTX_TX_HOST_BSEQ 0x00000090 981 #define BNX_L2CTX_TSCH_BSEQ 0x00000094 982 #define BNX_L2CTX_TBDR_BSEQ 0x00000098 983 #define BNX_L2CTX_TBDR_BOFF 0x0000009c 984 #define BNX_L2CTX_TBDR_BIDX 0x0000009c 985 #define BNX_L2CTX_TBDR_BHADDR_HI 0x000000a0 986 #define BNX_L2CTX_TBDR_BHADDR_LO 0x000000a4 987 #define BNX_L2CTX_TXP_BOFF 0x000000a8 988 #define BNX_L2CTX_TXP_BIDX 0x000000a8 989 #define BNX_L2CTX_TXP_BSEQ 0x000000ac 990 991 #define BNX_L2CTX_CMD_TYPE_XI 0x00000240 992 #define BNX_L2CTX_TBDR_BHADDR_HI_XI 0x00000258 993 #define BNX_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c 994 995 /* 996 * l2_bd_chain_context definition 997 */ 998 #define BNX_L2CTX_BD_PRE_READ 0x00000000 999 #define BNX_L2CTX_CTX_SIZE 0x00000000 1000 #define BNX_L2CTX_CTX_TYPE 0x00000000 1001 #define BNX_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) 1002 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1003 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1004 #define BNX_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1005 1006 #define BNX_L2CTX_HOST_BDIDX 0x00000004 1007 #define BNX_L2CTX_HOST_BSEQ 0x00000008 1008 #define BNX_L2CTX_NX_BSEQ 0x0000000c 1009 #define BNX_L2CTX_NX_BDHADDR_HI 0x00000010 1010 #define BNX_L2CTX_NX_BDHADDR_LO 0x00000014 1011 #define BNX_L2CTX_NX_BDIDX 0x00000018 1012 1013 /* 1014 * l2_rx_context definition (5706, 5708, 5709, and 5716) 1015 */ 1016 #define BNX_L2CTX_RX_WATER_MARK 0x00000000 1017 #define BNX_L2CTX_RX_LO_WATER_MARK_SHIFT 0 1018 #define BNX_L2CTX_RX_LO_WATER_MARK_DEFAULT 32 1019 #define BNX_L2CTX_RX_LO_WATER_MARK_SCALE 4 1020 #define BNX_L2CTX_RX_LO_WATER_MARK_DIS 0 1021 #define BNX_L2CTX_RX_HI_WATER_MARK_SHIFT 4 1022 #define BNX_L2CTX_RX_HI_WATER_MARK_SCALE 16 1023 #define BNX_L2CTX_RX_WATER_MARKS_MSK 0x000000ff 1024 1025 #define BNX_L2CTX_RX_BD_PRE_READ 0x00000000 1026 #define BNX_L2CTX_RX_BD_PRE_READ_SHIFT 8 1027 1028 #define BNX_L2CTX_RX_CTX_SIZE 0x00000000 1029 #define BNX_L2CTX_RX_CTX_SIZE_SHIFT 16 1030 #define BNX_L2CTX_RX_CTX_TYPE_SIZE_L2 ((0x20/20)<<BNX_L2CTX_RX_CTX_SIZE_SHIFT) 1031 1032 #define BNX_L2CTX_RX_CTX_TYPE 0x00000000 1033 #define BNX_L2CTX_RX_CTX_TYPE_SHIFT 24 1034 1035 #define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28) 1036 #define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28) 1037 #define BNX_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28) 1038 1039 #define BNX_L2CTX_RX_HOST_BDIDX 0x00000004 1040 #define BNX_L2CTX_RX_HOST_BSEQ 0x00000008 1041 #define BNX_L2CTX_RX_NX_BSEQ 0x0000000c 1042 #define BNX_L2CTX_RX_NX_BDHADDR_HI 0x00000010 1043 #define BNX_L2CTX_RX_NX_BDHADDR_LO 0x00000014 1044 #define BNX_L2CTX_RX_NX_BDIDX 0x00000018 1045 1046 #define BNX_L2CTX_RX_HOST_PG_BDIDX 0x00000044 1047 #define BNX_L2CTX_RX_PG_BUF_SIZE 0x00000048 1048 #define BNX_L2CTX_RX_RBDC_KEY 0x0000004c 1049 #define BNX_L2CTX_RX_RBDC_JUMBO_KEY 0x3ffe 1050 #define BNX_L2CTX_RX_NX_PG_BDHADDR_HI 0x00000050 1051 #define BNX_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054 1052 #define BNX_L2CTX_RX_NX_PG_BDIDX 0x00000058 1053 1054 1055 /* 1056 * pci_config_l definition 1057 * offset: 0000 1058 */ 1059 #define BNX_PCICFG_MISC_CONFIG 0x00000068 1060 #define BNX_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2) 1061 #define BNX_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3) 1062 #define BNX_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5) 1063 #define BNX_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6) 1064 #define BNX_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7) 1065 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8) 1066 #define BNX_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9) 1067 #define BNX_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16) 1068 #define BNX_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24) 1069 #define BNX_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) 1070 #define BNX_PCICFG_MISC_CONFIG_ASIC_REV (0xffffL<<16) 1071 1072 #define BNX_PCICFG_MISC_STATUS 0x0000006c 1073 #define BNX_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0) 1074 #define BNX_PCICFG_MISC_STATUS_32BIT_DET (1L<<1) 1075 #define BNX_PCICFG_MISC_STATUS_M66EN (1L<<2) 1076 #define BNX_PCICFG_MISC_STATUS_PCIX_DET (1L<<3) 1077 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4) 1078 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4) 1079 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4) 1080 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4) 1081 #define BNX_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4) 1082 1083 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070 1084 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1085 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1086 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1087 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1088 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1089 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1090 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1091 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1092 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1093 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1094 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1095 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1096 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1097 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1098 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1099 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1100 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1101 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1102 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1103 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1104 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1105 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1106 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1107 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1108 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1109 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1110 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1111 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1112 #define BNX_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1113 1114 #define BNX_PCICFG_REG_WINDOW_ADDRESS 0x00000078 1115 #define BNX_PCICFG_REG_WINDOW 0x00000080 1116 #define BNX_PCICFG_INT_ACK_CMD 0x00000084 1117 #define BNX_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) 1118 #define BNX_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16) 1119 #define BNX_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17) 1120 #define BNX_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18) 1121 1122 #define BNX_PCICFG_STATUS_BIT_SET_CMD 0x00000088 1123 #define BNX_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c 1124 #define BNX_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 1125 #define BNX_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 1126 1127 1128 /* 1129 * pci_reg definition 1130 * offset: 0x400 1131 */ 1132 #define BNX_PCI_GRC_WINDOW_ADDR 0x00000400 1133 #define BNX_PCI_GRC_WINDOW_ADDR_PCI_GRC_WINDOW_ADDR_VALUE (0x3ffffL<<8) 1134 1135 #define BNX_PCI_CONFIG_1 0x00000404 1136 #define BNX_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) 1137 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8) 1138 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8) 1139 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8) 1140 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8) 1141 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8) 1142 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8) 1143 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8) 1144 #define BNX_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8) 1145 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11) 1146 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11) 1147 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11) 1148 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11) 1149 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11) 1150 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11) 1151 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11) 1152 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11) 1153 #define BNX_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11) 1154 1155 #define BNX_PCI_CONFIG_2 0x00000408 1156 #define BNX_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 1157 #define BNX_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 1158 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 1159 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 1160 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 1161 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 1162 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 1163 #define BNX_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 1164 #define BNX_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 1165 #define BNX_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 1166 #define BNX_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 1167 #define BNX_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 1168 #define BNX_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 1169 #define BNX_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 1170 #define BNX_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 1171 #define BNX_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 1172 #define BNX_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 1173 #define BNX_PCI_CONFIG_2_BAR1_64ENA (1L<<4) 1174 #define BNX_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 1175 #define BNX_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 1176 #define BNX_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 1177 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 1178 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 1179 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8) 1180 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8) 1181 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8) 1182 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8) 1183 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8) 1184 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8) 1185 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8) 1186 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8) 1187 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8) 1188 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8) 1189 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8) 1190 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8) 1191 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8) 1192 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8) 1193 #define BNX_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8) 1194 #define BNX_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16) 1195 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21) 1196 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21) 1197 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21) 1198 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21) 1199 #define BNX_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21) 1200 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23) 1201 #define BNX_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24) 1202 #define BNX_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25) 1203 1204 #define BNX_PCI_CONFIG_3 0x0000040c 1205 #define BNX_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 1206 #define BNX_PCI_CONFIG_3_FORCE_PME (1L<<24) 1207 #define BNX_PCI_CONFIG_3_PME_STATUS (1L<<25) 1208 #define BNX_PCI_CONFIG_3_PME_ENABLE (1L<<26) 1209 #define BNX_PCI_CONFIG_3_PM_STATE (0x3L<<27) 1210 #define BNX_PCI_CONFIG_3_VAUX_PRESET (1L<<30) 1211 #define BNX_PCI_CONFIG_3_PCI_POWER (1L<<31) 1212 1213 #define BNX_PCI_PM_DATA_A 0x00000410 1214 #define BNX_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0) 1215 #define BNX_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8) 1216 #define BNX_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16) 1217 #define BNX_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24) 1218 1219 #define BNX_PCI_PM_DATA_B 0x00000414 1220 #define BNX_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0) 1221 #define BNX_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8) 1222 #define BNX_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16) 1223 #define BNX_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24) 1224 1225 #define BNX_PCI_SWAP_DIAG0 0x00000418 1226 #define BNX_PCI_SWAP_DIAG1 0x0000041c 1227 #define BNX_PCI_EXP_ROM_ADDR 0x00000420 1228 #define BNX_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) 1229 #define BNX_PCI_EXP_ROM_ADDR_REQ (1L<<31) 1230 1231 #define BNX_PCI_EXP_ROM_DATA 0x00000424 1232 #define BNX_PCI_VPD_INTF 0x00000428 1233 #define BNX_PCI_VPD_INTF_INTF_REQ (1L<<0) 1234 1235 #define BNX_PCI_VPD_ADDR_FLAG 0x0000042c 1236 #define BNX_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) 1237 #define BNX_PCI_VPD_ADDR_FLAG_WR (1<<15) 1238 1239 #define BNX_PCI_VPD_DATA 0x00000430 1240 #define BNX_PCI_ID_VAL1 0x00000434 1241 #define BNX_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) 1242 #define BNX_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) 1243 1244 #define BNX_PCI_ID_VAL2 0x00000438 1245 #define BNX_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0) 1246 #define BNX_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) 1247 1248 #define BNX_PCI_ID_VAL3 0x0000043c 1249 #define BNX_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) 1250 #define BNX_PCI_ID_VAL3_REVISION_ID (0xffL<<24) 1251 1252 #define BNX_PCI_ID_VAL4 0x00000440 1253 #define BNX_PCI_ID_VAL4_CAP_ENA (0xfL<<0) 1254 #define BNX_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) 1255 #define BNX_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) 1256 #define BNX_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) 1257 #define BNX_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) 1258 #define BNX_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) 1259 #define BNX_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) 1260 #define BNX_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) 1261 #define BNX_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) 1262 #define BNX_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) 1263 #define BNX_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) 1264 #define BNX_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) 1265 #define BNX_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) 1266 #define BNX_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) 1267 #define BNX_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) 1268 #define BNX_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) 1269 #define BNX_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) 1270 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) 1271 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) 1272 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) 1273 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) 1274 #define BNX_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) 1275 #define BNX_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) 1276 #define BNX_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) 1277 #define BNX_PCI_ID_VAL4_MSI_ENABLE (1L<<15) 1278 #define BNX_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16) 1279 #define BNX_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17) 1280 #define BNX_PCI_ID_VAL4_MAX_MEM_READ_SIZE (0x3L<<21) 1281 #define BNX_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) 1282 #define BNX_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE (0x7L<<26) 1283 1284 #define BNX_PCI_ID_VAL5 0x00000444 1285 #define BNX_PCI_ID_VAL5_D1_SUPPORT (1L<<0) 1286 #define BNX_PCI_ID_VAL5_D2_SUPPORT (1L<<1) 1287 #define BNX_PCI_ID_VAL5_PME_IN_D0 (1L<<2) 1288 #define BNX_PCI_ID_VAL5_PME_IN_D1 (1L<<3) 1289 #define BNX_PCI_ID_VAL5_PME_IN_D2 (1L<<4) 1290 #define BNX_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) 1291 1292 #define BNX_PCI_PCIX_EXTENDED_STATUS 0x00000448 1293 #define BNX_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8) 1294 #define BNX_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9) 1295 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16) 1296 #define BNX_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24) 1297 1298 #define BNX_PCI_ID_VAL6 0x0000044c 1299 #define BNX_PCI_ID_VAL6_MAX_LAT (0xffL<<0) 1300 #define BNX_PCI_ID_VAL6_MIN_GNT (0xffL<<8) 1301 #define BNX_PCI_ID_VAL6_BIST (0xffL<<16) 1302 1303 #define BNX_PCI_MSI_DATA 0x00000450 1304 #define BNX_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) 1305 1306 #define BNX_PCI_MSI_ADDR_H 0x00000454 1307 #define BNX_PCI_MSI_ADDR_L 0x00000458 1308 1309 1310 /* 1311 * misc_reg definition 1312 * offset: 0x800 1313 */ 1314 #define BNX_MISC_COMMAND 0x00000800 1315 #define BNX_MISC_COMMAND_ENABLE_ALL (1L<<0) 1316 #define BNX_MISC_COMMAND_DISABLE_ALL (1L<<1) 1317 #define BNX_MISC_COMMAND_SW_RESET (1L<<4) 1318 #define BNX_MISC_COMMAND_POR_RESET (1L<<5) 1319 #define BNX_MISC_COMMAND_HD_RESET (1L<<6) 1320 #define BNX_MISC_COMMAND_CMN_SW_RESET (1L<<7) 1321 #define BNX_MISC_COMMAND_PAR_ERROR (1L<<8) 1322 #define BNX_MISC_COMMAND_CS16_ERR (1L<<9) 1323 #define BNX_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12) 1324 #define BNX_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) 1325 #define BNX_MISC_COMMAND_POWERDOWN_EVENT (1L<<23) 1326 #define BNX_MISC_COMMAND_SW_SHUTDOWN (1L<<24) 1327 #define BNX_MISC_COMMAND_SHUTDOWN_EN (1L<<25) 1328 #define BNX_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26) 1329 #define BNX_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27) 1330 #define BNX_MISC_COMMAND_PCIE_DIS (1L<<28) 1331 1332 #define BNX_MISC_CFG 0x00000804 1333 #define BNX_MISC_CFG_PCI_GRC_TMOUT (1L<<0) 1334 #define BNX_MISC_CFG_NVM_WR_EN (0x3L<<1) 1335 #define BNX_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) 1336 #define BNX_MISC_CFG_NVM_WR_EN_PCI (1L<<1) 1337 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) 1338 #define BNX_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) 1339 #define BNX_MISC_CFG_BIST_EN (1L<<3) 1340 #define BNX_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) 1341 #define BNX_MISC_CFG_BYPASS_BSCAN (1L<<5) 1342 #define BNX_MISC_CFG_BYPASS_EJTAG (1L<<6) 1343 #define BNX_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) 1344 #define BNX_MISC_CFG_LEDMODE (0x3L<<8) 1345 #define BNX_MISC_CFG_LEDMODE_MAC (0L<<8) 1346 #define BNX_MISC_CFG_LEDMODE_GPHY1 (1L<<8) 1347 #define BNX_MISC_CFG_LEDMODE_GPHY2 (2L<<8) 1348 1349 #define BNX_MISC_ID 0x00000808 1350 #define BNX_MISC_ID_BOND_ID (0xfL<<0) 1351 #define BNX_MISC_ID_CHIP_METAL (0xffL<<4) 1352 #define BNX_MISC_ID_CHIP_REV (0xfL<<12) 1353 #define BNX_MISC_ID_CHIP_NUM (0xffffL<<16) 1354 1355 #define BNX_MISC_ENABLE_STATUS_BITS 0x0000080c 1356 #define BNX_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1357 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1) 1358 #define BNX_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1359 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1360 #define BNX_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4) 1361 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5) 1362 #define BNX_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1363 #define BNX_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1364 #define BNX_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1365 #define BNX_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9) 1366 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1367 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1368 #define BNX_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12) 1369 #define BNX_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13) 1370 #define BNX_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1371 #define BNX_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15) 1372 #define BNX_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1373 #define BNX_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17) 1374 #define BNX_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18) 1375 #define BNX_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19) 1376 #define BNX_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1377 #define BNX_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21) 1378 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1379 #define BNX_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1380 #define BNX_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1381 #define BNX_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25) 1382 #define BNX_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26) 1383 #define BNX_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27) 1384 1385 #define BNX_MISC_ENABLE_SET_BITS 0x00000810 1386 #define BNX_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1387 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1) 1388 #define BNX_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1389 #define BNX_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1390 #define BNX_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4) 1391 #define BNX_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5) 1392 #define BNX_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1393 #define BNX_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1394 #define BNX_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1395 #define BNX_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9) 1396 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1397 #define BNX_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1398 #define BNX_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12) 1399 #define BNX_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13) 1400 #define BNX_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1401 #define BNX_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15) 1402 #define BNX_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1403 #define BNX_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17) 1404 #define BNX_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18) 1405 #define BNX_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19) 1406 #define BNX_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1407 #define BNX_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21) 1408 #define BNX_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1409 #define BNX_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1410 #define BNX_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1411 #define BNX_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25) 1412 #define BNX_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26) 1413 #define BNX_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27) 1414 1415 #define BNX_MISC_ENABLE_DEFAULT 0x05ffffff 1416 #define BNX_MISC_ENABLE_DEFAULT_XI 0x17ffffff 1417 1418 #define BNX_MISC_ENABLE_CLR_BITS 0x00000814 1419 #define BNX_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1420 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1) 1421 #define BNX_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1422 #define BNX_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1423 #define BNX_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4) 1424 #define BNX_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5) 1425 #define BNX_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1426 #define BNX_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1427 #define BNX_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1428 #define BNX_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9) 1429 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1430 #define BNX_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1431 #define BNX_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12) 1432 #define BNX_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13) 1433 #define BNX_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1434 #define BNX_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15) 1435 #define BNX_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1436 #define BNX_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17) 1437 #define BNX_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18) 1438 #define BNX_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19) 1439 #define BNX_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1440 #define BNX_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21) 1441 #define BNX_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1442 #define BNX_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1443 #define BNX_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1444 #define BNX_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25) 1445 #define BNX_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26) 1446 #define BNX_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27) 1447 1448 #define BNX_MISC_CLOCK_CONTROL_BITS 0x00000818 1449 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0) 1450 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0) 1451 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0) 1452 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0) 1453 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0) 1454 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0) 1455 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0) 1456 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0) 1457 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0) 1458 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0) 1459 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6) 1460 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7) 1461 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8) 1462 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8) 1463 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8) 1464 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8) 1465 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8) 1466 #define BNX_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11) 1467 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12) 1468 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12) 1469 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12) 1470 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12) 1471 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12) 1472 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12) 1473 #define BNX_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16) 1474 #define BNX_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17) 1475 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18) 1476 #define BNX_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19) 1477 #define BNX_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20) 1478 1479 #define BNX_MISC_GPIO 0x0000081c 1480 #define BNX_MISC_GPIO_VALUE (0xffL<<0) 1481 #define BNX_MISC_GPIO_SET (0xffL<<8) 1482 #define BNX_MISC_GPIO_CLR (0xffL<<16) 1483 #define BNX_MISC_GPIO_FLOAT (0xffL<<24) 1484 1485 #define BNX_MISC_GPIO_INT 0x00000820 1486 #define BNX_MISC_GPIO_INT_INT_STATE (0xfL<<0) 1487 #define BNX_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) 1488 #define BNX_MISC_GPIO_INT_OLD_SET (0xfL<<16) 1489 #define BNX_MISC_GPIO_INT_OLD_CLR (0xfL<<24) 1490 1491 #define BNX_MISC_CONFIG_LFSR 0x00000824 1492 #define BNX_MISC_CONFIG_LFSR_DIV (0xffffL<<0) 1493 1494 #define BNX_MISC_LFSR_MASK_BITS 0x00000828 1495 #define BNX_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0) 1496 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1) 1497 #define BNX_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2) 1498 #define BNX_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3) 1499 #define BNX_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4) 1500 #define BNX_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5) 1501 #define BNX_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6) 1502 #define BNX_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7) 1503 #define BNX_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8) 1504 #define BNX_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9) 1505 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10) 1506 #define BNX_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11) 1507 #define BNX_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12) 1508 #define BNX_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13) 1509 #define BNX_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14) 1510 #define BNX_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15) 1511 #define BNX_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16) 1512 #define BNX_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17) 1513 #define BNX_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18) 1514 #define BNX_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19) 1515 #define BNX_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20) 1516 #define BNX_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21) 1517 #define BNX_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22) 1518 #define BNX_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23) 1519 #define BNX_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24) 1520 #define BNX_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25) 1521 #define BNX_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26) 1522 #define BNX_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27) 1523 1524 #define BNX_MISC_ARB_REQ0 0x0000082c 1525 #define BNX_MISC_ARB_REQ1 0x00000830 1526 #define BNX_MISC_ARB_REQ2 0x00000834 1527 #define BNX_MISC_ARB_REQ3 0x00000838 1528 #define BNX_MISC_ARB_REQ4 0x0000083c 1529 #define BNX_MISC_ARB_FREE0 0x00000840 1530 #define BNX_MISC_ARB_FREE1 0x00000844 1531 #define BNX_MISC_ARB_FREE2 0x00000848 1532 #define BNX_MISC_ARB_FREE3 0x0000084c 1533 #define BNX_MISC_ARB_FREE4 0x00000850 1534 #define BNX_MISC_ARB_REQ_STATUS0 0x00000854 1535 #define BNX_MISC_ARB_REQ_STATUS1 0x00000858 1536 #define BNX_MISC_ARB_REQ_STATUS2 0x0000085c 1537 #define BNX_MISC_ARB_REQ_STATUS3 0x00000860 1538 #define BNX_MISC_ARB_REQ_STATUS4 0x00000864 1539 #define BNX_MISC_ARB_GNT0 0x00000868 1540 #define BNX_MISC_ARB_GNT0_0 (0x7L<<0) 1541 #define BNX_MISC_ARB_GNT0_1 (0x7L<<4) 1542 #define BNX_MISC_ARB_GNT0_2 (0x7L<<8) 1543 #define BNX_MISC_ARB_GNT0_3 (0x7L<<12) 1544 #define BNX_MISC_ARB_GNT0_4 (0x7L<<16) 1545 #define BNX_MISC_ARB_GNT0_5 (0x7L<<20) 1546 #define BNX_MISC_ARB_GNT0_6 (0x7L<<24) 1547 #define BNX_MISC_ARB_GNT0_7 (0x7L<<28) 1548 1549 #define BNX_MISC_ARB_GNT1 0x0000086c 1550 #define BNX_MISC_ARB_GNT1_8 (0x7L<<0) 1551 #define BNX_MISC_ARB_GNT1_9 (0x7L<<4) 1552 #define BNX_MISC_ARB_GNT1_10 (0x7L<<8) 1553 #define BNX_MISC_ARB_GNT1_11 (0x7L<<12) 1554 #define BNX_MISC_ARB_GNT1_12 (0x7L<<16) 1555 #define BNX_MISC_ARB_GNT1_13 (0x7L<<20) 1556 #define BNX_MISC_ARB_GNT1_14 (0x7L<<24) 1557 #define BNX_MISC_ARB_GNT1_15 (0x7L<<28) 1558 1559 #define BNX_MISC_ARB_GNT2 0x00000870 1560 #define BNX_MISC_ARB_GNT2_16 (0x7L<<0) 1561 #define BNX_MISC_ARB_GNT2_17 (0x7L<<4) 1562 #define BNX_MISC_ARB_GNT2_18 (0x7L<<8) 1563 #define BNX_MISC_ARB_GNT2_19 (0x7L<<12) 1564 #define BNX_MISC_ARB_GNT2_20 (0x7L<<16) 1565 #define BNX_MISC_ARB_GNT2_21 (0x7L<<20) 1566 #define BNX_MISC_ARB_GNT2_22 (0x7L<<24) 1567 #define BNX_MISC_ARB_GNT2_23 (0x7L<<28) 1568 1569 #define BNX_MISC_ARB_GNT3 0x00000874 1570 #define BNX_MISC_ARB_GNT3_24 (0x7L<<0) 1571 #define BNX_MISC_ARB_GNT3_25 (0x7L<<4) 1572 #define BNX_MISC_ARB_GNT3_26 (0x7L<<8) 1573 #define BNX_MISC_ARB_GNT3_27 (0x7L<<12) 1574 #define BNX_MISC_ARB_GNT3_28 (0x7L<<16) 1575 #define BNX_MISC_ARB_GNT3_29 (0x7L<<20) 1576 #define BNX_MISC_ARB_GNT3_30 (0x7L<<24) 1577 #define BNX_MISC_ARB_GNT3_31 (0x7L<<28) 1578 1579 #define BNX_MISC_PRBS_CONTROL 0x00000878 1580 #define BNX_MISC_PRBS_CONTROL_EN (1L<<0) 1581 #define BNX_MISC_PRBS_CONTROL_RSTB (1L<<1) 1582 #define BNX_MISC_PRBS_CONTROL_INV (1L<<2) 1583 #define BNX_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) 1584 #define BNX_MISC_PRBS_CONTROL_ORDER (0x3L<<4) 1585 #define BNX_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4) 1586 #define BNX_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4) 1587 #define BNX_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4) 1588 #define BNX_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4) 1589 1590 #define BNX_MISC_PRBS_STATUS 0x0000087c 1591 #define BNX_MISC_PRBS_STATUS_LOCK (1L<<0) 1592 #define BNX_MISC_PRBS_STATUS_STKY (1L<<1) 1593 #define BNX_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) 1594 #define BNX_MISC_PRBS_STATUS_STATE (0xfL<<16) 1595 1596 #define BNX_MISC_SM_ASF_CONTROL 0x00000880 1597 #define BNX_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0) 1598 #define BNX_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) 1599 #define BNX_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) 1600 #define BNX_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) 1601 #define BNX_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) 1602 #define BNX_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) 1603 #define BNX_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) 1604 #define BNX_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7) 1605 #define BNX_MISC_SM_ASF_CONTROL_RES (0xfL<<8) 1606 #define BNX_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) 1607 #define BNX_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13) 1608 #define BNX_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14) 1609 #define BNX_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15) 1610 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16) 1611 #define BNX_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24) 1612 #define BNX_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30) 1613 #define BNX_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31) 1614 1615 #define BNX_MISC_SMB_IN 0x00000884 1616 #define BNX_MISC_SMB_IN_DAT_IN (0xffL<<0) 1617 #define BNX_MISC_SMB_IN_RDY (1L<<8) 1618 #define BNX_MISC_SMB_IN_DONE (1L<<9) 1619 #define BNX_MISC_SMB_IN_FIRSTBYTE (1L<<10) 1620 #define BNX_MISC_SMB_IN_STATUS (0x7L<<11) 1621 #define BNX_MISC_SMB_IN_STATUS_OK (0x0L<<11) 1622 #define BNX_MISC_SMB_IN_STATUS_PEC (0x1L<<11) 1623 #define BNX_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) 1624 #define BNX_MISC_SMB_IN_STATUS_STOP (0x3L<<11) 1625 #define BNX_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) 1626 1627 #define BNX_MISC_SMB_OUT 0x00000888 1628 #define BNX_MISC_SMB_OUT_DAT_OUT (0xffL<<0) 1629 #define BNX_MISC_SMB_OUT_RDY (1L<<8) 1630 #define BNX_MISC_SMB_OUT_START (1L<<9) 1631 #define BNX_MISC_SMB_OUT_LAST (1L<<10) 1632 #define BNX_MISC_SMB_OUT_ACC_TYPE (1L<<11) 1633 #define BNX_MISC_SMB_OUT_ENB_PEC (1L<<12) 1634 #define BNX_MISC_SMB_OUT_GET_RX_LEN (1L<<13) 1635 #define BNX_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) 1636 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20) 1637 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20) 1638 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20) 1639 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20) 1640 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20) 1641 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20) 1642 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20) 1643 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20) 1644 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20) 1645 #define BNX_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20) 1646 #define BNX_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24) 1647 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25) 1648 #define BNX_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26) 1649 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27) 1650 #define BNX_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28) 1651 1652 #define BNX_MISC_SMB_WATCHDOG 0x0000088c 1653 #define BNX_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) 1654 1655 #define BNX_MISC_SMB_HEARTBEAT 0x00000890 1656 #define BNX_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0) 1657 1658 #define BNX_MISC_SMB_POLL_ASF 0x00000894 1659 #define BNX_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) 1660 1661 #define BNX_MISC_SMB_POLL_LEGACY 0x00000898 1662 #define BNX_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0) 1663 1664 #define BNX_MISC_SMB_RETRAN 0x0000089c 1665 #define BNX_MISC_SMB_RETRAN_RETRAN (0xffL<<0) 1666 1667 #define BNX_MISC_SMB_TIMESTAMP 0x000008a0 1668 #define BNX_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0) 1669 1670 #define BNX_MISC_PERR_ENA0 0x000008a4 1671 #define BNX_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0) 1672 #define BNX_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1) 1673 #define BNX_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2) 1674 #define BNX_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3) 1675 #define BNX_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4) 1676 #define BNX_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5) 1677 #define BNX_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6) 1678 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7) 1679 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8) 1680 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9) 1681 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10) 1682 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11) 1683 #define BNX_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12) 1684 #define BNX_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13) 1685 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14) 1686 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15) 1687 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16) 1688 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17) 1689 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18) 1690 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19) 1691 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20) 1692 #define BNX_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21) 1693 #define BNX_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) 1694 #define BNX_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23) 1695 #define BNX_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24) 1696 #define BNX_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) 1697 #define BNX_MISC_PERR_ENA0_RBDC_MISC (1L<<26) 1698 #define BNX_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27) 1699 #define BNX_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28) 1700 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29) 1701 #define BNX_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30) 1702 #define BNX_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31) 1703 1704 #define BNX_MISC_PERR_ENA1 0x000008a8 1705 #define BNX_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0) 1706 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1) 1707 #define BNX_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2) 1708 #define BNX_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3) 1709 #define BNX_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4) 1710 #define BNX_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5) 1711 #define BNX_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6) 1712 #define BNX_MISC_PERR_ENA1_TBDC_MISC (1L<<7) 1713 #define BNX_MISC_PERR_ENA1_TDMA_MISC (1L<<8) 1714 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9) 1715 #define BNX_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10) 1716 #define BNX_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11) 1717 #define BNX_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12) 1718 #define BNX_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13) 1719 #define BNX_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14) 1720 #define BNX_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15) 1721 #define BNX_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16) 1722 #define BNX_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17) 1723 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18) 1724 #define BNX_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19) 1725 #define BNX_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) 1726 #define BNX_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) 1727 #define BNX_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) 1728 #define BNX_MISC_PERR_ENA1_CSQ_MISC (1L<<23) 1729 #define BNX_MISC_PERR_ENA1_CPQ_MISC (1L<<24) 1730 #define BNX_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) 1731 #define BNX_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) 1732 #define BNX_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) 1733 #define BNX_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) 1734 #define BNX_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) 1735 #define BNX_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) 1736 #define BNX_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) 1737 1738 #define BNX_MISC_PERR_ENA2 0x000008ac 1739 #define BNX_MISC_PERR_ENA2_COMQ_MISC (1L<<0) 1740 #define BNX_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) 1741 #define BNX_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) 1742 #define BNX_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) 1743 #define BNX_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) 1744 #define BNX_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) 1745 #define BNX_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) 1746 #define BNX_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) 1747 #define BNX_MISC_PERR_ENA2_TASQ_MISC (1L<<8) 1748 1749 #define BNX_MISC_DEBUG_VECTOR_SEL 0x000008b0 1750 #define BNX_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) 1751 #define BNX_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) 1752 1753 #define BNX_MISC_VREG_CONTROL 0x000008b4 1754 #define BNX_MISC_VREG_CONTROL_1_2 (0xfL<<0) 1755 #define BNX_MISC_VREG_CONTROL_2_5 (0xfL<<4) 1756 1757 #define BNX_MISC_FINAL_CLK_CTL_VAL 0x000008b8 1758 #define BNX_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6) 1759 1760 #define BNX_MISC_NEW_CORE_CTL 0x000008c8 1761 #define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0) 1762 #define BNX_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1) 1763 #define BNX_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16) 1764 #define BNX_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2) 1765 #define BNX_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16) 1766 1767 #define BNX_MISC_DUAL_MEDIA_CTRL 0x000008ec 1768 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0) 1769 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0) 1770 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0) 1771 #define BNX_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0) 1772 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8) 1773 #define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11) 1774 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12) 1775 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13) 1776 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14) 1777 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15) 1778 #define BNX_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16) 1779 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17) 1780 #define BNX_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18) 1781 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19) 1782 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20) 1783 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21) 1784 #define BNX_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24) 1785 #define BNX_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25) 1786 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26) 1787 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26) 1788 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26) 1789 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26) 1790 #define BNX_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26) 1791 1792 #define BNX_MISC_UNUSED0 0x000008bc 1793 1794 1795 /* 1796 * nvm_reg definition 1797 * offset: 0x6400 1798 */ 1799 #define BNX_NVM_COMMAND 0x00006400 1800 #define BNX_NVM_COMMAND_RST (1L<<0) 1801 #define BNX_NVM_COMMAND_DONE (1L<<3) 1802 #define BNX_NVM_COMMAND_DOIT (1L<<4) 1803 #define BNX_NVM_COMMAND_WR (1L<<5) 1804 #define BNX_NVM_COMMAND_ERASE (1L<<6) 1805 #define BNX_NVM_COMMAND_FIRST (1L<<7) 1806 #define BNX_NVM_COMMAND_LAST (1L<<8) 1807 #define BNX_NVM_COMMAND_WREN (1L<<16) 1808 #define BNX_NVM_COMMAND_WRDI (1L<<17) 1809 #define BNX_NVM_COMMAND_EWSR (1L<<18) 1810 #define BNX_NVM_COMMAND_WRSR (1L<<19) 1811 1812 #define BNX_NVM_STATUS 0x00006404 1813 #define BNX_NVM_STATUS_PI_FSM_STATE (0xfL<<0) 1814 #define BNX_NVM_STATUS_EE_FSM_STATE (0xfL<<4) 1815 #define BNX_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) 1816 1817 #define BNX_NVM_WRITE 0x00006408 1818 #define BNX_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) 1819 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0) 1820 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0) 1821 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0) 1822 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0) 1823 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0) 1824 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0) 1825 #define BNX_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0) 1826 1827 #define BNX_NVM_ADDR 0x0000640c 1828 #define BNX_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 1829 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0) 1830 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0) 1831 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0) 1832 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0) 1833 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0) 1834 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) 1835 #define BNX_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) 1836 1837 #define BNX_NVM_READ 0x00006410 1838 #define BNX_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) 1839 #define BNX_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0) 1840 #define BNX_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0) 1841 #define BNX_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0) 1842 #define BNX_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0) 1843 #define BNX_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0) 1844 #define BNX_NVM_READ_NVM_READ_VALUE_SO (16L<<0) 1845 #define BNX_NVM_READ_NVM_READ_VALUE_SI (32L<<0) 1846 1847 #define BNX_NVM_CFG1 0x00006414 1848 #define BNX_NVM_CFG1_FLASH_MODE (1L<<0) 1849 #define BNX_NVM_CFG1_BUFFER_MODE (1L<<1) 1850 #define BNX_NVM_CFG1_PASS_MODE (1L<<2) 1851 #define BNX_NVM_CFG1_BITBANG_MODE (1L<<3) 1852 #define BNX_NVM_CFG1_STATUS_BIT (0x7L<<4) 1853 #define BNX_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4) 1854 #define BNX_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4) 1855 #define BNX_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) 1856 #define BNX_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) 1857 #define BNX_NVM_CFG1_PROTECT_MODE (1L<<24) 1858 #define BNX_NVM_CFG1_FLASH_SIZE (1L<<25) 1859 #define BNX_NVM_CFG1_COMPAT_BYPASSS (1L<<31) 1860 1861 #define BNX_NVM_CFG2 0x00006418 1862 #define BNX_NVM_CFG2_ERASE_CMD (0xffL<<0) 1863 #define BNX_NVM_CFG2_DUMMY (0xffL<<8) 1864 #define BNX_NVM_CFG2_STATUS_CMD (0xffL<<16) 1865 1866 #define BNX_NVM_CFG3 0x0000641c 1867 #define BNX_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) 1868 #define BNX_NVM_CFG3_WRITE_CMD (0xffL<<8) 1869 #define BNX_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) 1870 #define BNX_NVM_CFG3_READ_CMD (0xffL<<24) 1871 1872 #define BNX_NVM_SW_ARB 0x00006420 1873 #define BNX_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) 1874 #define BNX_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 1875 #define BNX_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) 1876 #define BNX_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) 1877 #define BNX_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) 1878 #define BNX_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 1879 #define BNX_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) 1880 #define BNX_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) 1881 #define BNX_NVM_SW_ARB_ARB_ARB0 (1L<<8) 1882 #define BNX_NVM_SW_ARB_ARB_ARB1 (1L<<9) 1883 #define BNX_NVM_SW_ARB_ARB_ARB2 (1L<<10) 1884 #define BNX_NVM_SW_ARB_ARB_ARB3 (1L<<11) 1885 #define BNX_NVM_SW_ARB_REQ0 (1L<<12) 1886 #define BNX_NVM_SW_ARB_REQ1 (1L<<13) 1887 #define BNX_NVM_SW_ARB_REQ2 (1L<<14) 1888 #define BNX_NVM_SW_ARB_REQ3 (1L<<15) 1889 1890 #define BNX_NVM_ACCESS_ENABLE 0x00006424 1891 #define BNX_NVM_ACCESS_ENABLE_EN (1L<<0) 1892 #define BNX_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 1893 1894 #define BNX_NVM_WRITE1 0x00006428 1895 #define BNX_NVM_WRITE1_WREN_CMD (0xffL<<0) 1896 #define BNX_NVM_WRITE1_WRDI_CMD (0xffL<<8) 1897 #define BNX_NVM_WRITE1_SR_DATA (0xffL<<16) 1898 1899 1900 1901 /* 1902 * dma_reg definition 1903 * offset: 0xc00 1904 */ 1905 #define BNX_DMA_COMMAND 0x00000c00 1906 #define BNX_DMA_COMMAND_ENABLE (1L<<0) 1907 1908 #define BNX_DMA_STATUS 0x00000c04 1909 #define BNX_DMA_STATUS_PAR_ERROR_STATE (1L<<0) 1910 #define BNX_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16) 1911 #define BNX_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17) 1912 #define BNX_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18) 1913 #define BNX_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19) 1914 #define BNX_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20) 1915 #define BNX_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21) 1916 #define BNX_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22) 1917 #define BNX_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23) 1918 #define BNX_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24) 1919 #define BNX_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25) 1920 1921 #define BNX_DMA_CONFIG 0x00000c08 1922 #define BNX_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) 1923 #define BNX_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) 1924 #define BNX_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) 1925 #define BNX_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) 1926 #define BNX_DMA_CONFIG_ONE_DMA (1L<<6) 1927 #define BNX_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) 1928 #define BNX_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) 1929 #define BNX_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10) 1930 #define BNX_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11) 1931 #define BNX_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12) 1932 #define BNX_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16) 1933 #define BNX_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20) 1934 #define BNX_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23) 1935 #define BNX_DMA_CONFIG_BIG_SIZE (0xfL<<24) 1936 #define BNX_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) 1937 #define BNX_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) 1938 #define BNX_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) 1939 #define BNX_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) 1940 #define BNX_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) 1941 1942 #define BNX_DMA_BLACKOUT 0x00000c0c 1943 #define BNX_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0) 1944 #define BNX_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8) 1945 #define BNX_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16) 1946 1947 #define BNX_DMA_RCHAN_STAT 0x00000c30 1948 #define BNX_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1949 #define BNX_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) 1950 #define BNX_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1951 #define BNX_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) 1952 #define BNX_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1953 #define BNX_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) 1954 #define BNX_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1955 #define BNX_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) 1956 #define BNX_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1957 #define BNX_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) 1958 #define BNX_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1959 #define BNX_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) 1960 #define BNX_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1961 #define BNX_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) 1962 #define BNX_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1963 #define BNX_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) 1964 1965 #define BNX_DMA_WCHAN_STAT 0x00000c34 1966 #define BNX_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) 1967 #define BNX_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) 1968 #define BNX_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) 1969 #define BNX_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) 1970 #define BNX_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) 1971 #define BNX_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) 1972 #define BNX_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) 1973 #define BNX_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) 1974 #define BNX_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) 1975 #define BNX_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) 1976 #define BNX_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) 1977 #define BNX_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) 1978 #define BNX_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) 1979 #define BNX_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) 1980 #define BNX_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) 1981 #define BNX_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) 1982 1983 #define BNX_DMA_RCHAN_ASSIGNMENT 0x00000c38 1984 #define BNX_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) 1985 #define BNX_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) 1986 #define BNX_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) 1987 #define BNX_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) 1988 #define BNX_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) 1989 #define BNX_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) 1990 #define BNX_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) 1991 #define BNX_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) 1992 1993 #define BNX_DMA_WCHAN_ASSIGNMENT 0x00000c3c 1994 #define BNX_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) 1995 #define BNX_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) 1996 #define BNX_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) 1997 #define BNX_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) 1998 #define BNX_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) 1999 #define BNX_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) 2000 #define BNX_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) 2001 #define BNX_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) 2002 2003 #define BNX_DMA_RCHAN_STAT_00 0x00000c40 2004 #define BNX_DMA_RCHAN_STAT_00_RCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2005 2006 #define BNX_DMA_RCHAN_STAT_01 0x00000c44 2007 #define BNX_DMA_RCHAN_STAT_01_RCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2008 2009 #define BNX_DMA_RCHAN_STAT_02 0x00000c48 2010 #define BNX_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) 2011 #define BNX_DMA_RCHAN_STAT_02_WORD_SWAP (1L<<16) 2012 #define BNX_DMA_RCHAN_STAT_02_BYTE_SWAP (1L<<17) 2013 #define BNX_DMA_RCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2014 2015 #define BNX_DMA_RCHAN_STAT_10 0x00000c4c 2016 #define BNX_DMA_RCHAN_STAT_11 0x00000c50 2017 #define BNX_DMA_RCHAN_STAT_12 0x00000c54 2018 #define BNX_DMA_RCHAN_STAT_20 0x00000c58 2019 #define BNX_DMA_RCHAN_STAT_21 0x00000c5c 2020 #define BNX_DMA_RCHAN_STAT_22 0x00000c60 2021 #define BNX_DMA_RCHAN_STAT_30 0x00000c64 2022 #define BNX_DMA_RCHAN_STAT_31 0x00000c68 2023 #define BNX_DMA_RCHAN_STAT_32 0x00000c6c 2024 #define BNX_DMA_RCHAN_STAT_40 0x00000c70 2025 #define BNX_DMA_RCHAN_STAT_41 0x00000c74 2026 #define BNX_DMA_RCHAN_STAT_42 0x00000c78 2027 #define BNX_DMA_RCHAN_STAT_50 0x00000c7c 2028 #define BNX_DMA_RCHAN_STAT_51 0x00000c80 2029 #define BNX_DMA_RCHAN_STAT_52 0x00000c84 2030 #define BNX_DMA_RCHAN_STAT_60 0x00000c88 2031 #define BNX_DMA_RCHAN_STAT_61 0x00000c8c 2032 #define BNX_DMA_RCHAN_STAT_62 0x00000c90 2033 #define BNX_DMA_RCHAN_STAT_70 0x00000c94 2034 #define BNX_DMA_RCHAN_STAT_71 0x00000c98 2035 #define BNX_DMA_RCHAN_STAT_72 0x00000c9c 2036 #define BNX_DMA_WCHAN_STAT_00 0x00000ca0 2037 #define BNX_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0) 2038 2039 #define BNX_DMA_WCHAN_STAT_01 0x00000ca4 2040 #define BNX_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0) 2041 2042 #define BNX_DMA_WCHAN_STAT_02 0x00000ca8 2043 #define BNX_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) 2044 #define BNX_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16) 2045 #define BNX_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17) 2046 #define BNX_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18) 2047 2048 #define BNX_DMA_WCHAN_STAT_10 0x00000cac 2049 #define BNX_DMA_WCHAN_STAT_11 0x00000cb0 2050 #define BNX_DMA_WCHAN_STAT_12 0x00000cb4 2051 #define BNX_DMA_WCHAN_STAT_20 0x00000cb8 2052 #define BNX_DMA_WCHAN_STAT_21 0x00000cbc 2053 #define BNX_DMA_WCHAN_STAT_22 0x00000cc0 2054 #define BNX_DMA_WCHAN_STAT_30 0x00000cc4 2055 #define BNX_DMA_WCHAN_STAT_31 0x00000cc8 2056 #define BNX_DMA_WCHAN_STAT_32 0x00000ccc 2057 #define BNX_DMA_WCHAN_STAT_40 0x00000cd0 2058 #define BNX_DMA_WCHAN_STAT_41 0x00000cd4 2059 #define BNX_DMA_WCHAN_STAT_42 0x00000cd8 2060 #define BNX_DMA_WCHAN_STAT_50 0x00000cdc 2061 #define BNX_DMA_WCHAN_STAT_51 0x00000ce0 2062 #define BNX_DMA_WCHAN_STAT_52 0x00000ce4 2063 #define BNX_DMA_WCHAN_STAT_60 0x00000ce8 2064 #define BNX_DMA_WCHAN_STAT_61 0x00000cec 2065 #define BNX_DMA_WCHAN_STAT_62 0x00000cf0 2066 #define BNX_DMA_WCHAN_STAT_70 0x00000cf4 2067 #define BNX_DMA_WCHAN_STAT_71 0x00000cf8 2068 #define BNX_DMA_WCHAN_STAT_72 0x00000cfc 2069 #define BNX_DMA_ARB_STAT_00 0x00000d00 2070 #define BNX_DMA_ARB_STAT_00_MASTER (0xffffL<<0) 2071 #define BNX_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) 2072 #define BNX_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24) 2073 2074 #define BNX_DMA_ARB_STAT_01 0x00000d04 2075 #define BNX_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) 2076 #define BNX_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) 2077 #define BNX_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) 2078 #define BNX_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) 2079 #define BNX_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) 2080 #define BNX_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) 2081 #define BNX_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) 2082 #define BNX_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) 2083 2084 #define BNX_DMA_FUSE_CTRL0_CMD 0x00000f00 2085 #define BNX_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0) 2086 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1) 2087 #define BNX_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) 2088 #define BNX_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) 2089 #define BNX_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) 2090 2091 #define BNX_DMA_FUSE_CTRL0_DATA 0x00000f04 2092 #define BNX_DMA_FUSE_CTRL1_CMD 0x00000f08 2093 #define BNX_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0) 2094 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1) 2095 #define BNX_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) 2096 #define BNX_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) 2097 #define BNX_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) 2098 2099 #define BNX_DMA_FUSE_CTRL1_DATA 0x00000f0c 2100 #define BNX_DMA_FUSE_CTRL2_CMD 0x00000f10 2101 #define BNX_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0) 2102 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1) 2103 #define BNX_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) 2104 #define BNX_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) 2105 #define BNX_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) 2106 2107 #define BNX_DMA_FUSE_CTRL2_DATA 0x00000f14 2108 2109 2110 /* 2111 * context_reg definition 2112 * offset: 0x1000 2113 */ 2114 #define BNX_CTX_COMMAND 0x00001000 2115 #define BNX_CTX_COMMAND_ENABLED (1L<<0) 2116 #define BNX_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1) 2117 #define BNX_CTX_COMMAND_DISABLE_PLRU (1L<<2) 2118 #define BNX_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3) 2119 #define BNX_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8) 2120 #define BNX_CTX_COMMAND_MEM_INIT (1L<<13) 2121 #define BNX_CTX_COMMAND_PAGE_SIZE (0xfL<<16) 2122 #define BNX_CTX_COMMAND_PAGE_SIZE_256 (0L<<16) 2123 #define BNX_CTX_COMMAND_PAGE_SIZE_512 (1L<<16) 2124 #define BNX_CTX_COMMAND_PAGE_SIZE_1K (2L<<16) 2125 #define BNX_CTX_COMMAND_PAGE_SIZE_2K (3L<<16) 2126 #define BNX_CTX_COMMAND_PAGE_SIZE_4K (4L<<16) 2127 #define BNX_CTX_COMMAND_PAGE_SIZE_8K (5L<<16) 2128 #define BNX_CTX_COMMAND_PAGE_SIZE_16K (6L<<16) 2129 #define BNX_CTX_COMMAND_PAGE_SIZE_32K (7L<<16) 2130 #define BNX_CTX_COMMAND_PAGE_SIZE_64K (8L<<16) 2131 #define BNX_CTX_COMMAND_PAGE_SIZE_128K (9L<<16) 2132 #define BNX_CTX_COMMAND_PAGE_SIZE_256K (10L<<16) 2133 #define BNX_CTX_COMMAND_PAGE_SIZE_512K (11L<<16) 2134 #define BNX_CTX_COMMAND_PAGE_SIZE_1M (12L<<16) 2135 2136 #define BNX_CTX_STATUS 0x00001004 2137 #define BNX_CTX_STATUS_LOCK_WAIT (1L<<0) 2138 #define BNX_CTX_STATUS_READ_STAT (1L<<16) 2139 #define BNX_CTX_STATUS_WRITE_STAT (1L<<17) 2140 #define BNX_CTX_STATUS_ACC_STALL_STAT (1L<<18) 2141 #define BNX_CTX_STATUS_LOCK_STALL_STAT (1L<<19) 2142 2143 #define BNX_CTX_VIRT_ADDR 0x00001008 2144 #define BNX_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) 2145 2146 #define BNX_CTX_PAGE_TBL 0x0000100c 2147 #define BNX_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) 2148 2149 #define BNX_CTX_DATA_ADR 0x00001010 2150 #define BNX_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) 2151 2152 #define BNX_CTX_DATA 0x00001014 2153 #define BNX_CTX_LOCK 0x00001018 2154 #define BNX_CTX_LOCK_TYPE (0x7L<<0) 2155 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0) 2156 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0) 2157 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0) 2158 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) 2159 #define BNX_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0) 2160 #define BNX_CTX_LOCK_CID_VALUE (0x3fffL<<7) 2161 #define BNX_CTX_LOCK_GRANTED (1L<<26) 2162 #define BNX_CTX_LOCK_MODE (0x7L<<27) 2163 #define BNX_CTX_LOCK_MODE_UNLOCK (0x0L<<27) 2164 #define BNX_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) 2165 #define BNX_CTX_LOCK_MODE_SURE (0x2L<<27) 2166 #define BNX_CTX_LOCK_STATUS (1L<<30) 2167 #define BNX_CTX_LOCK_REQ (1L<<31) 2168 2169 #define BNX_CTX_CTX_CTRL 0x0000101c 2170 #define BNX_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2) 2171 #define BNX_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21) 2172 #define BNX_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23) 2173 #define BNX_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24) 2174 #define BNX_CTX_CTX_CTRL_ATTR (1L<<26) 2175 #define BNX_CTX_CTX_CTRL_WRITE_REQ (1L<<30) 2176 #define BNX_CTX_CTX_CTRL_READ_REQ (1L<<31) 2177 2178 #define BNX_CTX_CTX_DATA 0x00001020 2179 2180 #define BNX_CTX_ACCESS_STATUS 0x00001040 2181 #define BNX_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0) 2182 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10) 2183 #define BNX_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12) 2184 #define BNX_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14) 2185 #define BNX_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17) 2186 #define BNX_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0) 2187 #define BNX_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5) 2188 #define BNX_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10) 2189 2190 #define BNX_CTX_DBG_LOCK_STATUS 0x00001044 2191 #define BNX_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) 2192 #define BNX_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) 2193 2194 #define BNX_CTX_CHNL_LOCK_STATUS_0 0x00001080 2195 #define BNX_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) 2196 #define BNX_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14) 2197 #define BNX_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16) 2198 2199 #define BNX_CTX_CHNL_LOCK_STATUS_1 0x00001084 2200 #define BNX_CTX_CHNL_LOCK_STATUS_2 0x00001088 2201 #define BNX_CTX_CHNL_LOCK_STATUS_3 0x0000108c 2202 #define BNX_CTX_CHNL_LOCK_STATUS_4 0x00001090 2203 #define BNX_CTX_CHNL_LOCK_STATUS_5 0x00001094 2204 #define BNX_CTX_CHNL_LOCK_STATUS_6 0x00001098 2205 #define BNX_CTX_CHNL_LOCK_STATUS_7 0x0000109c 2206 #define BNX_CTX_CHNL_LOCK_STATUS_8 0x000010a0 2207 2208 #define BNX_CTX_CACHE_DATA 0x000010c4 2209 #define BNX_CTX_HOST_PAGE_TBL_CTRL 0x000010c8 2210 #define BNX_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0) 2211 #define BNX_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30) 2212 #define BNX_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31) 2213 2214 #define BNX_CTX_HOST_PAGE_TBL_DATA0 0x000010cc 2215 #define BNX_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0) 2216 #define BNX_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8) 2217 2218 #define BNX_CTX_HOST_PAGE_TBL_DATA1 0x000010d0 2219 2220 /* 2221 * emac_reg definition 2222 * offset: 0x1400 2223 */ 2224 #define BNX_EMAC_MODE 0x00001400 2225 #define BNX_EMAC_MODE_RESET (1L<<0) 2226 #define BNX_EMAC_MODE_HALF_DUPLEX (1L<<1) 2227 #define BNX_EMAC_MODE_PORT (0x3L<<2) 2228 #define BNX_EMAC_MODE_PORT_NONE (0L<<2) 2229 #define BNX_EMAC_MODE_PORT_MII (1L<<2) 2230 #define BNX_EMAC_MODE_PORT_GMII (2L<<2) 2231 #define BNX_EMAC_MODE_PORT_MII_10 (3L<<2) 2232 #define BNX_EMAC_MODE_MAC_LOOP (1L<<4) 2233 #define BNX_EMAC_MODE_25G (1L<<5) 2234 #define BNX_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) 2235 #define BNX_EMAC_MODE_TX_BURST (1L<<8) 2236 #define BNX_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9) 2237 #define BNX_EMAC_MODE_EXT_LINK_POL (1L<<10) 2238 #define BNX_EMAC_MODE_FORCE_LINK (1L<<11) 2239 #define BNX_EMAC_MODE_MPKT (1L<<18) 2240 #define BNX_EMAC_MODE_MPKT_RCVD (1L<<19) 2241 #define BNX_EMAC_MODE_ACPI_RCVD (1L<<20) 2242 2243 #define BNX_EMAC_STATUS 0x00001404 2244 #define BNX_EMAC_STATUS_LINK (1L<<11) 2245 #define BNX_EMAC_STATUS_LINK_CHANGE (1L<<12) 2246 #define BNX_EMAC_STATUS_MI_COMPLETE (1L<<22) 2247 #define BNX_EMAC_STATUS_MI_INT (1L<<23) 2248 #define BNX_EMAC_STATUS_AP_ERROR (1L<<24) 2249 #define BNX_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31) 2250 2251 #define BNX_EMAC_ATTENTION_ENA 0x00001408 2252 #define BNX_EMAC_ATTENTION_ENA_LINK (1L<<11) 2253 #define BNX_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22) 2254 #define BNX_EMAC_ATTENTION_ENA_MI_INT (1L<<23) 2255 #define BNX_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24) 2256 2257 #define BNX_EMAC_LED 0x0000140c 2258 #define BNX_EMAC_LED_OVERRIDE (1L<<0) 2259 #define BNX_EMAC_LED_1000MB_OVERRIDE (1L<<1) 2260 #define BNX_EMAC_LED_100MB_OVERRIDE (1L<<2) 2261 #define BNX_EMAC_LED_10MB_OVERRIDE (1L<<3) 2262 #define BNX_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) 2263 #define BNX_EMAC_LED_BLNK_TRAFFIC (1L<<5) 2264 #define BNX_EMAC_LED_TRAFFIC (1L<<6) 2265 #define BNX_EMAC_LED_1000MB (1L<<7) 2266 #define BNX_EMAC_LED_100MB (1L<<8) 2267 #define BNX_EMAC_LED_10MB (1L<<9) 2268 #define BNX_EMAC_LED_TRAFFIC_STAT (1L<<10) 2269 #define BNX_EMAC_LED_BLNK_RATE (0xfffL<<19) 2270 #define BNX_EMAC_LED_BLNK_RATE_ENA (1L<<31) 2271 2272 #define BNX_EMAC_MAC_MATCH0 0x00001410 2273 #define BNX_EMAC_MAC_MATCH1 0x00001414 2274 #define BNX_EMAC_MAC_MATCH2 0x00001418 2275 #define BNX_EMAC_MAC_MATCH3 0x0000141c 2276 #define BNX_EMAC_MAC_MATCH4 0x00001420 2277 #define BNX_EMAC_MAC_MATCH5 0x00001424 2278 #define BNX_EMAC_MAC_MATCH6 0x00001428 2279 #define BNX_EMAC_MAC_MATCH7 0x0000142c 2280 #define BNX_EMAC_MAC_MATCH8 0x00001430 2281 #define BNX_EMAC_MAC_MATCH9 0x00001434 2282 #define BNX_EMAC_MAC_MATCH10 0x00001438 2283 #define BNX_EMAC_MAC_MATCH11 0x0000143c 2284 #define BNX_EMAC_MAC_MATCH12 0x00001440 2285 #define BNX_EMAC_MAC_MATCH13 0x00001444 2286 #define BNX_EMAC_MAC_MATCH14 0x00001448 2287 #define BNX_EMAC_MAC_MATCH15 0x0000144c 2288 #define BNX_EMAC_MAC_MATCH16 0x00001450 2289 #define BNX_EMAC_MAC_MATCH17 0x00001454 2290 #define BNX_EMAC_MAC_MATCH18 0x00001458 2291 #define BNX_EMAC_MAC_MATCH19 0x0000145c 2292 #define BNX_EMAC_MAC_MATCH20 0x00001460 2293 #define BNX_EMAC_MAC_MATCH21 0x00001464 2294 #define BNX_EMAC_MAC_MATCH22 0x00001468 2295 #define BNX_EMAC_MAC_MATCH23 0x0000146c 2296 #define BNX_EMAC_MAC_MATCH24 0x00001470 2297 #define BNX_EMAC_MAC_MATCH25 0x00001474 2298 #define BNX_EMAC_MAC_MATCH26 0x00001478 2299 #define BNX_EMAC_MAC_MATCH27 0x0000147c 2300 #define BNX_EMAC_MAC_MATCH28 0x00001480 2301 #define BNX_EMAC_MAC_MATCH29 0x00001484 2302 #define BNX_EMAC_MAC_MATCH30 0x00001488 2303 #define BNX_EMAC_MAC_MATCH31 0x0000148c 2304 #define BNX_EMAC_BACKOFF_SEED 0x00001498 2305 #define BNX_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0) 2306 2307 #define BNX_EMAC_RX_MTU_SIZE 0x0000149c 2308 #define BNX_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) 2309 #define BNX_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 2310 2311 #define BNX_EMAC_SERDES_CNTL 0x000014a4 2312 #define BNX_EMAC_SERDES_CNTL_RXR (0x7L<<0) 2313 #define BNX_EMAC_SERDES_CNTL_RXG (0x3L<<3) 2314 #define BNX_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) 2315 #define BNX_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) 2316 #define BNX_EMAC_SERDES_CNTL_BGMAX (1L<<10) 2317 #define BNX_EMAC_SERDES_CNTL_BGMIN (1L<<11) 2318 #define BNX_EMAC_SERDES_CNTL_TXMODE (1L<<12) 2319 #define BNX_EMAC_SERDES_CNTL_TXEDGE (1L<<13) 2320 #define BNX_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14) 2321 #define BNX_EMAC_SERDES_CNTL_PLLTEST (1L<<15) 2322 #define BNX_EMAC_SERDES_CNTL_CDET_EN (1L<<16) 2323 #define BNX_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) 2324 #define BNX_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18) 2325 #define BNX_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) 2326 #define BNX_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) 2327 #define BNX_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) 2328 2329 #define BNX_EMAC_SERDES_STATUS 0x000014a8 2330 #define BNX_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) 2331 #define BNX_EMAC_SERDES_STATUS_COMMA_DET (1L<<8) 2332 2333 #define BNX_EMAC_MDIO_COMM 0x000014ac 2334 #define BNX_EMAC_MDIO_COMM_DATA (0xffffL<<0) 2335 #define BNX_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) 2336 #define BNX_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) 2337 #define BNX_EMAC_MDIO_COMM_COMMAND (0x3L<<26) 2338 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26) 2339 #define BNX_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26) 2340 #define BNX_EMAC_MDIO_COMM_COMMAND_READ (2L<<26) 2341 #define BNX_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26) 2342 #define BNX_EMAC_MDIO_COMM_FAIL (1L<<28) 2343 #define BNX_EMAC_MDIO_COMM_START_BUSY (1L<<29) 2344 #define BNX_EMAC_MDIO_COMM_DISEXT (1L<<30) 2345 2346 #define BNX_EMAC_MDIO_STATUS 0x000014b0 2347 #define BNX_EMAC_MDIO_STATUS_LINK (1L<<0) 2348 #define BNX_EMAC_MDIO_STATUS_10MB (1L<<1) 2349 2350 #define BNX_EMAC_MDIO_MODE 0x000014b4 2351 #define BNX_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1) 2352 #define BNX_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 2353 #define BNX_EMAC_MDIO_MODE_BIT_BANG (1L<<8) 2354 #define BNX_EMAC_MDIO_MODE_MDIO (1L<<9) 2355 #define BNX_EMAC_MDIO_MODE_MDIO_OE (1L<<10) 2356 #define BNX_EMAC_MDIO_MODE_MDC (1L<<11) 2357 #define BNX_EMAC_MDIO_MODE_MDINT (1L<<12) 2358 #define BNX_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) 2359 2360 #define BNX_EMAC_MDIO_AUTO_STATUS 0x000014b8 2361 #define BNX_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0) 2362 2363 #define BNX_EMAC_TX_MODE 0x000014bc 2364 #define BNX_EMAC_TX_MODE_RESET (1L<<0) 2365 #define BNX_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 2366 #define BNX_EMAC_TX_MODE_FLOW_EN (1L<<4) 2367 #define BNX_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) 2368 #define BNX_EMAC_TX_MODE_LONG_PAUSE (1L<<6) 2369 #define BNX_EMAC_TX_MODE_LINK_AWARE (1L<<7) 2370 2371 #define BNX_EMAC_TX_STATUS 0x000014c0 2372 #define BNX_EMAC_TX_STATUS_XOFFED (1L<<0) 2373 #define BNX_EMAC_TX_STATUS_XOFF_SENT (1L<<1) 2374 #define BNX_EMAC_TX_STATUS_XON_SENT (1L<<2) 2375 #define BNX_EMAC_TX_STATUS_LINK_UP (1L<<3) 2376 #define BNX_EMAC_TX_STATUS_UNDERRUN (1L<<4) 2377 2378 #define BNX_EMAC_TX_LENGTHS 0x000014c4 2379 #define BNX_EMAC_TX_LENGTHS_SLOT (0xffL<<0) 2380 #define BNX_EMAC_TX_LENGTHS_IPG (0xfL<<8) 2381 #define BNX_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) 2382 2383 #define BNX_EMAC_RX_MODE 0x000014c8 2384 #define BNX_EMAC_RX_MODE_RESET (1L<<0) 2385 #define BNX_EMAC_RX_MODE_FLOW_EN (1L<<2) 2386 #define BNX_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 2387 #define BNX_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) 2388 #define BNX_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5) 2389 #define BNX_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) 2390 #define BNX_EMAC_RX_MODE_LLC_CHK (1L<<7) 2391 #define BNX_EMAC_RX_MODE_PROMISCUOUS (1L<<8) 2392 #define BNX_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) 2393 #define BNX_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 2394 #define BNX_EMAC_RX_MODE_FILT_BROADCAST (1L<<11) 2395 #define BNX_EMAC_RX_MODE_SORT_MODE (1L<<12) 2396 2397 #define BNX_EMAC_RX_STATUS 0x000014cc 2398 #define BNX_EMAC_RX_STATUS_FFED (1L<<0) 2399 #define BNX_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) 2400 #define BNX_EMAC_RX_STATUS_N_RECEIVED (1L<<2) 2401 2402 #define BNX_EMAC_MULTICAST_HASH0 0x000014d0 2403 #define BNX_EMAC_MULTICAST_HASH1 0x000014d4 2404 #define BNX_EMAC_MULTICAST_HASH2 0x000014d8 2405 #define BNX_EMAC_MULTICAST_HASH3 0x000014dc 2406 #define BNX_EMAC_MULTICAST_HASH4 0x000014e0 2407 #define BNX_EMAC_MULTICAST_HASH5 0x000014e4 2408 #define BNX_EMAC_MULTICAST_HASH6 0x000014e8 2409 #define BNX_EMAC_MULTICAST_HASH7 0x000014ec 2410 #define BNX_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 2411 #define BNX_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504 2412 #define BNX_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508 2413 #define BNX_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c 2414 #define BNX_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510 2415 #define BNX_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514 2416 #define BNX_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518 2417 #define BNX_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c 2418 #define BNX_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520 2419 #define BNX_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524 2420 #define BNX_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528 2421 #define BNX_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c 2422 #define BNX_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530 2423 #define BNX_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534 2424 #define BNX_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538 2425 #define BNX_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c 2426 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540 2427 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544 2428 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548 2429 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c 2430 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550 2431 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554 2432 #define BNX_EMAC_RX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001558 2433 #define BNX_EMAC_RXMAC_DEBUG0 0x0000155c 2434 #define BNX_EMAC_RXMAC_DEBUG1 0x00001560 2435 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0) 2436 #define BNX_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1) 2437 #define BNX_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) 2438 #define BNX_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) 2439 #define BNX_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4) 2440 #define BNX_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5) 2441 #define BNX_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6) 2442 #define BNX_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7) 2443 #define BNX_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23) 2444 2445 #define BNX_EMAC_RXMAC_DEBUG2 0x00001564 2446 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) 2447 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0) 2448 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0) 2449 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0) 2450 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0) 2451 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0) 2452 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0) 2453 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0) 2454 #define BNX_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0) 2455 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3) 2456 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3) 2457 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3) 2458 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3) 2459 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3) 2460 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3) 2461 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3) 2462 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3) 2463 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3) 2464 #define BNX_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3) 2465 #define BNX_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) 2466 #define BNX_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) 2467 #define BNX_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) 2468 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18) 2469 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18) 2470 #define BNX_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18) 2471 #define BNX_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19) 2472 #define BNX_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) 2473 2474 #define BNX_EMAC_RXMAC_DEBUG3 0x00001568 2475 #define BNX_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0) 2476 #define BNX_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16) 2477 2478 #define BNX_EMAC_RXMAC_DEBUG4 0x0000156c 2479 #define BNX_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0) 2480 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16) 2481 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16) 2482 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16) 2483 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16) 2484 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16) 2485 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16) 2486 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16) 2487 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16) 2488 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16) 2489 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16) 2490 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16) 2491 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16) 2492 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16) 2493 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16) 2494 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16) 2495 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16) 2496 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16) 2497 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16) 2498 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16) 2499 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16) 2500 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16) 2501 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16) 2502 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16) 2503 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16) 2504 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16) 2505 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16) 2506 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16) 2507 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16) 2508 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16) 2509 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16) 2510 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16) 2511 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16) 2512 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16) 2513 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16) 2514 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16) 2515 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16) 2516 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16) 2517 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16) 2518 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16) 2519 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16) 2520 #define BNX_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16) 2521 #define BNX_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) 2522 #define BNX_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23) 2523 #define BNX_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24) 2524 #define BNX_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25) 2525 #define BNX_EMAC_RXMAC_DEBUG4_sfd_FOUND (1L<<26) 2526 #define BNX_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) 2527 #define BNX_EMAC_RXMAC_DEBUG4_START (1L<<28) 2528 2529 #define BNX_EMAC_RXMAC_DEBUG5 0x00001570 2530 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) 2531 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0) 2532 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0) 2533 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0) 2534 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0) 2535 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0) 2536 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0) 2537 #define BNX_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0) 2538 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4) 2539 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4) 2540 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4) 2541 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4) 2542 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4) 2543 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4) 2544 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4) 2545 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4) 2546 #define BNX_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7) 2547 #define BNX_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8) 2548 #define BNX_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11) 2549 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12) 2550 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13) 2551 #define BNX_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14) 2552 #define BNX_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) 2553 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16) 2554 #define BNX_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19) 2555 #define BNX_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) 2556 2557 #define BNX_EMAC_RX_STAT_AC0 0x00001580 2558 #define BNX_EMAC_RX_STAT_AC1 0x00001584 2559 #define BNX_EMAC_RX_STAT_AC2 0x00001588 2560 #define BNX_EMAC_RX_STAT_AC3 0x0000158c 2561 #define BNX_EMAC_RX_STAT_AC4 0x00001590 2562 #define BNX_EMAC_RX_STAT_AC5 0x00001594 2563 #define BNX_EMAC_RX_STAT_AC6 0x00001598 2564 #define BNX_EMAC_RX_STAT_AC7 0x0000159c 2565 #define BNX_EMAC_RX_STAT_AC8 0x000015a0 2566 #define BNX_EMAC_RX_STAT_AC9 0x000015a4 2567 #define BNX_EMAC_RX_STAT_AC10 0x000015a8 2568 #define BNX_EMAC_RX_STAT_AC11 0x000015ac 2569 #define BNX_EMAC_RX_STAT_AC12 0x000015b0 2570 #define BNX_EMAC_RX_STAT_AC13 0x000015b4 2571 #define BNX_EMAC_RX_STAT_AC14 0x000015b8 2572 #define BNX_EMAC_RX_STAT_AC15 0x000015bc 2573 #define BNX_EMAC_RX_STAT_AC16 0x000015c0 2574 #define BNX_EMAC_RX_STAT_AC17 0x000015c4 2575 #define BNX_EMAC_RX_STAT_AC18 0x000015c8 2576 #define BNX_EMAC_RX_STAT_AC19 0x000015cc 2577 #define BNX_EMAC_RX_STAT_AC20 0x000015d0 2578 #define BNX_EMAC_RX_STAT_AC21 0x000015d4 2579 #define BNX_EMAC_RX_STAT_AC22 0x000015d8 2580 #define BNX_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc 2581 #define BNX_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 2582 #define BNX_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604 2583 #define BNX_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608 2584 #define BNX_EMAC_TX_STAT_OUTXONSENT 0x0000160c 2585 #define BNX_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 2586 #define BNX_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614 2587 #define BNX_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618 2588 #define BNX_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c 2589 #define BNX_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620 2590 #define BNX_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624 2591 #define BNX_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628 2592 #define BNX_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c 2593 #define BNX_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630 2594 #define BNX_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634 2595 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638 2596 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c 2597 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640 2598 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644 2599 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648 2600 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c 2601 #define BNX_EMAC_TX_STAT_ETHERSTATSPKTS1523OCTETSTO9022OCTETS 0x00001650 2602 #define BNX_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654 2603 #define BNX_EMAC_TXMAC_DEBUG0 0x00001658 2604 #define BNX_EMAC_TXMAC_DEBUG1 0x0000165c 2605 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0) 2606 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0) 2607 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0) 2608 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0) 2609 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0) 2610 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0) 2611 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0) 2612 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0) 2613 #define BNX_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0) 2614 #define BNX_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4) 2615 #define BNX_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) 2616 #define BNX_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6) 2617 #define BNX_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10) 2618 #define BNX_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11) 2619 #define BNX_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12) 2620 #define BNX_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) 2621 #define BNX_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) 2622 #define BNX_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) 2623 #define BNX_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19) 2624 2625 #define BNX_EMAC_TXMAC_DEBUG2 0x00001660 2626 #define BNX_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) 2627 #define BNX_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10) 2628 #define BNX_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26) 2629 #define BNX_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) 2630 2631 #define BNX_EMAC_TXMAC_DEBUG3 0x00001664 2632 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) 2633 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0) 2634 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0) 2635 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0) 2636 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0) 2637 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0) 2638 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0) 2639 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0) 2640 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0) 2641 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0) 2642 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0) 2643 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0) 2644 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0) 2645 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0) 2646 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0) 2647 #define BNX_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0) 2648 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4) 2649 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4) 2650 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4) 2651 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4) 2652 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4) 2653 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4) 2654 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4) 2655 #define BNX_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4) 2656 #define BNX_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) 2657 #define BNX_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) 2658 #define BNX_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9) 2659 #define BNX_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13) 2660 2661 #define BNX_EMAC_TXMAC_DEBUG4 0x00001668 2662 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0) 2663 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16) 2664 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16) 2665 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16) 2666 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16) 2667 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16) 2668 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16) 2669 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16) 2670 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16) 2671 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16) 2672 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16) 2673 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16) 2674 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16) 2675 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16) 2676 #define BNX_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16) 2677 #define BNX_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20) 2678 #define BNX_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21) 2679 #define BNX_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22) 2680 #define BNX_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23) 2681 #define BNX_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24) 2682 #define BNX_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25) 2683 #define BNX_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) 2684 #define BNX_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27) 2685 #define BNX_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) 2686 #define BNX_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) 2687 #define BNX_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) 2688 #define BNX_EMAC_TXMAC_DEBUG4_GO (1L<<31) 2689 2690 #define BNX_EMAC_TX_STAT_AC0 0x00001680 2691 #define BNX_EMAC_TX_STAT_AC1 0x00001684 2692 #define BNX_EMAC_TX_STAT_AC2 0x00001688 2693 #define BNX_EMAC_TX_STAT_AC3 0x0000168c 2694 #define BNX_EMAC_TX_STAT_AC4 0x00001690 2695 #define BNX_EMAC_TX_STAT_AC5 0x00001694 2696 #define BNX_EMAC_TX_STAT_AC6 0x00001698 2697 #define BNX_EMAC_TX_STAT_AC7 0x0000169c 2698 #define BNX_EMAC_TX_STAT_AC8 0x000016a0 2699 #define BNX_EMAC_TX_STAT_AC9 0x000016a4 2700 #define BNX_EMAC_TX_STAT_AC10 0x000016a8 2701 #define BNX_EMAC_TX_STAT_AC11 0x000016ac 2702 #define BNX_EMAC_TX_STAT_AC12 0x000016b0 2703 #define BNX_EMAC_TX_STAT_AC13 0x000016b4 2704 #define BNX_EMAC_TX_STAT_AC14 0x000016b8 2705 #define BNX_EMAC_TX_STAT_AC15 0x000016bc 2706 #define BNX_EMAC_TX_STAT_AC16 0x000016c0 2707 #define BNX_EMAC_TX_STAT_AC17 0x000016c4 2708 #define BNX_EMAC_TX_STAT_AC18 0x000016c8 2709 #define BNX_EMAC_TX_STAT_AC19 0x000016cc 2710 #define BNX_EMAC_TX_STAT_AC20 0x000016d0 2711 #define BNX_EMAC_TX_STAT_AC21 0x000016d4 2712 #define BNX_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8 2713 2714 2715 /* 2716 * rpm_reg definition 2717 * offset: 0x1800 2718 */ 2719 #define BNX_RPM_COMMAND 0x00001800 2720 #define BNX_RPM_COMMAND_ENABLED (1L<<0) 2721 #define BNX_RPM_COMMAND_OVERRUN_ABORT (1L<<4) 2722 2723 #define BNX_RPM_STATUS 0x00001804 2724 #define BNX_RPM_STATUS_MBUF_WAIT (1L<<0) 2725 #define BNX_RPM_STATUS_FREE_WAIT (1L<<1) 2726 2727 #define BNX_RPM_CONFIG 0x00001808 2728 #define BNX_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0) 2729 #define BNX_RPM_CONFIG_ACPI_ENA (1L<<1) 2730 #define BNX_RPM_CONFIG_ACPI_KEEP (1L<<2) 2731 #define BNX_RPM_CONFIG_MP_KEEP (1L<<3) 2732 #define BNX_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) 2733 #define BNX_RPM_CONFIG_IGNORE_VLAN (1L<<31) 2734 2735 #define BNX_RPM_VLAN_MATCH0 0x00001810 2736 #define BNX_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0) 2737 2738 #define BNX_RPM_VLAN_MATCH1 0x00001814 2739 #define BNX_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0) 2740 2741 #define BNX_RPM_VLAN_MATCH2 0x00001818 2742 #define BNX_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0) 2743 2744 #define BNX_RPM_VLAN_MATCH3 0x0000181c 2745 #define BNX_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0) 2746 2747 #define BNX_RPM_SORT_USER0 0x00001820 2748 #define BNX_RPM_SORT_USER0_PM_EN (0xffffL<<0) 2749 #define BNX_RPM_SORT_USER0_BC_EN (1L<<16) 2750 #define BNX_RPM_SORT_USER0_MC_EN (1L<<17) 2751 #define BNX_RPM_SORT_USER0_MC_HSH_EN (1L<<18) 2752 #define BNX_RPM_SORT_USER0_PROM_EN (1L<<19) 2753 #define BNX_RPM_SORT_USER0_VLAN_EN (0xfL<<20) 2754 #define BNX_RPM_SORT_USER0_PROM_VLAN (1L<<24) 2755 #define BNX_RPM_SORT_USER0_ENA (1L<<31) 2756 2757 #define BNX_RPM_SORT_USER1 0x00001824 2758 #define BNX_RPM_SORT_USER1_PM_EN (0xffffL<<0) 2759 #define BNX_RPM_SORT_USER1_BC_EN (1L<<16) 2760 #define BNX_RPM_SORT_USER1_MC_EN (1L<<17) 2761 #define BNX_RPM_SORT_USER1_MC_HSH_EN (1L<<18) 2762 #define BNX_RPM_SORT_USER1_PROM_EN (1L<<19) 2763 #define BNX_RPM_SORT_USER1_VLAN_EN (0xfL<<20) 2764 #define BNX_RPM_SORT_USER1_PROM_VLAN (1L<<24) 2765 #define BNX_RPM_SORT_USER1_ENA (1L<<31) 2766 2767 #define BNX_RPM_SORT_USER2 0x00001828 2768 #define BNX_RPM_SORT_USER2_PM_EN (0xffffL<<0) 2769 #define BNX_RPM_SORT_USER2_BC_EN (1L<<16) 2770 #define BNX_RPM_SORT_USER2_MC_EN (1L<<17) 2771 #define BNX_RPM_SORT_USER2_MC_HSH_EN (1L<<18) 2772 #define BNX_RPM_SORT_USER2_PROM_EN (1L<<19) 2773 #define BNX_RPM_SORT_USER2_VLAN_EN (0xfL<<20) 2774 #define BNX_RPM_SORT_USER2_PROM_VLAN (1L<<24) 2775 #define BNX_RPM_SORT_USER2_ENA (1L<<31) 2776 2777 #define BNX_RPM_SORT_USER3 0x0000182c 2778 #define BNX_RPM_SORT_USER3_PM_EN (0xffffL<<0) 2779 #define BNX_RPM_SORT_USER3_BC_EN (1L<<16) 2780 #define BNX_RPM_SORT_USER3_MC_EN (1L<<17) 2781 #define BNX_RPM_SORT_USER3_MC_HSH_EN (1L<<18) 2782 #define BNX_RPM_SORT_USER3_PROM_EN (1L<<19) 2783 #define BNX_RPM_SORT_USER3_VLAN_EN (0xfL<<20) 2784 #define BNX_RPM_SORT_USER3_PROM_VLAN (1L<<24) 2785 #define BNX_RPM_SORT_USER3_ENA (1L<<31) 2786 2787 #define BNX_RPM_STAT_L2_FILTER_DISCARDS 0x00001840 2788 #define BNX_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844 2789 #define BNX_RPM_STAT_IFINFTQDISCARDS 0x00001848 2790 #define BNX_RPM_STAT_IFINMBUFDISCARD 0x0000184c 2791 #define BNX_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850 2792 #define BNX_RPM_STAT_AC0 0x00001880 2793 #define BNX_RPM_STAT_AC1 0x00001884 2794 #define BNX_RPM_STAT_AC2 0x00001888 2795 #define BNX_RPM_STAT_AC3 0x0000188c 2796 #define BNX_RPM_STAT_AC4 0x00001890 2797 #define BNX_RPM_RC_CNTL_0 0x00001900 2798 #define BNX_RPM_RC_CNTL_0_OFFSET (0xffL<<0) 2799 #define BNX_RPM_RC_CNTL_0_CLASS (0x7L<<8) 2800 #define BNX_RPM_RC_CNTL_0_PRIORITY (1L<<11) 2801 #define BNX_RPM_RC_CNTL_0_P4 (1L<<12) 2802 #define BNX_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) 2803 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13) 2804 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) 2805 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) 2806 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) 2807 #define BNX_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13) 2808 #define BNX_RPM_RC_CNTL_0_COMP (0x3L<<16) 2809 #define BNX_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) 2810 #define BNX_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) 2811 #define BNX_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) 2812 #define BNX_RPM_RC_CNTL_0_COMP_LESS (3L<<16) 2813 #define BNX_RPM_RC_CNTL_0_SBIT (1L<<19) 2814 #define BNX_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) 2815 #define BNX_RPM_RC_CNTL_0_MAP (1L<<24) 2816 #define BNX_RPM_RC_CNTL_0_DISCARD (1L<<25) 2817 #define BNX_RPM_RC_CNTL_0_MASK (1L<<26) 2818 #define BNX_RPM_RC_CNTL_0_P1 (1L<<27) 2819 #define BNX_RPM_RC_CNTL_0_P2 (1L<<28) 2820 #define BNX_RPM_RC_CNTL_0_P3 (1L<<29) 2821 #define BNX_RPM_RC_CNTL_0_NBIT (1L<<30) 2822 2823 #define BNX_RPM_RC_VALUE_MASK_0 0x00001904 2824 #define BNX_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) 2825 #define BNX_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) 2826 2827 #define BNX_RPM_RC_CNTL_1 0x00001908 2828 #define BNX_RPM_RC_CNTL_1_A (0x3ffffL<<0) 2829 #define BNX_RPM_RC_CNTL_1_B (0xfffL<<19) 2830 2831 #define BNX_RPM_RC_VALUE_MASK_1 0x0000190c 2832 #define BNX_RPM_RC_CNTL_2 0x00001910 2833 #define BNX_RPM_RC_CNTL_2_A (0x3ffffL<<0) 2834 #define BNX_RPM_RC_CNTL_2_B (0xfffL<<19) 2835 2836 #define BNX_RPM_RC_VALUE_MASK_2 0x00001914 2837 #define BNX_RPM_RC_CNTL_3 0x00001918 2838 #define BNX_RPM_RC_CNTL_3_A (0x3ffffL<<0) 2839 #define BNX_RPM_RC_CNTL_3_B (0xfffL<<19) 2840 2841 #define BNX_RPM_RC_VALUE_MASK_3 0x0000191c 2842 #define BNX_RPM_RC_CNTL_4 0x00001920 2843 #define BNX_RPM_RC_CNTL_4_A (0x3ffffL<<0) 2844 #define BNX_RPM_RC_CNTL_4_B (0xfffL<<19) 2845 2846 #define BNX_RPM_RC_VALUE_MASK_4 0x00001924 2847 #define BNX_RPM_RC_CNTL_5 0x00001928 2848 #define BNX_RPM_RC_CNTL_5_A (0x3ffffL<<0) 2849 #define BNX_RPM_RC_CNTL_5_B (0xfffL<<19) 2850 2851 #define BNX_RPM_RC_VALUE_MASK_5 0x0000192c 2852 #define BNX_RPM_RC_CNTL_6 0x00001930 2853 #define BNX_RPM_RC_CNTL_6_A (0x3ffffL<<0) 2854 #define BNX_RPM_RC_CNTL_6_B (0xfffL<<19) 2855 2856 #define BNX_RPM_RC_VALUE_MASK_6 0x00001934 2857 #define BNX_RPM_RC_CNTL_7 0x00001938 2858 #define BNX_RPM_RC_CNTL_7_A (0x3ffffL<<0) 2859 #define BNX_RPM_RC_CNTL_7_B (0xfffL<<19) 2860 2861 #define BNX_RPM_RC_VALUE_MASK_7 0x0000193c 2862 #define BNX_RPM_RC_CNTL_8 0x00001940 2863 #define BNX_RPM_RC_CNTL_8_A (0x3ffffL<<0) 2864 #define BNX_RPM_RC_CNTL_8_B (0xfffL<<19) 2865 2866 #define BNX_RPM_RC_VALUE_MASK_8 0x00001944 2867 #define BNX_RPM_RC_CNTL_9 0x00001948 2868 #define BNX_RPM_RC_CNTL_9_A (0x3ffffL<<0) 2869 #define BNX_RPM_RC_CNTL_9_B (0xfffL<<19) 2870 2871 #define BNX_RPM_RC_VALUE_MASK_9 0x0000194c 2872 #define BNX_RPM_RC_CNTL_10 0x00001950 2873 #define BNX_RPM_RC_CNTL_10_A (0x3ffffL<<0) 2874 #define BNX_RPM_RC_CNTL_10_B (0xfffL<<19) 2875 2876 #define BNX_RPM_RC_VALUE_MASK_10 0x00001954 2877 #define BNX_RPM_RC_CNTL_11 0x00001958 2878 #define BNX_RPM_RC_CNTL_11_A (0x3ffffL<<0) 2879 #define BNX_RPM_RC_CNTL_11_B (0xfffL<<19) 2880 2881 #define BNX_RPM_RC_VALUE_MASK_11 0x0000195c 2882 #define BNX_RPM_RC_CNTL_12 0x00001960 2883 #define BNX_RPM_RC_CNTL_12_A (0x3ffffL<<0) 2884 #define BNX_RPM_RC_CNTL_12_B (0xfffL<<19) 2885 2886 #define BNX_RPM_RC_VALUE_MASK_12 0x00001964 2887 #define BNX_RPM_RC_CNTL_13 0x00001968 2888 #define BNX_RPM_RC_CNTL_13_A (0x3ffffL<<0) 2889 #define BNX_RPM_RC_CNTL_13_B (0xfffL<<19) 2890 2891 #define BNX_RPM_RC_VALUE_MASK_13 0x0000196c 2892 #define BNX_RPM_RC_CNTL_14 0x00001970 2893 #define BNX_RPM_RC_CNTL_14_A (0x3ffffL<<0) 2894 #define BNX_RPM_RC_CNTL_14_B (0xfffL<<19) 2895 2896 #define BNX_RPM_RC_VALUE_MASK_14 0x00001974 2897 #define BNX_RPM_RC_CNTL_15 0x00001978 2898 #define BNX_RPM_RC_CNTL_15_A (0x3ffffL<<0) 2899 #define BNX_RPM_RC_CNTL_15_B (0xfffL<<19) 2900 2901 #define BNX_RPM_RC_VALUE_MASK_15 0x0000197c 2902 #define BNX_RPM_RC_CONFIG 0x00001980 2903 #define BNX_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) 2904 #define BNX_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) 2905 2906 #define BNX_RPM_DEBUG0 0x00001984 2907 #define BNX_RPM_DEBUG0_FM_BCNT (0xffffL<<0) 2908 #define BNX_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) 2909 #define BNX_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) 2910 #define BNX_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) 2911 #define BNX_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) 2912 #define BNX_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) 2913 #define BNX_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21) 2914 #define BNX_RPM_DEBUG0_LLC_SNAP (1L<<22) 2915 #define BNX_RPM_DEBUG0_FM_STARTED (1L<<23) 2916 #define BNX_RPM_DEBUG0_DONE (1L<<24) 2917 #define BNX_RPM_DEBUG0_WAIT_4_DONE (1L<<25) 2918 #define BNX_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) 2919 #define BNX_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27) 2920 #define BNX_RPM_DEBUG0_IGNORE_VLAN (1L<<28) 2921 #define BNX_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) 2922 2923 #define BNX_RPM_DEBUG1 0x00001988 2924 #define BNX_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) 2925 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) 2926 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0) 2927 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0) 2928 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0) 2929 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0) 2930 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0) 2931 #define BNX_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) 2932 #define BNX_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) 2933 #define BNX_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) 2934 #define BNX_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) 2935 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) 2936 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0) 2937 #define BNX_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) 2938 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0) 2939 #define BNX_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0) 2940 #define BNX_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0) 2941 #define BNX_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) 2942 #define BNX_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) 2943 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) 2944 #define BNX_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) 2945 #define BNX_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) 2946 2947 #define BNX_RPM_DEBUG2 0x0000198c 2948 #define BNX_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) 2949 #define BNX_RPM_DEBUG2_IP_BCNT (0xffL<<16) 2950 #define BNX_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) 2951 #define BNX_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) 2952 #define BNX_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) 2953 #define BNX_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) 2954 #define BNX_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) 2955 #define BNX_RPM_DEBUG2_FM_DISCARD (1L<<29) 2956 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30) 2957 #define BNX_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31) 2958 2959 #define BNX_RPM_DEBUG3 0x00001990 2960 #define BNX_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) 2961 #define BNX_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9) 2962 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10) 2963 #define BNX_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11) 2964 #define BNX_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12) 2965 #define BNX_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13) 2966 #define BNX_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14) 2967 #define BNX_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15) 2968 #define BNX_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16) 2969 #define BNX_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21) 2970 #define BNX_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) 2971 #define BNX_RPM_DEBUG3_DROP_NXT (1L<<23) 2972 #define BNX_RPM_DEBUG3_FTQ_FSM (0x3L<<24) 2973 #define BNX_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) 2974 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24) 2975 #define BNX_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24) 2976 #define BNX_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) 2977 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26) 2978 #define BNX_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26) 2979 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26) 2980 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26) 2981 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26) 2982 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26) 2983 #define BNX_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26) 2984 #define BNX_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26) 2985 #define BNX_RPM_DEBUG3_MBFREE_FSM (1L<<29) 2986 #define BNX_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) 2987 #define BNX_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29) 2988 #define BNX_RPM_DEBUG3_MBALLOC_FSM (1L<<30) 2989 #define BNX_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30) 2990 #define BNX_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30) 2991 #define BNX_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) 2992 2993 #define BNX_RPM_DEBUG4 0x00001994 2994 #define BNX_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0) 2995 #define BNX_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) 2996 #define BNX_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) 2997 #define BNX_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) 2998 2999 #define BNX_RPM_DEBUG5 0x00001998 3000 #define BNX_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) 3001 #define BNX_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) 3002 #define BNX_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) 3003 #define BNX_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) 3004 #define BNX_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20) 3005 #define BNX_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) 3006 #define BNX_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22) 3007 #define BNX_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23) 3008 #define BNX_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) 3009 #define BNX_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25) 3010 #define BNX_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26) 3011 #define BNX_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27) 3012 #define BNX_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28) 3013 #define BNX_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29) 3014 #define BNX_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) 3015 #define BNX_RPM_DEBUG5_HOLDREG_RD (1L<<31) 3016 3017 #define BNX_RPM_DEBUG6 0x0000199c 3018 #define BNX_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) 3019 #define BNX_RPM_DEBUG6_VEC (0xffffL<<16) 3020 3021 #define BNX_RPM_DEBUG7 0x000019a0 3022 #define BNX_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0) 3023 3024 #define BNX_RPM_DEBUG8 0x000019a4 3025 #define BNX_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) 3026 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0) 3027 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0) 3028 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0) 3029 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0) 3030 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0) 3031 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0) 3032 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0) 3033 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0) 3034 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0) 3035 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0) 3036 #define BNX_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0) 3037 #define BNX_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) 3038 #define BNX_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5) 3039 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6) 3040 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7) 3041 #define BNX_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8) 3042 #define BNX_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9) 3043 #define BNX_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10) 3044 #define BNX_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11) 3045 #define BNX_RPM_DEBUG8_EOF_DET (1L<<12) 3046 #define BNX_RPM_DEBUG8_SOF_DET (1L<<13) 3047 #define BNX_RPM_DEBUG8_WAIT_4_SOF (1L<<14) 3048 #define BNX_RPM_DEBUG8_ALL_DONE (1L<<15) 3049 #define BNX_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) 3050 #define BNX_RPM_DEBUG8_BYTE_CTR (0xffL<<24) 3051 3052 #define BNX_RPM_DEBUG9 0x000019a8 3053 #define BNX_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) 3054 #define BNX_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) 3055 #define BNX_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) 3056 #define BNX_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28) 3057 #define BNX_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29) 3058 #define BNX_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) 3059 #define BNX_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) 3060 3061 #define BNX_RPM_ACPI_DBG_BUF_W00 0x000019c0 3062 #define BNX_RPM_ACPI_DBG_BUF_W01 0x000019c4 3063 #define BNX_RPM_ACPI_DBG_BUF_W02 0x000019c8 3064 #define BNX_RPM_ACPI_DBG_BUF_W03 0x000019cc 3065 #define BNX_RPM_ACPI_DBG_BUF_W10 0x000019d0 3066 #define BNX_RPM_ACPI_DBG_BUF_W11 0x000019d4 3067 #define BNX_RPM_ACPI_DBG_BUF_W12 0x000019d8 3068 #define BNX_RPM_ACPI_DBG_BUF_W13 0x000019dc 3069 #define BNX_RPM_ACPI_DBG_BUF_W20 0x000019e0 3070 #define BNX_RPM_ACPI_DBG_BUF_W21 0x000019e4 3071 #define BNX_RPM_ACPI_DBG_BUF_W22 0x000019e8 3072 #define BNX_RPM_ACPI_DBG_BUF_W23 0x000019ec 3073 #define BNX_RPM_ACPI_DBG_BUF_W30 0x000019f0 3074 #define BNX_RPM_ACPI_DBG_BUF_W31 0x000019f4 3075 #define BNX_RPM_ACPI_DBG_BUF_W32 0x000019f8 3076 #define BNX_RPM_ACPI_DBG_BUF_W33 0x000019fc 3077 3078 3079 /* 3080 * rbuf_reg definition 3081 * offset: 0x200000 3082 */ 3083 #define BNX_RBUF_COMMAND 0x00200000 3084 #define BNX_RBUF_COMMAND_ENABLED (1L<<0) 3085 #define BNX_RBUF_COMMAND_FREE_INIT (1L<<1) 3086 #define BNX_RBUF_COMMAND_RAM_INIT (1L<<2) 3087 #define BNX_RBUF_COMMAND_OVER_FREE (1L<<4) 3088 #define BNX_RBUF_COMMAND_ALLOC_REQ (1L<<5) 3089 3090 #define BNX_RBUF_STATUS1 0x00200004 3091 #define BNX_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) 3092 3093 #define BNX_RBUF_STATUS2 0x00200008 3094 #define BNX_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) 3095 #define BNX_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) 3096 3097 #define BNX_RBUF_CONFIG 0x0020000c 3098 #define BNX_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) 3099 #define BNX_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) 3100 3101 #define BNX_RBUF_FW_BUF_ALLOC 0x00200010 3102 #define BNX_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) 3103 3104 #define BNX_RBUF_FW_BUF_FREE 0x00200014 3105 #define BNX_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) 3106 #define BNX_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) 3107 #define BNX_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) 3108 3109 #define BNX_RBUF_FW_BUF_SEL 0x00200018 3110 #define BNX_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) 3111 #define BNX_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) 3112 #define BNX_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) 3113 3114 #define BNX_RBUF_CONFIG2 0x0020001c 3115 #define BNX_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) 3116 #define BNX_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) 3117 3118 #define BNX_RBUF_CONFIG3 0x00200020 3119 #define BNX_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) 3120 #define BNX_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) 3121 3122 #define BNX_RBUF_PKT_DATA 0x00208000 3123 #define BNX_RBUF_CLIST_DATA 0x00210000 3124 #define BNX_RBUF_BUF_DATA 0x00220000 3125 3126 3127 /* 3128 * rv2p_reg definition 3129 * offset: 0x2800 3130 */ 3131 #define BNX_RV2P_COMMAND 0x00002800 3132 #define BNX_RV2P_COMMAND_ENABLED (1L<<0) 3133 #define BNX_RV2P_COMMAND_PROC1_INTRPT (1L<<1) 3134 #define BNX_RV2P_COMMAND_PROC2_INTRPT (1L<<2) 3135 #define BNX_RV2P_COMMAND_ABORT0 (1L<<4) 3136 #define BNX_RV2P_COMMAND_ABORT1 (1L<<5) 3137 #define BNX_RV2P_COMMAND_ABORT2 (1L<<6) 3138 #define BNX_RV2P_COMMAND_ABORT3 (1L<<7) 3139 #define BNX_RV2P_COMMAND_ABORT4 (1L<<8) 3140 #define BNX_RV2P_COMMAND_ABORT5 (1L<<9) 3141 #define BNX_RV2P_COMMAND_PROC1_RESET (1L<<16) 3142 #define BNX_RV2P_COMMAND_PROC2_RESET (1L<<17) 3143 #define BNX_RV2P_COMMAND_CTXIF_RESET (1L<<18) 3144 3145 #define BNX_RV2P_STATUS 0x00002804 3146 #define BNX_RV2P_STATUS_ALWAYS_0 (1L<<0) 3147 #define BNX_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8) 3148 #define BNX_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9) 3149 #define BNX_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10) 3150 #define BNX_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11) 3151 #define BNX_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12) 3152 #define BNX_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13) 3153 3154 #define BNX_RV2P_CONFIG 0x00002808 3155 #define BNX_RV2P_CONFIG_STALL_PROC1 (1L<<0) 3156 #define BNX_RV2P_CONFIG_STALL_PROC2 (1L<<1) 3157 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8) 3158 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9) 3159 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10) 3160 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11) 3161 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12) 3162 #define BNX_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13) 3163 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16) 3164 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17) 3165 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18) 3166 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19) 3167 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20) 3168 #define BNX_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21) 3169 #define BNX_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) 3170 #define BNX_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) 3171 #define BNX_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) 3172 #define BNX_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) 3173 #define BNX_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) 3174 #define BNX_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) 3175 #define BNX_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) 3176 #define BNX_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) 3177 #define BNX_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) 3178 #define BNX_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) 3179 #define BNX_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) 3180 #define BNX_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) 3181 #define BNX_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) 3182 #define BNX_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) 3183 3184 #define BNX_RV2P_GEN_BFR_ADDR_0 0x00002810 3185 #define BNX_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) 3186 3187 #define BNX_RV2P_GEN_BFR_ADDR_1 0x00002814 3188 #define BNX_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) 3189 3190 #define BNX_RV2P_GEN_BFR_ADDR_2 0x00002818 3191 #define BNX_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) 3192 3193 #define BNX_RV2P_GEN_BFR_ADDR_3 0x0000281c 3194 #define BNX_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) 3195 3196 #define BNX_RV2P_INSTR_HIGH 0x00002830 3197 #define BNX_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) 3198 3199 #define BNX_RV2P_INSTR_LOW 0x00002834 3200 #define BNX_RV2P_PROC1_ADDR_CMD 0x00002838 3201 #define BNX_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) 3202 #define BNX_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) 3203 3204 #define BNX_RV2P_PROC2_ADDR_CMD 0x0000283c 3205 #define BNX_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) 3206 #define BNX_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) 3207 3208 #define BNX_RV2P_PROC1_GRC_DEBUG 0x00002840 3209 #define BNX_RV2P_PROC2_GRC_DEBUG 0x00002844 3210 #define BNX_RV2P_GRC_PROC_DEBUG 0x00002848 3211 #define BNX_RV2P_DEBUG_VECT_PEEK 0x0000284c 3212 #define BNX_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3213 #define BNX_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3214 #define BNX_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3215 #define BNX_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3216 #define BNX_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3217 #define BNX_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3218 3219 #define BNX_RV2P_PFTQ_DATA 0x00002b40 3220 #define BNX_RV2P_PFTQ_CMD 0x00002b78 3221 #define BNX_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) 3222 #define BNX_RV2P_PFTQ_CMD_WR_TOP (1L<<10) 3223 #define BNX_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) 3224 #define BNX_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) 3225 #define BNX_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) 3226 #define BNX_RV2P_PFTQ_CMD_RD_DATA (1L<<26) 3227 #define BNX_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) 3228 #define BNX_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) 3229 #define BNX_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29) 3230 #define BNX_RV2P_PFTQ_CMD_POP (1L<<30) 3231 #define BNX_RV2P_PFTQ_CMD_BUSY (1L<<31) 3232 3233 #define BNX_RV2P_PFTQ_CTL 0x00002b7c 3234 #define BNX_RV2P_PFTQ_CTL_INTERVENE (1L<<0) 3235 #define BNX_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) 3236 #define BNX_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2) 3237 #define BNX_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3238 #define BNX_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3239 3240 #define BNX_RV2P_TFTQ_DATA 0x00002b80 3241 #define BNX_RV2P_TFTQ_CMD 0x00002bb8 3242 #define BNX_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) 3243 #define BNX_RV2P_TFTQ_CMD_WR_TOP (1L<<10) 3244 #define BNX_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) 3245 #define BNX_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) 3246 #define BNX_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) 3247 #define BNX_RV2P_TFTQ_CMD_RD_DATA (1L<<26) 3248 #define BNX_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) 3249 #define BNX_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) 3250 #define BNX_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29) 3251 #define BNX_RV2P_TFTQ_CMD_POP (1L<<30) 3252 #define BNX_RV2P_TFTQ_CMD_BUSY (1L<<31) 3253 3254 #define BNX_RV2P_TFTQ_CTL 0x00002bbc 3255 #define BNX_RV2P_TFTQ_CTL_INTERVENE (1L<<0) 3256 #define BNX_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) 3257 #define BNX_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2) 3258 #define BNX_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3259 #define BNX_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3260 3261 #define BNX_RV2P_MFTQ_DATA 0x00002bc0 3262 #define BNX_RV2P_MFTQ_CMD 0x00002bf8 3263 #define BNX_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) 3264 #define BNX_RV2P_MFTQ_CMD_WR_TOP (1L<<10) 3265 #define BNX_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) 3266 #define BNX_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) 3267 #define BNX_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) 3268 #define BNX_RV2P_MFTQ_CMD_RD_DATA (1L<<26) 3269 #define BNX_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) 3270 #define BNX_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) 3271 #define BNX_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29) 3272 #define BNX_RV2P_MFTQ_CMD_POP (1L<<30) 3273 #define BNX_RV2P_MFTQ_CMD_BUSY (1L<<31) 3274 3275 #define BNX_RV2P_MFTQ_CTL 0x00002bfc 3276 #define BNX_RV2P_MFTQ_CTL_INTERVENE (1L<<0) 3277 #define BNX_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) 3278 #define BNX_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2) 3279 #define BNX_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3280 #define BNX_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3281 3282 3283 3284 /* 3285 * mq_reg definition 3286 * offset: 0x3c00 3287 */ 3288 #define BNX_MQ_COMMAND 0x00003c00 3289 #define BNX_MQ_COMMAND_ENABLED (1L<<0) 3290 #define BNX_MQ_COMMAND_OVERFLOW (1L<<4) 3291 #define BNX_MQ_COMMAND_WR_ERROR (1L<<5) 3292 #define BNX_MQ_COMMAND_RD_ERROR (1L<<6) 3293 3294 #define BNX_MQ_STATUS 0x00003c04 3295 #define BNX_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) 3296 #define BNX_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17) 3297 #define BNX_MQ_STATUS_PCI_STALL_STAT (1L<<18) 3298 3299 #define BNX_MQ_CONFIG 0x00003c08 3300 #define BNX_MQ_CONFIG_TX_HIGH_PRI (1L<<0) 3301 #define BNX_MQ_CONFIG_HALT_DIS (1L<<1) 3302 #define BNX_MQ_CONFIG_BIN_MQ_MODE (1L<<2) 3303 #define BNX_MQ_CONFIG_DIS_IDB_DROP (1L<<3) 3304 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) 3305 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4) 3306 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4) 3307 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4) 3308 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4) 3309 #define BNX_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4) 3310 #define BNX_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) 3311 #define BNX_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) 3312 3313 #define BNX_MQ_ENQUEUE1 0x00003c0c 3314 #define BNX_MQ_ENQUEUE1_OFFSET (0x3fL<<2) 3315 #define BNX_MQ_ENQUEUE1_CID (0x3fffL<<8) 3316 #define BNX_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) 3317 #define BNX_MQ_ENQUEUE1_KNL_MODE (1L<<28) 3318 3319 #define BNX_MQ_ENQUEUE2 0x00003c10 3320 #define BNX_MQ_BAD_WR_ADDR 0x00003c14 3321 #define BNX_MQ_BAD_RD_ADDR 0x00003c18 3322 #define BNX_MQ_KNL_BYP_WIND_START 0x00003c1c 3323 #define BNX_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12) 3324 3325 #define BNX_MQ_KNL_WIND_END 0x00003c20 3326 #define BNX_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) 3327 3328 #define BNX_MQ_KNL_WRITE_MASK1 0x00003c24 3329 #define BNX_MQ_KNL_TX_MASK1 0x00003c28 3330 #define BNX_MQ_KNL_CMD_MASK1 0x00003c2c 3331 #define BNX_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 3332 #define BNX_MQ_KNL_RX_V2P_MASK1 0x00003c34 3333 #define BNX_MQ_KNL_WRITE_MASK2 0x00003c38 3334 #define BNX_MQ_KNL_TX_MASK2 0x00003c3c 3335 #define BNX_MQ_KNL_CMD_MASK2 0x00003c40 3336 #define BNX_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 3337 #define BNX_MQ_KNL_RX_V2P_MASK2 0x00003c48 3338 #define BNX_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c 3339 #define BNX_MQ_KNL_BYP_TX_MASK1 0x00003c50 3340 #define BNX_MQ_KNL_BYP_CMD_MASK1 0x00003c54 3341 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58 3342 #define BNX_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c 3343 #define BNX_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 3344 #define BNX_MQ_KNL_BYP_TX_MASK2 0x00003c64 3345 #define BNX_MQ_KNL_BYP_CMD_MASK2 0x00003c68 3346 #define BNX_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c 3347 #define BNX_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 3348 #define BNX_MQ_MEM_WR_ADDR 0x00003c74 3349 #define BNX_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) 3350 3351 #define BNX_MQ_MEM_WR_DATA0 0x00003c78 3352 #define BNX_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) 3353 3354 #define BNX_MQ_MEM_WR_DATA1 0x00003c7c 3355 #define BNX_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) 3356 3357 #define BNX_MQ_MEM_WR_DATA2 0x00003c80 3358 #define BNX_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) 3359 3360 #define BNX_MQ_MEM_RD_ADDR 0x00003c84 3361 #define BNX_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) 3362 3363 #define BNX_MQ_MEM_RD_DATA0 0x00003c88 3364 #define BNX_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) 3365 3366 #define BNX_MQ_MEM_RD_DATA1 0x00003c8c 3367 #define BNX_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) 3368 3369 #define BNX_MQ_MEM_RD_DATA2 0x00003c90 3370 #define BNX_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) 3371 3372 #define BNX_MQ_MAP_L2_5 0x00003d34 3373 #define BNX_MQ_MAP_L2_5_MQ_OFFSET (0xffL<<0) 3374 #define BNX_MQ_MAP_L2_5_SZ (0x3L<<8) 3375 #define BNX_MQ_MAP_L2_5_CTX_OFFSET (0x2ffL<<10) 3376 #define BNX_MQ_MAP_L2_5_BIN_OFFSET (0x7L<<23) 3377 #define BNX_MQ_MAP_L2_5_ARM (0x3L<<26) 3378 #define BNX_MQ_MAP_L2_5_ENA (0x1L<<31) 3379 #define BNX_MQ_MAP_L2_5_DEFAULT 0x83000b08 3380 3381 3382 /* 3383 * tbdr_reg definition 3384 * offset: 0x5000 3385 */ 3386 #define BNX_TBDR_COMMAND 0x00005000 3387 #define BNX_TBDR_COMMAND_ENABLE (1L<<0) 3388 #define BNX_TBDR_COMMAND_SOFT_RST (1L<<1) 3389 #define BNX_TBDR_COMMAND_MSTR_ABORT (1L<<4) 3390 3391 #define BNX_TBDR_STATUS 0x00005004 3392 #define BNX_TBDR_STATUS_DMA_WAIT (1L<<0) 3393 #define BNX_TBDR_STATUS_FTQ_WAIT (1L<<1) 3394 #define BNX_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) 3395 #define BNX_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) 3396 #define BNX_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4) 3397 #define BNX_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) 3398 #define BNX_TBDR_STATUS_BURST_CNT (1L<<6) 3399 3400 #define BNX_TBDR_CONFIG 0x00005008 3401 #define BNX_TBDR_CONFIG_MAX_BDS (0xffL<<0) 3402 #define BNX_TBDR_CONFIG_SWAP_MODE (1L<<8) 3403 #define BNX_TBDR_CONFIG_PRIORITY (1L<<9) 3404 #define BNX_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10) 3405 #define BNX_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) 3406 #define BNX_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) 3407 #define BNX_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) 3408 #define BNX_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) 3409 #define BNX_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) 3410 #define BNX_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) 3411 #define BNX_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) 3412 #define BNX_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) 3413 #define BNX_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) 3414 #define BNX_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) 3415 #define BNX_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) 3416 #define BNX_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) 3417 #define BNX_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) 3418 #define BNX_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) 3419 3420 #define BNX_TBDR_DEBUG_VECT_PEEK 0x0000500c 3421 #define BNX_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3422 #define BNX_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3423 #define BNX_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3424 #define BNX_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3425 #define BNX_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3426 #define BNX_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3427 3428 #define BNX_TBDR_FTQ_DATA 0x000053c0 3429 #define BNX_TBDR_FTQ_CMD 0x000053f8 3430 #define BNX_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) 3431 #define BNX_TBDR_FTQ_CMD_WR_TOP (1L<<10) 3432 #define BNX_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) 3433 #define BNX_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) 3434 #define BNX_TBDR_FTQ_CMD_SFT_RESET (1L<<25) 3435 #define BNX_TBDR_FTQ_CMD_RD_DATA (1L<<26) 3436 #define BNX_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) 3437 #define BNX_TBDR_FTQ_CMD_ADD_DATA (1L<<28) 3438 #define BNX_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) 3439 #define BNX_TBDR_FTQ_CMD_POP (1L<<30) 3440 #define BNX_TBDR_FTQ_CMD_BUSY (1L<<31) 3441 3442 #define BNX_TBDR_FTQ_CTL 0x000053fc 3443 #define BNX_TBDR_FTQ_CTL_INTERVENE (1L<<0) 3444 #define BNX_TBDR_FTQ_CTL_OVERFLOW (1L<<1) 3445 #define BNX_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3446 #define BNX_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3447 #define BNX_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3448 3449 3450 3451 /* 3452 * tdma_reg definition 3453 * offset: 0x5c00 3454 */ 3455 #define BNX_TDMA_COMMAND 0x00005c00 3456 #define BNX_TDMA_COMMAND_ENABLED (1L<<0) 3457 #define BNX_TDMA_COMMAND_MASTER_ABORT (1L<<4) 3458 #define BNX_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7) 3459 3460 #define BNX_TDMA_STATUS 0x00005c04 3461 #define BNX_TDMA_STATUS_DMA_WAIT (1L<<0) 3462 #define BNX_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) 3463 #define BNX_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) 3464 #define BNX_TDMA_STATUS_LOCK_WAIT (1L<<3) 3465 #define BNX_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) 3466 #define BNX_TDMA_STATUS_BURST_CNT (1L<<17) 3467 3468 #define BNX_TDMA_CONFIG 0x00005c08 3469 #define BNX_TDMA_CONFIG_ONE_DMA (1L<<0) 3470 #define BNX_TDMA_CONFIG_ONE_RECORD (1L<<1) 3471 #define BNX_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) 3472 #define BNX_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) 3473 #define BNX_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) 3474 #define BNX_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) 3475 #define BNX_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) 3476 #define BNX_TDMA_CONFIG_LINE_SZ (0xfL<<8) 3477 #define BNX_TDMA_CONFIG_LINE_SZ_64 (0L<<8) 3478 #define BNX_TDMA_CONFIG_LINE_SZ_128 (4L<<8) 3479 #define BNX_TDMA_CONFIG_LINE_SZ_256 (6L<<8) 3480 #define BNX_TDMA_CONFIG_LINE_SZ_512 (8L<<8) 3481 #define BNX_TDMA_CONFIG_ALIGN_ENA (1L<<15) 3482 #define BNX_TDMA_CONFIG_CHK_L2_BD (1L<<16) 3483 #define BNX_TDMA_CONFIG_FIFO_CMP (0xfL<<20) 3484 3485 #define BNX_TDMA_PAYLOAD_PROD 0x00005c0c 3486 #define BNX_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) 3487 3488 #define BNX_TDMA_DBG_WATCHDOG 0x00005c10 3489 #define BNX_TDMA_DBG_TRIGGER 0x00005c14 3490 #define BNX_TDMA_DMAD_FSM 0x00005c80 3491 #define BNX_TDMA_DMAD_FSM_BD_INVLD (1L<<0) 3492 #define BNX_TDMA_DMAD_FSM_PUSH (0xfL<<4) 3493 #define BNX_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) 3494 #define BNX_TDMA_DMAD_FSM_ARB_CTX (1L<<12) 3495 #define BNX_TDMA_DMAD_FSM_DR_INTF (1L<<16) 3496 #define BNX_TDMA_DMAD_FSM_DMAD (0x7L<<20) 3497 #define BNX_TDMA_DMAD_FSM_BD (0xfL<<24) 3498 3499 #define BNX_TDMA_DMAD_STATUS 0x00005c84 3500 #define BNX_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0) 3501 #define BNX_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4) 3502 #define BNX_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8) 3503 #define BNX_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) 3504 3505 #define BNX_TDMA_DR_INTF_FSM 0x00005c88 3506 #define BNX_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) 3507 #define BNX_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) 3508 #define BNX_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) 3509 #define BNX_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) 3510 #define BNX_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) 3511 3512 #define BNX_TDMA_DR_INTF_STATUS 0x00005c8c 3513 #define BNX_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0) 3514 #define BNX_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4) 3515 #define BNX_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8) 3516 #define BNX_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12) 3517 #define BNX_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16) 3518 3519 #define BNX_TDMA_FTQ_DATA 0x00005fc0 3520 #define BNX_TDMA_FTQ_CMD 0x00005ff8 3521 #define BNX_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) 3522 #define BNX_TDMA_FTQ_CMD_WR_TOP (1L<<10) 3523 #define BNX_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) 3524 #define BNX_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) 3525 #define BNX_TDMA_FTQ_CMD_SFT_RESET (1L<<25) 3526 #define BNX_TDMA_FTQ_CMD_RD_DATA (1L<<26) 3527 #define BNX_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) 3528 #define BNX_TDMA_FTQ_CMD_ADD_DATA (1L<<28) 3529 #define BNX_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) 3530 #define BNX_TDMA_FTQ_CMD_POP (1L<<30) 3531 #define BNX_TDMA_FTQ_CMD_BUSY (1L<<31) 3532 3533 #define BNX_TDMA_FTQ_CTL 0x00005ffc 3534 #define BNX_TDMA_FTQ_CTL_INTERVENE (1L<<0) 3535 #define BNX_TDMA_FTQ_CTL_OVERFLOW (1L<<1) 3536 #define BNX_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3537 #define BNX_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3538 #define BNX_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3539 3540 3541 3542 /* 3543 * hc_reg definition 3544 * offset: 0x6800 3545 */ 3546 #define BNX_HC_COMMAND 0x00006800 3547 #define BNX_HC_COMMAND_ENABLE (1L<<0) 3548 #define BNX_HC_COMMAND_SKIP_ABORT (1L<<4) 3549 #define BNX_HC_COMMAND_COAL_NOW (1L<<16) 3550 #define BNX_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) 3551 #define BNX_HC_COMMAND_STATS_NOW (1L<<18) 3552 #define BNX_HC_COMMAND_FORCE_INT (0x3L<<19) 3553 #define BNX_HC_COMMAND_FORCE_INT_NULL (0L<<19) 3554 #define BNX_HC_COMMAND_FORCE_INT_HIGH (1L<<19) 3555 #define BNX_HC_COMMAND_FORCE_INT_LOW (2L<<19) 3556 #define BNX_HC_COMMAND_FORCE_INT_FREE (3L<<19) 3557 #define BNX_HC_COMMAND_CLR_STAT_NOW (1L<<21) 3558 3559 #define BNX_HC_STATUS 0x00006804 3560 #define BNX_HC_STATUS_MASTER_ABORT (1L<<0) 3561 #define BNX_HC_STATUS_PARITY_ERROR_STATE (1L<<1) 3562 #define BNX_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) 3563 #define BNX_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17) 3564 #define BNX_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18) 3565 #define BNX_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) 3566 #define BNX_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20) 3567 #define BNX_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23) 3568 #define BNX_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24) 3569 #define BNX_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25) 3570 3571 #define BNX_HC_CONFIG 0x00006808 3572 #define BNX_HC_CONFIG_COLLECT_STATS (1L<<0) 3573 #define BNX_HC_CONFIG_RX_TMR_MODE (1L<<1) 3574 #define BNX_HC_CONFIG_TX_TMR_MODE (1L<<2) 3575 #define BNX_HC_CONFIG_COM_TMR_MODE (1L<<3) 3576 #define BNX_HC_CONFIG_CMD_TMR_MODE (1L<<4) 3577 #define BNX_HC_CONFIG_STATISTIC_PRIORITY (1L<<5) 3578 #define BNX_HC_CONFIG_STATUS_PRIORITY (1L<<6) 3579 #define BNX_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) 3580 3581 #define BNX_HC_ATTN_BITS_ENABLE 0x0000680c 3582 #define BNX_HC_STATUS_ADDR_L 0x00006810 3583 #define BNX_HC_STATUS_ADDR_H 0x00006814 3584 #define BNX_HC_STATISTICS_ADDR_L 0x00006818 3585 #define BNX_HC_STATISTICS_ADDR_H 0x0000681c 3586 #define BNX_HC_TX_QUICK_CONS_TRIP 0x00006820 3587 #define BNX_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3588 #define BNX_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) 3589 3590 #define BNX_HC_COMP_PROD_TRIP 0x00006824 3591 #define BNX_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) 3592 #define BNX_HC_COMP_PROD_TRIP_INT (0xffL<<16) 3593 3594 #define BNX_HC_RX_QUICK_CONS_TRIP 0x00006828 3595 #define BNX_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0) 3596 #define BNX_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) 3597 3598 #define BNX_HC_RX_TICKS 0x0000682c 3599 #define BNX_HC_RX_TICKS_VALUE (0x3ffL<<0) 3600 #define BNX_HC_RX_TICKS_INT (0x3ffL<<16) 3601 3602 #define BNX_HC_TX_TICKS 0x00006830 3603 #define BNX_HC_TX_TICKS_VALUE (0x3ffL<<0) 3604 #define BNX_HC_TX_TICKS_INT (0x3ffL<<16) 3605 3606 #define BNX_HC_COM_TICKS 0x00006834 3607 #define BNX_HC_COM_TICKS_VALUE (0x3ffL<<0) 3608 #define BNX_HC_COM_TICKS_INT (0x3ffL<<16) 3609 3610 #define BNX_HC_CMD_TICKS 0x00006838 3611 #define BNX_HC_CMD_TICKS_VALUE (0x3ffL<<0) 3612 #define BNX_HC_CMD_TICKS_INT (0x3ffL<<16) 3613 3614 #define BNX_HC_PERIODIC_TICKS 0x0000683c 3615 #define BNX_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0) 3616 3617 #define BNX_HC_STAT_COLLECT_TICKS 0x00006840 3618 #define BNX_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4) 3619 3620 #define BNX_HC_STATS_TICKS 0x00006844 3621 #define BNX_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8) 3622 3623 #define BNX_HC_STAT_MEM_DATA 0x0000684c 3624 #define BNX_HC_STAT_GEN_SEL_0 0x00006850 3625 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0) 3626 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0) 3627 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0) 3628 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0) 3629 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0) 3630 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0) 3631 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0) 3632 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0) 3633 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0) 3634 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0) 3635 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0) 3636 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0) 3637 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0) 3638 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0) 3639 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0) 3640 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0) 3641 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0) 3642 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0) 3643 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0) 3644 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0) 3645 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0) 3646 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0) 3647 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0) 3648 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0) 3649 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0) 3650 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0) 3651 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0) 3652 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0) 3653 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0) 3654 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0) 3655 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0) 3656 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0) 3657 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0) 3658 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0) 3659 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0) 3660 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0) 3661 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0) 3662 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0) 3663 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0) 3664 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0) 3665 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0) 3666 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0) 3667 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0) 3668 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0) 3669 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0) 3670 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0) 3671 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0) 3672 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0) 3673 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0) 3674 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0) 3675 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0) 3676 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0) 3677 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0) 3678 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0) 3679 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0) 3680 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0) 3681 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0) 3682 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0) 3683 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0) 3684 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0) 3685 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0) 3686 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0) 3687 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0) 3688 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0) 3689 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0) 3690 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0) 3691 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0) 3692 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0) 3693 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0) 3694 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0) 3695 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0) 3696 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0) 3697 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0) 3698 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0) 3699 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0) 3700 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0) 3701 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0) 3702 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0) 3703 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0) 3704 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0) 3705 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0) 3706 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0) 3707 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0) 3708 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0) 3709 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0) 3710 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0) 3711 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0) 3712 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0) 3713 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0) 3714 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0) 3715 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0) 3716 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0) 3717 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0) 3718 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0) 3719 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0) 3720 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0) 3721 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0) 3722 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0) 3723 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0) 3724 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0) 3725 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0) 3726 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0) 3727 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0) 3728 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0) 3729 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0) 3730 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0) 3731 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0) 3732 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0) 3733 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0) 3734 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0) 3735 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0) 3736 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0) 3737 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0) 3738 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0) 3739 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0) 3740 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0) 3741 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0) 3742 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0) 3743 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0) 3744 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0) 3745 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0) 3746 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0) 3747 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0) 3748 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8) 3749 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16) 3750 #define BNX_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24) 3751 3752 #define BNX_HC_STAT_GEN_SEL_1 0x00006854 3753 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0) 3754 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8) 3755 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16) 3756 #define BNX_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24) 3757 3758 #define BNX_HC_STAT_GEN_SEL_2 0x00006858 3759 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0) 3760 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8) 3761 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16) 3762 #define BNX_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24) 3763 3764 #define BNX_HC_STAT_GEN_SEL_3 0x0000685c 3765 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0) 3766 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8) 3767 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16) 3768 #define BNX_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24) 3769 3770 #define BNX_HC_STAT_GEN_STAT0 0x00006888 3771 #define BNX_HC_STAT_GEN_STAT1 0x0000688c 3772 #define BNX_HC_STAT_GEN_STAT2 0x00006890 3773 #define BNX_HC_STAT_GEN_STAT3 0x00006894 3774 #define BNX_HC_STAT_GEN_STAT4 0x00006898 3775 #define BNX_HC_STAT_GEN_STAT5 0x0000689c 3776 #define BNX_HC_STAT_GEN_STAT6 0x000068a0 3777 #define BNX_HC_STAT_GEN_STAT7 0x000068a4 3778 #define BNX_HC_STAT_GEN_STAT8 0x000068a8 3779 #define BNX_HC_STAT_GEN_STAT9 0x000068ac 3780 #define BNX_HC_STAT_GEN_STAT10 0x000068b0 3781 #define BNX_HC_STAT_GEN_STAT11 0x000068b4 3782 #define BNX_HC_STAT_GEN_STAT12 0x000068b8 3783 #define BNX_HC_STAT_GEN_STAT13 0x000068bc 3784 #define BNX_HC_STAT_GEN_STAT14 0x000068c0 3785 #define BNX_HC_STAT_GEN_STAT15 0x000068c4 3786 #define BNX_HC_STAT_GEN_STAT_AC0 0x000068c8 3787 #define BNX_HC_STAT_GEN_STAT_AC1 0x000068cc 3788 #define BNX_HC_STAT_GEN_STAT_AC2 0x000068d0 3789 #define BNX_HC_STAT_GEN_STAT_AC3 0x000068d4 3790 #define BNX_HC_STAT_GEN_STAT_AC4 0x000068d8 3791 #define BNX_HC_STAT_GEN_STAT_AC5 0x000068dc 3792 #define BNX_HC_STAT_GEN_STAT_AC6 0x000068e0 3793 #define BNX_HC_STAT_GEN_STAT_AC7 0x000068e4 3794 #define BNX_HC_STAT_GEN_STAT_AC8 0x000068e8 3795 #define BNX_HC_STAT_GEN_STAT_AC9 0x000068ec 3796 #define BNX_HC_STAT_GEN_STAT_AC10 0x000068f0 3797 #define BNX_HC_STAT_GEN_STAT_AC11 0x000068f4 3798 #define BNX_HC_STAT_GEN_STAT_AC12 0x000068f8 3799 #define BNX_HC_STAT_GEN_STAT_AC13 0x000068fc 3800 #define BNX_HC_STAT_GEN_STAT_AC14 0x00006900 3801 #define BNX_HC_STAT_GEN_STAT_AC15 0x00006904 3802 #define BNX_HC_VIS 0x00006908 3803 #define BNX_HC_VIS_STAT_BUILD_STATE (0xfL<<0) 3804 #define BNX_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0) 3805 #define BNX_HC_VIS_STAT_BUILD_STATE_START (1L<<0) 3806 #define BNX_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0) 3807 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0) 3808 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0) 3809 #define BNX_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0) 3810 #define BNX_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0) 3811 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0) 3812 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0) 3813 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0) 3814 #define BNX_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0) 3815 #define BNX_HC_VIS_DMA_STAT_STATE (0xfL<<8) 3816 #define BNX_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) 3817 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8) 3818 #define BNX_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8) 3819 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8) 3820 #define BNX_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) 3821 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8) 3822 #define BNX_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8) 3823 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8) 3824 #define BNX_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8) 3825 #define BNX_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) 3826 #define BNX_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8) 3827 #define BNX_HC_VIS_DMA_MSI_STATE (0x7L<<12) 3828 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15) 3829 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15) 3830 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15) 3831 #define BNX_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15) 3832 3833 #define BNX_HC_VIS_1 0x0000690c 3834 #define BNX_HC_VIS_1_HW_INTACK_STATE (1L<<4) 3835 #define BNX_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4) 3836 #define BNX_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4) 3837 #define BNX_HC_VIS_1_SW_INTACK_STATE (1L<<5) 3838 #define BNX_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5) 3839 #define BNX_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5) 3840 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6) 3841 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6) 3842 #define BNX_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6) 3843 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7) 3844 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7) 3845 #define BNX_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7) 3846 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) 3847 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17) 3848 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17) 3849 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17) 3850 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17) 3851 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17) 3852 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17) 3853 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17) 3854 #define BNX_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17) 3855 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) 3856 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21) 3857 #define BNX_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21) 3858 #define BNX_HC_VIS_1_INT_GEN_STATE (1L<<23) 3859 #define BNX_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) 3860 #define BNX_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23) 3861 #define BNX_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) 3862 #define BNX_HC_VIS_1_INT_B (1L<<27) 3863 3864 #define BNX_HC_DEBUG_VECT_PEEK 0x00006910 3865 #define BNX_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3866 #define BNX_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3867 #define BNX_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3868 #define BNX_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3869 #define BNX_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3870 #define BNX_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3871 3872 3873 3874 /* 3875 * txp_reg definition 3876 * offset: 0x40000 3877 */ 3878 #define BNX_TXP_CPU_MODE 0x00045000 3879 #define BNX_TXP_CPU_MODE_LOCAL_RST (1L<<0) 3880 #define BNX_TXP_CPU_MODE_STEP_ENA (1L<<1) 3881 #define BNX_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3882 #define BNX_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3883 #define BNX_TXP_CPU_MODE_MSG_BIT1 (1L<<6) 3884 #define BNX_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 3885 #define BNX_TXP_CPU_MODE_SOFT_HALT (1L<<10) 3886 #define BNX_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3887 #define BNX_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3888 #define BNX_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3889 #define BNX_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3890 3891 #define BNX_TXP_CPU_STATE 0x00045004 3892 #define BNX_TXP_CPU_STATE_BREAKPOINT (1L<<0) 3893 #define BNX_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 3894 #define BNX_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3895 #define BNX_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3896 #define BNX_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3897 #define BNX_TXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 3898 #define BNX_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) 3899 #define BNX_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3900 #define BNX_TXP_CPU_STATE_SOFT_HALTED (1L<<10) 3901 #define BNX_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3902 #define BNX_TXP_CPU_STATE_INTERRRUPT (1L<<12) 3903 #define BNX_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3904 #define BNX_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 3905 #define BNX_TXP_CPU_STATE_BLOCKED_READ (1L<<31) 3906 3907 #define BNX_TXP_CPU_EVENT_MASK 0x00045008 3908 #define BNX_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 3909 #define BNX_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 3910 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 3911 #define BNX_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 3912 #define BNX_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 3913 #define BNX_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 3914 #define BNX_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 3915 #define BNX_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 3916 #define BNX_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 3917 #define BNX_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 3918 #define BNX_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 3919 3920 #define BNX_TXP_CPU_PROGRAM_COUNTER 0x0004501c 3921 #define BNX_TXP_CPU_INSTRUCTION 0x00045020 3922 #define BNX_TXP_CPU_DATA_ACCESS 0x00045024 3923 #define BNX_TXP_CPU_INTERRUPT_ENABLE 0x00045028 3924 #define BNX_TXP_CPU_INTERRUPT_VECTOR 0x0004502c 3925 #define BNX_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 3926 #define BNX_TXP_CPU_HW_BREAKPOINT 0x00045034 3927 #define BNX_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 3928 #define BNX_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 3929 3930 #define BNX_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 3931 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 3932 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 3933 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 3934 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 3935 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 3936 #define BNX_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 3937 3938 #define BNX_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 3939 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 3940 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 3941 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 3942 #define BNX_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 3943 3944 #define BNX_TXP_CPU_REG_FILE 0x00045200 3945 #define BNX_TXP_FTQ_DATA 0x000453c0 3946 #define BNX_TXP_FTQ_CMD 0x000453f8 3947 #define BNX_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) 3948 #define BNX_TXP_FTQ_CMD_WR_TOP (1L<<10) 3949 #define BNX_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) 3950 #define BNX_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) 3951 #define BNX_TXP_FTQ_CMD_SFT_RESET (1L<<25) 3952 #define BNX_TXP_FTQ_CMD_RD_DATA (1L<<26) 3953 #define BNX_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 3954 #define BNX_TXP_FTQ_CMD_ADD_DATA (1L<<28) 3955 #define BNX_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 3956 #define BNX_TXP_FTQ_CMD_POP (1L<<30) 3957 #define BNX_TXP_FTQ_CMD_BUSY (1L<<31) 3958 3959 #define BNX_TXP_FTQ_CTL 0x000453fc 3960 #define BNX_TXP_FTQ_CTL_INTERVENE (1L<<0) 3961 #define BNX_TXP_FTQ_CTL_OVERFLOW (1L<<1) 3962 #define BNX_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 3963 #define BNX_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 3964 #define BNX_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 3965 3966 #define BNX_TXP_SCRATCH 0x00060000 3967 3968 3969 /* 3970 * tpat_reg definition 3971 * offset: 0x80000 3972 */ 3973 #define BNX_TPAT_CPU_MODE 0x00085000 3974 #define BNX_TPAT_CPU_MODE_LOCAL_RST (1L<<0) 3975 #define BNX_TPAT_CPU_MODE_STEP_ENA (1L<<1) 3976 #define BNX_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 3977 #define BNX_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 3978 #define BNX_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) 3979 #define BNX_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7) 3980 #define BNX_TPAT_CPU_MODE_SOFT_HALT (1L<<10) 3981 #define BNX_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 3982 #define BNX_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 3983 #define BNX_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 3984 #define BNX_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 3985 3986 #define BNX_TPAT_CPU_STATE 0x00085004 3987 #define BNX_TPAT_CPU_STATE_BREAKPOINT (1L<<0) 3988 #define BNX_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2) 3989 #define BNX_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 3990 #define BNX_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 3991 #define BNX_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 3992 #define BNX_TPAT_CPU_STATE_BAD_pc_HALTED (1L<<6) 3993 #define BNX_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7) 3994 #define BNX_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 3995 #define BNX_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) 3996 #define BNX_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 3997 #define BNX_TPAT_CPU_STATE_INTERRRUPT (1L<<12) 3998 #define BNX_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 3999 #define BNX_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15) 4000 #define BNX_TPAT_CPU_STATE_BLOCKED_READ (1L<<31) 4001 4002 #define BNX_TPAT_CPU_EVENT_MASK 0x00085008 4003 #define BNX_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4004 #define BNX_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4005 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4006 #define BNX_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4007 #define BNX_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4008 #define BNX_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4009 #define BNX_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4010 #define BNX_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4011 #define BNX_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4012 #define BNX_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4013 #define BNX_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4014 4015 #define BNX_TPAT_CPU_PROGRAM_COUNTER 0x0008501c 4016 #define BNX_TPAT_CPU_INSTRUCTION 0x00085020 4017 #define BNX_TPAT_CPU_DATA_ACCESS 0x00085024 4018 #define BNX_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 4019 #define BNX_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c 4020 #define BNX_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030 4021 #define BNX_TPAT_CPU_HW_BREAKPOINT 0x00085034 4022 #define BNX_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4023 #define BNX_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4024 4025 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 4026 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4027 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4028 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4029 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4030 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4031 #define BNX_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4032 4033 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 4034 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4035 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4036 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4037 #define BNX_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4038 4039 #define BNX_TPAT_CPU_REG_FILE 0x00085200 4040 #define BNX_TPAT_FTQ_DATA 0x000853c0 4041 #define BNX_TPAT_FTQ_CMD 0x000853f8 4042 #define BNX_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) 4043 #define BNX_TPAT_FTQ_CMD_WR_TOP (1L<<10) 4044 #define BNX_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) 4045 #define BNX_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) 4046 #define BNX_TPAT_FTQ_CMD_SFT_RESET (1L<<25) 4047 #define BNX_TPAT_FTQ_CMD_RD_DATA (1L<<26) 4048 #define BNX_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) 4049 #define BNX_TPAT_FTQ_CMD_ADD_DATA (1L<<28) 4050 #define BNX_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) 4051 #define BNX_TPAT_FTQ_CMD_POP (1L<<30) 4052 #define BNX_TPAT_FTQ_CMD_BUSY (1L<<31) 4053 4054 #define BNX_TPAT_FTQ_CTL 0x000853fc 4055 #define BNX_TPAT_FTQ_CTL_INTERVENE (1L<<0) 4056 #define BNX_TPAT_FTQ_CTL_OVERFLOW (1L<<1) 4057 #define BNX_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4058 #define BNX_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4059 #define BNX_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4060 4061 #define BNX_TPAT_SCRATCH 0x000a0000 4062 4063 4064 /* 4065 * rxp_reg definition 4066 * offset: 0xc0000 4067 */ 4068 #define BNX_RXP_CPU_MODE 0x000c5000 4069 #define BNX_RXP_CPU_MODE_LOCAL_RST (1L<<0) 4070 #define BNX_RXP_CPU_MODE_STEP_ENA (1L<<1) 4071 #define BNX_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4072 #define BNX_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4073 #define BNX_RXP_CPU_MODE_MSG_BIT1 (1L<<6) 4074 #define BNX_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4075 #define BNX_RXP_CPU_MODE_SOFT_HALT (1L<<10) 4076 #define BNX_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4077 #define BNX_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4078 #define BNX_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4079 #define BNX_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4080 4081 #define BNX_RXP_CPU_STATE 0x000c5004 4082 #define BNX_RXP_CPU_STATE_BREAKPOINT (1L<<0) 4083 #define BNX_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4084 #define BNX_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4085 #define BNX_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4086 #define BNX_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4087 #define BNX_RXP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4088 #define BNX_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) 4089 #define BNX_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4090 #define BNX_RXP_CPU_STATE_SOFT_HALTED (1L<<10) 4091 #define BNX_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4092 #define BNX_RXP_CPU_STATE_INTERRRUPT (1L<<12) 4093 #define BNX_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4094 #define BNX_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4095 #define BNX_RXP_CPU_STATE_BLOCKED_READ (1L<<31) 4096 4097 #define BNX_RXP_CPU_EVENT_MASK 0x000c5008 4098 #define BNX_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4099 #define BNX_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4100 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4101 #define BNX_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4102 #define BNX_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4103 #define BNX_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4104 #define BNX_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4105 #define BNX_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4106 #define BNX_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4107 #define BNX_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4108 #define BNX_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4109 4110 #define BNX_RXP_CPU_PROGRAM_COUNTER 0x000c501c 4111 #define BNX_RXP_CPU_INSTRUCTION 0x000c5020 4112 #define BNX_RXP_CPU_DATA_ACCESS 0x000c5024 4113 #define BNX_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 4114 #define BNX_RXP_CPU_INTERRUPT_VECTOR 0x000c502c 4115 #define BNX_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 4116 #define BNX_RXP_CPU_HW_BREAKPOINT 0x000c5034 4117 #define BNX_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4118 #define BNX_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4119 4120 #define BNX_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 4121 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4122 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4123 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4124 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4125 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4126 #define BNX_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4127 4128 #define BNX_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 4129 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4130 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4131 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4132 #define BNX_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4133 4134 #define BNX_RXP_CPU_REG_FILE 0x000c5200 4135 #define BNX_RXP_CFTQ_DATA 0x000c5380 4136 #define BNX_RXP_CFTQ_CMD 0x000c53b8 4137 #define BNX_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) 4138 #define BNX_RXP_CFTQ_CMD_WR_TOP (1L<<10) 4139 #define BNX_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) 4140 #define BNX_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) 4141 #define BNX_RXP_CFTQ_CMD_SFT_RESET (1L<<25) 4142 #define BNX_RXP_CFTQ_CMD_RD_DATA (1L<<26) 4143 #define BNX_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) 4144 #define BNX_RXP_CFTQ_CMD_ADD_DATA (1L<<28) 4145 #define BNX_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) 4146 #define BNX_RXP_CFTQ_CMD_POP (1L<<30) 4147 #define BNX_RXP_CFTQ_CMD_BUSY (1L<<31) 4148 4149 #define BNX_RXP_CFTQ_CTL 0x000c53bc 4150 #define BNX_RXP_CFTQ_CTL_INTERVENE (1L<<0) 4151 #define BNX_RXP_CFTQ_CTL_OVERFLOW (1L<<1) 4152 #define BNX_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2) 4153 #define BNX_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4154 #define BNX_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4155 4156 #define BNX_RXP_FTQ_DATA 0x000c53c0 4157 #define BNX_RXP_FTQ_CMD 0x000c53f8 4158 #define BNX_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) 4159 #define BNX_RXP_FTQ_CMD_WR_TOP (1L<<10) 4160 #define BNX_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) 4161 #define BNX_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) 4162 #define BNX_RXP_FTQ_CMD_SFT_RESET (1L<<25) 4163 #define BNX_RXP_FTQ_CMD_RD_DATA (1L<<26) 4164 #define BNX_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) 4165 #define BNX_RXP_FTQ_CMD_ADD_DATA (1L<<28) 4166 #define BNX_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) 4167 #define BNX_RXP_FTQ_CMD_POP (1L<<30) 4168 #define BNX_RXP_FTQ_CMD_BUSY (1L<<31) 4169 4170 #define BNX_RXP_FTQ_CTL 0x000c53fc 4171 #define BNX_RXP_FTQ_CTL_INTERVENE (1L<<0) 4172 #define BNX_RXP_FTQ_CTL_OVERFLOW (1L<<1) 4173 #define BNX_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4174 #define BNX_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4175 #define BNX_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4176 4177 #define BNX_RXP_SCRATCH 0x000e0000 4178 4179 4180 /* 4181 * com_reg definition 4182 * offset: 0x100000 4183 */ 4184 #define BNX_COM_CPU_MODE 0x00105000 4185 #define BNX_COM_CPU_MODE_LOCAL_RST (1L<<0) 4186 #define BNX_COM_CPU_MODE_STEP_ENA (1L<<1) 4187 #define BNX_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4188 #define BNX_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4189 #define BNX_COM_CPU_MODE_MSG_BIT1 (1L<<6) 4190 #define BNX_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) 4191 #define BNX_COM_CPU_MODE_SOFT_HALT (1L<<10) 4192 #define BNX_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4193 #define BNX_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4194 #define BNX_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4195 #define BNX_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4196 4197 #define BNX_COM_CPU_STATE 0x00105004 4198 #define BNX_COM_CPU_STATE_BREAKPOINT (1L<<0) 4199 #define BNX_COM_CPU_STATE_BAD_INST_HALTED (1L<<2) 4200 #define BNX_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4201 #define BNX_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4202 #define BNX_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4203 #define BNX_COM_CPU_STATE_BAD_pc_HALTED (1L<<6) 4204 #define BNX_COM_CPU_STATE_ALIGN_HALTED (1L<<7) 4205 #define BNX_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4206 #define BNX_COM_CPU_STATE_SOFT_HALTED (1L<<10) 4207 #define BNX_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4208 #define BNX_COM_CPU_STATE_INTERRRUPT (1L<<12) 4209 #define BNX_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4210 #define BNX_COM_CPU_STATE_INST_FETCH_STALL (1L<<15) 4211 #define BNX_COM_CPU_STATE_BLOCKED_READ (1L<<31) 4212 4213 #define BNX_COM_CPU_EVENT_MASK 0x00105008 4214 #define BNX_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4215 #define BNX_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4216 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4217 #define BNX_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4218 #define BNX_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4219 #define BNX_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4220 #define BNX_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4221 #define BNX_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4222 #define BNX_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4223 #define BNX_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4224 #define BNX_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4225 4226 #define BNX_COM_CPU_PROGRAM_COUNTER 0x0010501c 4227 #define BNX_COM_CPU_INSTRUCTION 0x00105020 4228 #define BNX_COM_CPU_DATA_ACCESS 0x00105024 4229 #define BNX_COM_CPU_INTERRUPT_ENABLE 0x00105028 4230 #define BNX_COM_CPU_INTERRUPT_VECTOR 0x0010502c 4231 #define BNX_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 4232 #define BNX_COM_CPU_HW_BREAKPOINT 0x00105034 4233 #define BNX_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4234 #define BNX_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4235 4236 #define BNX_COM_CPU_DEBUG_VECT_PEEK 0x00105038 4237 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4238 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4239 #define BNX_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4240 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4241 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4242 #define BNX_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4243 4244 #define BNX_COM_CPU_LAST_BRANCH_ADDR 0x00105048 4245 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4246 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4247 #define BNX_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4248 #define BNX_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4249 4250 #define BNX_COM_CPU_REG_FILE 0x00105200 4251 #define BNX_COM_COMXQ_FTQ_DATA 0x00105340 4252 #define BNX_COM_COMXQ_FTQ_CMD 0x00105378 4253 #define BNX_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4254 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) 4255 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4256 #define BNX_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4257 #define BNX_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25) 4258 #define BNX_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) 4259 #define BNX_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4260 #define BNX_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) 4261 #define BNX_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4262 #define BNX_COM_COMXQ_FTQ_CMD_POP (1L<<30) 4263 #define BNX_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) 4264 4265 #define BNX_COM_COMXQ_FTQ_CTL 0x0010537c 4266 #define BNX_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0) 4267 #define BNX_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) 4268 #define BNX_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4269 #define BNX_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4270 #define BNX_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4271 4272 #define BNX_COM_COMTQ_FTQ_DATA 0x00105380 4273 #define BNX_COM_COMTQ_FTQ_CMD 0x001053b8 4274 #define BNX_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4275 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) 4276 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4277 #define BNX_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4278 #define BNX_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25) 4279 #define BNX_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) 4280 #define BNX_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4281 #define BNX_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) 4282 #define BNX_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4283 #define BNX_COM_COMTQ_FTQ_CMD_POP (1L<<30) 4284 #define BNX_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) 4285 4286 #define BNX_COM_COMTQ_FTQ_CTL 0x001053bc 4287 #define BNX_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0) 4288 #define BNX_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) 4289 #define BNX_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4290 #define BNX_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4291 #define BNX_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4292 4293 #define BNX_COM_COMQ_FTQ_DATA 0x001053c0 4294 #define BNX_COM_COMQ_FTQ_CMD 0x001053f8 4295 #define BNX_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4296 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) 4297 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4298 #define BNX_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4299 #define BNX_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) 4300 #define BNX_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) 4301 #define BNX_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4302 #define BNX_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) 4303 #define BNX_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4304 #define BNX_COM_COMQ_FTQ_CMD_POP (1L<<30) 4305 #define BNX_COM_COMQ_FTQ_CMD_BUSY (1L<<31) 4306 4307 #define BNX_COM_COMQ_FTQ_CTL 0x001053fc 4308 #define BNX_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) 4309 #define BNX_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) 4310 #define BNX_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4311 #define BNX_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4312 #define BNX_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4313 4314 #define BNX_COM_SCRATCH 0x00120000 4315 4316 4317 /* 4318 * cp_reg definition 4319 * offset: 0x180000 4320 */ 4321 #define BNX_CP_CPU_MODE 0x00185000 4322 #define BNX_CP_CPU_MODE_LOCAL_RST (1L<<0) 4323 #define BNX_CP_CPU_MODE_STEP_ENA (1L<<1) 4324 #define BNX_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4325 #define BNX_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4326 #define BNX_CP_CPU_MODE_MSG_BIT1 (1L<<6) 4327 #define BNX_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4328 #define BNX_CP_CPU_MODE_SOFT_HALT (1L<<10) 4329 #define BNX_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4330 #define BNX_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4331 #define BNX_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4332 #define BNX_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4333 4334 #define BNX_CP_CPU_STATE 0x00185004 4335 #define BNX_CP_CPU_STATE_BREAKPOINT (1L<<0) 4336 #define BNX_CP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4337 #define BNX_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4338 #define BNX_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4339 #define BNX_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4340 #define BNX_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4341 #define BNX_CP_CPU_STATE_ALIGN_HALTED (1L<<7) 4342 #define BNX_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4343 #define BNX_CP_CPU_STATE_SOFT_HALTED (1L<<10) 4344 #define BNX_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4345 #define BNX_CP_CPU_STATE_INTERRRUPT (1L<<12) 4346 #define BNX_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4347 #define BNX_CP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4348 #define BNX_CP_CPU_STATE_BLOCKED_READ (1L<<31) 4349 4350 #define BNX_CP_CPU_EVENT_MASK 0x00185008 4351 #define BNX_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4352 #define BNX_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4353 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4354 #define BNX_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4355 #define BNX_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4356 #define BNX_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4357 #define BNX_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4358 #define BNX_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4359 #define BNX_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4360 #define BNX_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4361 #define BNX_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4362 4363 #define BNX_CP_CPU_PROGRAM_COUNTER 0x0018501c 4364 #define BNX_CP_CPU_INSTRUCTION 0x00185020 4365 #define BNX_CP_CPU_DATA_ACCESS 0x00185024 4366 #define BNX_CP_CPU_INTERRUPT_ENABLE 0x00185028 4367 #define BNX_CP_CPU_INTERRUPT_VECTOR 0x0018502c 4368 #define BNX_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 4369 #define BNX_CP_CPU_HW_BREAKPOINT 0x00185034 4370 #define BNX_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4371 #define BNX_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4372 4373 #define BNX_CP_CPU_DEBUG_VECT_PEEK 0x00185038 4374 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4375 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4376 #define BNX_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4377 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4378 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4379 #define BNX_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4380 4381 #define BNX_CP_CPU_LAST_BRANCH_ADDR 0x00185048 4382 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4383 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4384 #define BNX_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4385 #define BNX_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4386 4387 #define BNX_CP_CPU_REG_FILE 0x00185200 4388 #define BNX_CP_CPQ_FTQ_DATA 0x001853c0 4389 #define BNX_CP_CPQ_FTQ_CMD 0x001853f8 4390 #define BNX_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4391 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) 4392 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4393 #define BNX_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4394 #define BNX_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) 4395 #define BNX_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) 4396 #define BNX_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4397 #define BNX_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) 4398 #define BNX_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4399 #define BNX_CP_CPQ_FTQ_CMD_POP (1L<<30) 4400 #define BNX_CP_CPQ_FTQ_CMD_BUSY (1L<<31) 4401 4402 #define BNX_CP_CPQ_FTQ_CTL 0x001853fc 4403 #define BNX_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) 4404 #define BNX_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) 4405 #define BNX_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4406 #define BNX_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4407 #define BNX_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4408 4409 #define BNX_CP_SCRATCH 0x001a0000 4410 4411 4412 /* 4413 * mcp_reg definition 4414 * offset: 0x140000 4415 */ 4416 #define BNX_MCP_CPU_MODE 0x00145000 4417 #define BNX_MCP_CPU_MODE_LOCAL_RST (1L<<0) 4418 #define BNX_MCP_CPU_MODE_STEP_ENA (1L<<1) 4419 #define BNX_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2) 4420 #define BNX_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3) 4421 #define BNX_MCP_CPU_MODE_MSG_BIT1 (1L<<6) 4422 #define BNX_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) 4423 #define BNX_MCP_CPU_MODE_SOFT_HALT (1L<<10) 4424 #define BNX_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11) 4425 #define BNX_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12) 4426 #define BNX_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13) 4427 #define BNX_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15) 4428 4429 #define BNX_MCP_CPU_STATE 0x00145004 4430 #define BNX_MCP_CPU_STATE_BREAKPOINT (1L<<0) 4431 #define BNX_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2) 4432 #define BNX_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3) 4433 #define BNX_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4) 4434 #define BNX_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5) 4435 #define BNX_MCP_CPU_STATE_BAD_pc_HALTED (1L<<6) 4436 #define BNX_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) 4437 #define BNX_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8) 4438 #define BNX_MCP_CPU_STATE_SOFT_HALTED (1L<<10) 4439 #define BNX_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11) 4440 #define BNX_MCP_CPU_STATE_INTERRRUPT (1L<<12) 4441 #define BNX_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14) 4442 #define BNX_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15) 4443 #define BNX_MCP_CPU_STATE_BLOCKED_READ (1L<<31) 4444 4445 #define BNX_MCP_CPU_EVENT_MASK 0x00145008 4446 #define BNX_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0) 4447 #define BNX_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2) 4448 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3) 4449 #define BNX_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4) 4450 #define BNX_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5) 4451 #define BNX_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6) 4452 #define BNX_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7) 4453 #define BNX_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8) 4454 #define BNX_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10) 4455 #define BNX_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11) 4456 #define BNX_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12) 4457 4458 #define BNX_MCP_CPU_PROGRAM_COUNTER 0x0014501c 4459 #define BNX_MCP_CPU_INSTRUCTION 0x00145020 4460 #define BNX_MCP_CPU_DATA_ACCESS 0x00145024 4461 #define BNX_MCP_CPU_INTERRUPT_ENABLE 0x00145028 4462 #define BNX_MCP_CPU_INTERRUPT_VECTOR 0x0014502c 4463 #define BNX_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 4464 #define BNX_MCP_CPU_HW_BREAKPOINT 0x00145034 4465 #define BNX_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0) 4466 #define BNX_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2) 4467 4468 #define BNX_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 4469 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) 4470 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11) 4471 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) 4472 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) 4473 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27) 4474 #define BNX_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) 4475 4476 #define BNX_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 4477 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1) 4478 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1) 4479 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1) 4480 #define BNX_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2) 4481 4482 #define BNX_MCP_CPU_REG_FILE 0x00145200 4483 #define BNX_MCP_MCPQ_FTQ_DATA 0x001453c0 4484 #define BNX_MCP_MCPQ_FTQ_CMD 0x001453f8 4485 #define BNX_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) 4486 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) 4487 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) 4488 #define BNX_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) 4489 #define BNX_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) 4490 #define BNX_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) 4491 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27) 4492 #define BNX_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) 4493 #define BNX_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29) 4494 #define BNX_MCP_MCPQ_FTQ_CMD_POP (1L<<30) 4495 #define BNX_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) 4496 4497 #define BNX_MCP_MCPQ_FTQ_CTL 0x001453fc 4498 #define BNX_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) 4499 #define BNX_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) 4500 #define BNX_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2) 4501 #define BNX_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) 4502 #define BNX_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) 4503 4504 #define BNX_MCP_ROM 0x00150000 4505 #define BNX_MCP_SCRATCH 0x00160000 4506 4507 #define BNX_SHM_HDR_SIGNATURE BNX_MCP_SCRATCH 4508 #define BNX_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 4509 #define BNX_SHM_HDR_SIGNATURE_SIG 0x53530000 4510 #define BNX_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff 4511 #define BNX_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 4512 4513 #define BNX_SHM_HDR_ADDR_0 BNX_MCP_SCRATCH + 4 4514 #define BNX_SHM_HDR_ADDR_1 BNX_MCP_SCRATCH + 8 4515 4516 /****************************************************************************/ 4517 /* End machine generated definitions. */ 4518 /****************************************************************************/ 4519 4520 #define NUM_MC_HASH_REGISTERS 8 4521 4522 4523 /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */ 4524 #define PHY_BCM5706_PHY_ID 0x00206160 4525 4526 #define PHY_ID(id) ((id) & 0xfffffff0) 4527 #define PHY_REV_ID(id) ((id) & 0xf) 4528 4529 /* 5708 Serdes PHY registers */ 4530 4531 #define BCM5708S_UP1 0xb 4532 4533 #define BCM5708S_UP1_2G5 0x1 4534 4535 #define BCM5708S_BLK_ADDR 0x1f 4536 4537 #define BCM5708S_BLK_ADDR_DIG 0x0000 4538 #define BCM5708S_BLK_ADDR_DIG3 0x0002 4539 #define BCM5708S_BLK_ADDR_TX_MISC 0x0005 4540 4541 /* Digital Block */ 4542 #define BCM5708S_1000X_CTL1 0x10 4543 4544 #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001 4545 #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010 4546 4547 #define BCM5708S_1000X_CTL2 0x11 4548 4549 #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001 4550 4551 #define BCM5708S_1000X_STAT1 0x14 4552 4553 #define BCM5708S_1000X_STAT1_SGMII 0x0001 4554 #define BCM5708S_1000X_STAT1_LINK 0x0002 4555 #define BCM5708S_1000X_STAT1_FD 0x0004 4556 #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018 4557 #define BCM5708S_1000X_STAT1_SPEED_10 0x0000 4558 #define BCM5708S_1000X_STAT1_SPEED_100 0x0008 4559 #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010 4560 #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 4561 #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020 4562 #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040 4563 4564 /* Digital3 Block */ 4565 #define BCM5708S_DIG_3_0 0x10 4566 4567 #define BCM5708S_DIG_3_0_USE_IEEE 0x0001 4568 4569 /* Tx/Misc Block */ 4570 #define BCM5708S_TX_ACTL1 0x15 4571 4572 #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30 4573 4574 #define BCM5708S_TX_ACTL3 0x17 4575 4576 #define RX_COPY_THRESH 92 4577 4578 #define DMA_READ_CHANS 5 4579 #define DMA_WRITE_CHANS 3 4580 4581 /* Use the natural page size of the host CPU. */ 4582 #define BCM_PAGE_BITS PAGE_SHIFT 4583 #define BCM_PAGE_SIZE PAGE_SIZE 4584 4585 #define TX_PAGES 2 4586 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd)) 4587 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) 4588 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES) 4589 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES) 4590 #define MAX_TX_BD (TOTAL_TX_BD - 1) 4591 4592 #define RX_PAGES 2 4593 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd)) 4594 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1) 4595 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES) 4596 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES) 4597 #define MAX_RX_BD (TOTAL_RX_BD - 1) 4598 4599 #define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \ 4600 (USABLE_TX_BD_PER_PAGE - 1)) ? \ 4601 (x) + 2 : (x) + 1 4602 4603 #define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD) 4604 4605 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 4606 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE) 4607 4608 #define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \ 4609 (USABLE_RX_BD_PER_PAGE - 1)) ? \ 4610 (x) + 2 : (x) + 1 4611 4612 #define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD) 4613 4614 #define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4)) 4615 #define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE) 4616 4617 /* Context size. */ 4618 #define CTX_SHIFT 7 4619 #define CTX_SIZE (1 << CTX_SHIFT) 4620 #define CTX_MASK (CTX_SIZE - 1) 4621 #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT) 4622 #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT) 4623 4624 #define PHY_CTX_SHIFT 6 4625 #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT) 4626 #define PHY_CTX_MASK (PHY_CTX_SIZE - 1) 4627 #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT) 4628 #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT) 4629 4630 #define MB_KERNEL_CTX_SHIFT 8 4631 #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 4632 #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) 4633 #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT)) 4634 4635 #define MAX_CID_CNT 0x4000 4636 #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) 4637 #define INVALID_CID_ADDR 0xffffffff 4638 4639 #define TX_CID 16 4640 #define RX_CID 0 4641 4642 #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) 4643 #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) 4644 4645 /****************************************************************************/ 4646 /* BNX Processor Firmware Load Definitions */ 4647 /****************************************************************************/ 4648 4649 struct cpu_reg { 4650 u_int32_t mode; 4651 u_int32_t mode_value_halt; 4652 u_int32_t mode_value_sstep; 4653 4654 u_int32_t state; 4655 u_int32_t state_value_clear; 4656 4657 u_int32_t gpr0; 4658 u_int32_t evmask; 4659 u_int32_t pc; 4660 u_int32_t inst; 4661 u_int32_t bp; 4662 4663 u_int32_t spad_base; 4664 4665 u_int32_t mips_view_base; 4666 }; 4667 4668 struct fw_info { 4669 u_int32_t ver_major; 4670 u_int32_t ver_minor; 4671 u_int32_t ver_fix; 4672 4673 u_int32_t start_addr; 4674 4675 /* Text section. */ 4676 u_int32_t text_addr; 4677 u_int32_t text_len; 4678 u_int32_t text_index; 4679 u_int32_t *text; 4680 4681 /* Data section. */ 4682 u_int32_t data_addr; 4683 u_int32_t data_len; 4684 u_int32_t data_index; 4685 u_int32_t *data; 4686 4687 /* SBSS section. */ 4688 u_int32_t sbss_addr; 4689 u_int32_t sbss_len; 4690 u_int32_t sbss_index; 4691 u_int32_t *sbss; 4692 4693 /* BSS section. */ 4694 u_int32_t bss_addr; 4695 u_int32_t bss_len; 4696 u_int32_t bss_index; 4697 u_int32_t *bss; 4698 4699 /* Read-only section. */ 4700 u_int32_t rodata_addr; 4701 u_int32_t rodata_len; 4702 u_int32_t rodata_index; 4703 u_int32_t *rodata; 4704 }; 4705 4706 #define RV2P_PROC1 0 4707 #define RV2P_PROC2 1 4708 4709 #define BNX_MIREG(x) ((x & 0x1F) << 16) 4710 #define BNX_MIPHY(x) ((x & 0x1F) << 21) 4711 #define BNX_PHY_TIMEOUT 50 4712 4713 #define BNX_NVRAM_SIZE 0x200 4714 #define BNX_NVRAM_MAGIC 0x669955aa 4715 #define BNX_CRC32_RESIDUAL 0xdebb20e3 4716 4717 #define BNX_TX_TIMEOUT 5 4718 4719 #define BNX_MAX_SEGMENTS 8 4720 #define BNX_DMA_ALIGN 8 4721 #define BNX_DMA_BOUNDARY 0 4722 4723 #define BNX_MIN_MTU 60 4724 #define BNX_MIN_ETHER_MTU 64 4725 4726 #define BNX_MAX_STD_MTU 1500 4727 #define BNX_MAX_STD_ETHER_MTU 1518 4728 #define BNX_MAX_STD_ETHER_MTU_VLAN 1522 4729 4730 #define BNX_MAX_JUMBO_MTU 9000 4731 #define BNX_MAX_JUMBO_ETHER_MTU 9018 4732 #define BNX_MAX_JUMBO_ETHER_MTU_VLAN 9022 4733 4734 #define BNX_MAX_MRU MCLBYTES 4735 #define BNX_MAX_JUMBO_MRU 9216 4736 4737 /****************************************************************************/ 4738 /* BNX Device State Data Structure */ 4739 /****************************************************************************/ 4740 4741 #define BNX_STATUS_BLK_SZ sizeof(struct status_block) 4742 #define BNX_STATS_BLK_SZ sizeof(struct statistics_block) 4743 #define BNX_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4744 #define BNX_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE 4745 4746 struct bnx_pkt { 4747 TAILQ_ENTRY(bnx_pkt) pkt_entry; 4748 bus_dmamap_t pkt_dmamap; 4749 struct mbuf *pkt_mbuf; 4750 u_int16_t pkt_end_desc; 4751 }; 4752 4753 TAILQ_HEAD(bnx_pkt_list, bnx_pkt); 4754 4755 struct bnx_softc { 4756 struct device bnx_dev; /* Parent device handle */ 4757 struct arpcom arpcom; 4758 4759 struct pci_attach_args bnx_pa; 4760 pci_intr_handle_t bnx_ih; 4761 4762 bus_space_tag_t bnx_btag; /* Device bus tag */ 4763 bus_space_handle_t bnx_bhandle; /* Device bus handle */ 4764 bus_size_t bnx_size; 4765 4766 void *bnx_intrhand; /* Interrupt handler */ 4767 4768 /* ASIC Chip ID. */ 4769 u_int32_t bnx_chipid; 4770 4771 /* General controller flags. */ 4772 u_int32_t bnx_flags; 4773 #define BNX_PCIX_FLAG 0x01 4774 #define BNX_PCI_32BIT_FLAG 0x02 4775 #define BNX_ONE_TDMA_FLAG 0x04 /* Deprecated */ 4776 #define BNX_NO_WOL_FLAG 0x08 4777 #define BNX_USING_DAC_FLAG 0x10 4778 #define BNX_USING_MSI_FLAG 0x20 4779 #define BNX_MFW_ENABLE_FLAG 0x40 4780 #define BNX_ACTIVE_FLAG 0x80 4781 4782 /* PHY specific flags. */ 4783 u_int32_t bnx_phy_flags; 4784 #define BNX_PHY_SERDES_FLAG 0x001 4785 #define BNX_PHY_CRC_FIX_FLAG 0x002 4786 #define BNX_PHY_PARALLEL_DETECT_FLAG 0x004 4787 #define BNX_PHY_2_5G_CAPABLE_FLAG 0x008 4788 #define BNX_PHY_INT_MODE_MASK_FLAG 0x300 4789 #define BNX_PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 4790 #define BNX_PHY_INT_MODE_LINK_READY_FLAG 0x200 4791 #define BNX_PHY_IEEE_CLAUSE_45_FLAG 0x400 4792 4793 /* Values that need to be shared with the PHY driver. */ 4794 u_int32_t bnx_shared_hw_cfg; 4795 u_int32_t bnx_port_hw_cfg; 4796 4797 uint64_t bnx_flowflags; 4798 4799 u_int16_t bus_speed_mhz; /* PCI bus speed */ 4800 struct flash_spec *bnx_flash_info; /* Flash NVRAM settings */ 4801 u_int32_t bnx_flash_size; /* Flash NVRAM size */ 4802 u_int32_t bnx_shmem_base; /* ShMem base address */ 4803 char * bnx_name; /* Name string */ 4804 4805 /* Tracks the version of bootcode firmware. */ 4806 u_int32_t bnx_fw_ver; 4807 4808 /* Tracks the state of the firmware. 0 = Running while any */ 4809 /* other value indicates that the firmware is not responding. */ 4810 u_int16_t bnx_fw_timed_out; 4811 4812 /* An incrementing sequence used to coordinate messages passed */ 4813 /* from the driver to the firmware. */ 4814 u_int16_t bnx_fw_wr_seq; 4815 4816 /* An incrementing sequence used to let the firmware know that */ 4817 /* the driver is still operating. Without the pulse, management */ 4818 /* firmware such as IPMI or UMP will operate in OS absent state. */ 4819 u_int16_t bnx_fw_drv_pulse_wr_seq; 4820 4821 /* Ethernet MAC address. */ 4822 u_char eaddr[6]; 4823 4824 /* These setting are used by the host coalescing (HC) block to */ 4825 /* to control how often the status block, statistics block and */ 4826 /* interrupts are generated. */ 4827 u_int16_t bnx_tx_quick_cons_trip_int; 4828 u_int16_t bnx_tx_quick_cons_trip; 4829 u_int16_t bnx_rx_quick_cons_trip_int; 4830 u_int16_t bnx_rx_quick_cons_trip; 4831 u_int16_t bnx_comp_prod_trip_int; 4832 u_int16_t bnx_comp_prod_trip; 4833 u_int16_t bnx_tx_ticks_int; 4834 u_int16_t bnx_tx_ticks; 4835 u_int16_t bnx_rx_ticks_int; 4836 u_int16_t bnx_rx_ticks; 4837 u_int16_t bnx_com_ticks_int; 4838 u_int16_t bnx_com_ticks; 4839 u_int16_t bnx_cmd_ticks_int; 4840 u_int16_t bnx_cmd_ticks; 4841 u_int32_t bnx_stats_ticks; 4842 4843 /* The address of the integrated PHY on the MII bus. */ 4844 int bnx_phy_addr; 4845 4846 /* The device handle for the MII bus child device. */ 4847 struct mii_data bnx_mii; 4848 4849 /* Driver maintained TX chain pointers and byte counter. */ 4850 u_int16_t rx_prod; 4851 u_int16_t rx_cons; 4852 u_int32_t rx_prod_bseq; /* Counts the bytes used. */ 4853 u_int16_t tx_prod; 4854 u_int16_t tx_cons; 4855 u_int32_t tx_prod_bseq; /* Counts the bytes used. */ 4856 4857 int bnx_link; 4858 struct timeout bnx_timeout; 4859 struct timeout bnx_rxrefill; 4860 4861 /* Frame size and mbuf allocation size for RX frames. */ 4862 u_int32_t max_frame_size; 4863 int mbuf_alloc_size; 4864 4865 /* Receive mode settings (i.e promiscuous, multicast, etc.). */ 4866 u_int32_t rx_mode; 4867 4868 /* Bus tag for the bnx controller. */ 4869 bus_dma_tag_t bnx_dmatag; 4870 4871 /* H/W maintained TX buffer descriptor chain structure. */ 4872 bus_dma_segment_t tx_bd_chain_seg[TX_PAGES]; 4873 int tx_bd_chain_rseg[TX_PAGES]; 4874 bus_dmamap_t tx_bd_chain_map[TX_PAGES]; 4875 struct tx_bd *tx_bd_chain[TX_PAGES]; 4876 bus_addr_t tx_bd_chain_paddr[TX_PAGES]; 4877 4878 /* H/W maintained RX buffer descriptor chain structure. */ 4879 bus_dma_segment_t rx_bd_chain_seg[TX_PAGES]; 4880 int rx_bd_chain_rseg[TX_PAGES]; 4881 bus_dmamap_t rx_bd_chain_map[RX_PAGES]; 4882 struct rx_bd *rx_bd_chain[RX_PAGES]; 4883 bus_addr_t rx_bd_chain_paddr[RX_PAGES]; 4884 4885 /* H/W maintained status block. */ 4886 bus_dma_segment_t status_seg; 4887 int status_rseg; 4888 bus_dmamap_t status_map; 4889 struct status_block *status_block; /* virtual address */ 4890 bus_addr_t status_block_paddr; /* Physical address */ 4891 4892 /* H/W maintained context block */ 4893 int ctx_pages; 4894 bus_dma_segment_t ctx_segs[4]; 4895 int ctx_rsegs[4]; 4896 bus_dmamap_t ctx_map[4]; 4897 void *ctx_block[4]; 4898 4899 4900 /* Driver maintained status block values. */ 4901 u_int16_t last_status_idx; 4902 u_int16_t hw_rx_cons; 4903 u_int16_t hw_tx_cons; 4904 4905 /* H/W maintained statistics block. */ 4906 bus_dma_segment_t stats_seg; 4907 int stats_rseg; 4908 bus_dmamap_t stats_map; 4909 struct statistics_block *stats_block; /* Virtual address */ 4910 bus_addr_t stats_block_paddr; /* Physical address */ 4911 4912 /* Bus tag for RX/TX mbufs. */ 4913 bus_dma_segment_t rx_mbuf_seg; 4914 int rx_mbuf_rseg; 4915 bus_dma_segment_t tx_mbuf_seg; 4916 int tx_mbuf_rseg; 4917 4918 /* S/W maintained mbuf TX chain structure. */ 4919 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD]; 4920 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD]; 4921 4922 /* S/W maintained mbuf RX chain structure. */ 4923 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD]; 4924 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD]; 4925 4926 /* Track the number of rx_bd and tx_bd's in use. */ 4927 struct if_rxring rx_ring; 4928 u_int16_t max_rx_bd; 4929 int used_tx_bd; 4930 u_int16_t max_tx_bd; 4931 4932 /* Provides access to hardware statistics through sysctl. */ 4933 u_int64_t stat_IfHCInOctets; 4934 u_int64_t stat_IfHCInBadOctets; 4935 u_int64_t stat_IfHCOutOctets; 4936 u_int64_t stat_IfHCOutBadOctets; 4937 u_int64_t stat_IfHCInUcastPkts; 4938 u_int64_t stat_IfHCInMulticastPkts; 4939 u_int64_t stat_IfHCInBroadcastPkts; 4940 u_int64_t stat_IfHCOutUcastPkts; 4941 u_int64_t stat_IfHCOutMulticastPkts; 4942 u_int64_t stat_IfHCOutBroadcastPkts; 4943 4944 u_int32_t stat_emac_tx_stat_dot3statsinternalmactransmiterrors; 4945 u_int32_t stat_Dot3StatsCarrierSenseErrors; 4946 u_int32_t stat_Dot3StatsFCSErrors; 4947 u_int32_t stat_Dot3StatsAlignmentErrors; 4948 u_int32_t stat_Dot3StatsSingleCollisionFrames; 4949 u_int32_t stat_Dot3StatsMultipleCollisionFrames; 4950 u_int32_t stat_Dot3StatsDeferredTransmissions; 4951 u_int32_t stat_Dot3StatsExcessiveCollisions; 4952 u_int32_t stat_Dot3StatsLateCollisions; 4953 u_int32_t stat_EtherStatsCollisions; 4954 u_int32_t stat_EtherStatsFragments; 4955 u_int32_t stat_EtherStatsJabbers; 4956 u_int32_t stat_EtherStatsUndersizePkts; 4957 u_int32_t stat_EtherStatsOverrsizePkts; 4958 u_int32_t stat_EtherStatsPktsRx64Octets; 4959 u_int32_t stat_EtherStatsPktsRx65Octetsto127Octets; 4960 u_int32_t stat_EtherStatsPktsRx128Octetsto255Octets; 4961 u_int32_t stat_EtherStatsPktsRx256Octetsto511Octets; 4962 u_int32_t stat_EtherStatsPktsRx512Octetsto1023Octets; 4963 u_int32_t stat_EtherStatsPktsRx1024Octetsto1522Octets; 4964 u_int32_t stat_EtherStatsPktsRx1523Octetsto9022Octets; 4965 u_int32_t stat_EtherStatsPktsTx64Octets; 4966 u_int32_t stat_EtherStatsPktsTx65Octetsto127Octets; 4967 u_int32_t stat_EtherStatsPktsTx128Octetsto255Octets; 4968 u_int32_t stat_EtherStatsPktsTx256Octetsto511Octets; 4969 u_int32_t stat_EtherStatsPktsTx512Octetsto1023Octets; 4970 u_int32_t stat_EtherStatsPktsTx1024Octetsto1522Octets; 4971 u_int32_t stat_EtherStatsPktsTx1523Octetsto9022Octets; 4972 u_int32_t stat_XonPauseFramesReceived; 4973 u_int32_t stat_XoffPauseFramesReceived; 4974 u_int32_t stat_OutXonSent; 4975 u_int32_t stat_OutXoffSent; 4976 u_int32_t stat_FlowControlDone; 4977 u_int32_t stat_MacControlFramesReceived; 4978 u_int32_t stat_XoffStateEntered; 4979 u_int32_t stat_IfInFramesL2FilterDiscards; 4980 u_int32_t stat_IfInRuleCheckerDiscards; 4981 u_int32_t stat_IfInFTQDiscards; 4982 u_int32_t stat_IfInMBUFDiscards; 4983 u_int32_t stat_IfInRuleCheckerP4Hit; 4984 u_int32_t stat_CatchupInRuleCheckerDiscards; 4985 u_int32_t stat_CatchupInFTQDiscards; 4986 u_int32_t stat_CatchupInMBUFDiscards; 4987 u_int32_t stat_CatchupInRuleCheckerP4Hit; 4988 4989 /* Mbuf allocation failure counter. */ 4990 u_int32_t mbuf_alloc_failed; 4991 4992 /* TX DMA mapping failure counter. */ 4993 u_int32_t tx_dma_map_failures; 4994 4995 #ifdef BNX_DEBUG 4996 /* Track the number of enqueued mbufs. */ 4997 int tx_mbuf_alloc; 4998 int rx_mbuf_alloc; 4999 5000 /* Track the distribution buffer segments. */ 5001 u_int32_t rx_mbuf_segs[BNX_MAX_SEGMENTS+1]; 5002 5003 /* Track how many and what type of interrupts are generated. */ 5004 u_int32_t interrupts_generated; 5005 u_int32_t interrupts_handled; 5006 u_int32_t rx_interrupts; 5007 u_int32_t tx_interrupts; 5008 5009 u_int32_t rx_low_watermark; /* Lowest number of rx_bd's free. */ 5010 u_int32_t rx_empty_count; /* Number of times the RX chain was empty. */ 5011 u_int32_t tx_hi_watermark; /* Greatest number of tx_bd's used. */ 5012 u_int32_t tx_full_count; /* Number of times the TX chain was full. */ 5013 u_int32_t mbuf_sim_alloc_failed; /* Mbuf simulated allocation failure counter. */ 5014 u_int32_t l2fhdr_status_errors; 5015 u_int32_t unexpected_attentions; 5016 u_int32_t lost_status_block_updates; 5017 #endif 5018 }; 5019 5020 #endif /* _KERNEL */ 5021 5022 struct bnx_firmware_header { 5023 int bnx_COM_FwReleaseMajor; 5024 int bnx_COM_FwReleaseMinor; 5025 int bnx_COM_FwReleaseFix; 5026 u_int32_t bnx_COM_FwStartAddr; 5027 u_int32_t bnx_COM_FwTextAddr; 5028 int bnx_COM_FwTextLen; 5029 u_int32_t bnx_COM_FwDataAddr; 5030 int bnx_COM_FwDataLen; 5031 u_int32_t bnx_COM_FwRodataAddr; 5032 int bnx_COM_FwRodataLen; 5033 u_int32_t bnx_COM_FwBssAddr; 5034 int bnx_COM_FwBssLen; 5035 u_int32_t bnx_COM_FwSbssAddr; 5036 int bnx_COM_FwSbssLen; 5037 5038 int bnx_RXP_FwReleaseMajor; 5039 int bnx_RXP_FwReleaseMinor; 5040 int bnx_RXP_FwReleaseFix; 5041 u_int32_t bnx_RXP_FwStartAddr; 5042 u_int32_t bnx_RXP_FwTextAddr; 5043 int bnx_RXP_FwTextLen; 5044 u_int32_t bnx_RXP_FwDataAddr; 5045 int bnx_RXP_FwDataLen; 5046 u_int32_t bnx_RXP_FwRodataAddr; 5047 int bnx_RXP_FwRodataLen; 5048 u_int32_t bnx_RXP_FwBssAddr; 5049 int bnx_RXP_FwBssLen; 5050 u_int32_t bnx_RXP_FwSbssAddr; 5051 int bnx_RXP_FwSbssLen; 5052 5053 int bnx_TPAT_FwReleaseMajor; 5054 int bnx_TPAT_FwReleaseMinor; 5055 int bnx_TPAT_FwReleaseFix; 5056 u_int32_t bnx_TPAT_FwStartAddr; 5057 u_int32_t bnx_TPAT_FwTextAddr; 5058 int bnx_TPAT_FwTextLen; 5059 u_int32_t bnx_TPAT_FwDataAddr; 5060 int bnx_TPAT_FwDataLen; 5061 u_int32_t bnx_TPAT_FwRodataAddr; 5062 int bnx_TPAT_FwRodataLen; 5063 u_int32_t bnx_TPAT_FwBssAddr; 5064 int bnx_TPAT_FwBssLen; 5065 u_int32_t bnx_TPAT_FwSbssAddr; 5066 int bnx_TPAT_FwSbssLen; 5067 5068 int bnx_TXP_FwReleaseMajor; 5069 int bnx_TXP_FwReleaseMinor; 5070 int bnx_TXP_FwReleaseFix; 5071 u_int32_t bnx_TXP_FwStartAddr; 5072 u_int32_t bnx_TXP_FwTextAddr; 5073 int bnx_TXP_FwTextLen; 5074 u_int32_t bnx_TXP_FwDataAddr; 5075 int bnx_TXP_FwDataLen; 5076 u_int32_t bnx_TXP_FwRodataAddr; 5077 int bnx_TXP_FwRodataLen; 5078 u_int32_t bnx_TXP_FwBssAddr; 5079 int bnx_TXP_FwBssLen; 5080 u_int32_t bnx_TXP_FwSbssAddr; 5081 int bnx_TXP_FwSbssLen; 5082 5083 /* Followed by blocks of data, each sized according to 5084 * the (rather obvious) block length stated above. 5085 * 5086 * bnx_COM_FwText, bnx_COM_FwData, bnx_COM_FwRodata, 5087 * bnx_COM_FwBss, bnx_COM_FwSbss, 5088 * 5089 * bnx_RXP_FwText, bnx_RXP_FwData, bnx_RXP_FwRodata, 5090 * bnx_RXP_FwBss, bnx_RXP_FwSbss, 5091 * 5092 * bnx_TPAT_FwText, bnx_TPAT_FwData, bnx_TPAT_FwRodata, 5093 * bnx_TPAT_FwBss, bnx_TPAT_FwSbss, 5094 * 5095 * bnx_TXP_FwText, bnx_TXP_FwData, bnx_TXP_FwRodata, 5096 * bnx_TXP_FwBss, bnx_TXP_FwSbss, 5097 */ 5098 }; 5099 5100 struct bnx_rv2p_header { 5101 int bnx_rv2p_proc1len; 5102 int bnx_rv2p_proc2len; 5103 5104 /* 5105 * Followed by blocks of data, each sized according to 5106 * the (rather obvious) block length stated above. 5107 */ 5108 }; 5109 5110 /* 5111 * The RV2P block must be configured for the system 5112 * page size, or more specifically, the number of 5113 * usable rx_bd's per page, and should be called 5114 * as follows prior to loading the RV2P firmware: 5115 * 5116 * BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE) 5117 * 5118 * The default value is 0xFF. 5119 */ 5120 #define BNX_RV2P_PROC2_MAX_BD_PAGE_LOC 5 5121 #define BNX_RV2P_PROC2_CHG_MAX_BD_PAGE(_rv2p, _v) { \ 5122 _rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] = \ 5123 (_rv2p[BNX_RV2P_PROC2_MAX_BD_PAGE_LOC] & ~0xFFFF) | (_v); \ 5124 } 5125 5126 #endif /* #ifndef _BNX_H_DEFINED */ 5127