1// DESCRIPTION: Verilator: Verilog Test module 2// 3// This file ONLY is placed under the Creative Commons Public Domain, for 4// any use, without warranty, 2009 by Wilson Snyder. 5// SPDX-License-Identifier: CC0-1.0 6 7module t; 8 reg foobar; 9 10 task boobar; endtask 11 12 initial begin 13 if (foobat) $stop; 14 boobat; 15 end 16endmodule 17