1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * %sccs.include.redist.c% 15 * 16 * @(#)cache.h 8.1 (Berkeley) 06/11/93 17 * 18 * from: $Header: cache.h,v 1.7 93/04/27 14:31:16 torek Exp $ 19 */ 20 21 /* 22 * Sun-4 and Sun-4c virtual address cache. 23 * 24 * Sun-4 virtual caches come in two flavors, write-through (Sun-4c) 25 * and write-back (Sun-4). The write-back caches are much faster 26 * but require a bit more care. 27 * 28 * VAC_NONE is not actually used now, but if someone builds a physical 29 * cache Sun-4 (or, more likely, a virtual index/physical tag cache) 30 * everything will work (after pulling out the #ifdef notdef's: grep 31 * for VAC_NONE to find them). 32 */ 33 enum vactype { VAC_NONE, VAC_WRITETHROUGH, VAC_WRITEBACK }; 34 35 extern enum vactype vactype; /* XXX move into cacheinfo struct */ 36 37 /* 38 * Cache tags can be written in control space, and must be set to 0 39 * (or invalid anyway) before turning on the cache. The tags are 40 * addressed as an array of 32-bit structures of the form: 41 * 42 * struct cache_tag { 43 * u_int :7, (unused; must be zero) 44 * ct_cid:3, (context ID) 45 * ct_w:1, (write flag from PTE) 46 * ct_s:1, (supervisor flag from PTE) 47 * ct_v:1, (set => cache entry is valid) 48 * :3, (unused; must be zero) 49 * ct_tid:14, (cache tag ID) 50 * :2; (unused; must be zero) 51 * }; 52 * 53 * The SPARCstation 1 cache sees virtual addresses as: 54 * 55 * struct cache_va { 56 * u_int :2, (unused; probably copies of va_tid<13>) 57 * cva_tid:14, (tag ID) 58 * cva_line:12, (cache line number) 59 * cva_byte:4; (byte in cache line) 60 * }; 61 * 62 * (The SS2 cache is similar but has half as many lines, each twice as long.) 63 * 64 * Note that, because the 12-bit line ID is `wider' than the page offset, 65 * it is possible to have one page map to two different cache lines. 66 * This can happen whenever two different physical pages have the same bits 67 * in the part of the virtual address that overlaps the cache line ID, i.e., 68 * bits <15:12>. In order to prevent cache duplication, we have to 69 * make sure that no one page has more than one virtual address where 70 * (va1 & 0xf000) != (va2 & 0xf000). (The cache hardware turns off ct_v 71 * when a cache miss occurs on a write, i.e., if va1 is in the cache and 72 * va2 is not, and you write to va2, va1 goes out of the cache. If va1 73 * is in the cache and va2 is not, reading va2 also causes va1 to become 74 * uncached, and the [same] data is then read from main memory into the 75 * cache.) 76 * 77 * The other alternative, of course, is to disable caching of aliased 78 * pages. (In a few cases this might be faster anyway, but we do it 79 * only when forced.) 80 * 81 * THE CURRENT VM CODE DOES NOT ALLOW US TO SPECIFY PREFERRED VIRTUAL 82 * ADDRESSES ... THIS MUST BE FIXED! 83 */ 84 85 #define CACHE_ALIAS_DISTANCE (256 * 1024) /* 256 kbytes */ 86 87 /* 88 * True iff a1 and a2 are `bad' aliases (will cause cache duplication). 89 */ 90 #define BADALIAS(a1, a2) (((int)(a1) ^ (int)(a2)) & 0xf000) 91 92 /* 93 * Routines for dealing with the cache. 94 */ 95 void cache_enable __P((void)); /* turn it on */ 96 void cache_flush_context __P((void)); /* flush current context */ 97 void cache_flush_segment __P((int vseg)); /* flush seg in cur ctx */ 98 void cache_flush_page __P((int va)); /* flush page in cur ctx */ 99 void cache_flush __P((caddr_t base, u_int len));/* flush region */ 100 101 /* 102 * Cache control information. 103 */ 104 struct cacheinfo { 105 int c_totalsize; /* total size, in bytes */ 106 int c_enabled; /* true => cache is enabled */ 107 int c_hwflush; /* true => have hardware flush */ 108 int c_linesize; /* line size, in bytes */ 109 int c_l2linesize; /* log2(linesize) */ 110 }; 111 extern struct cacheinfo cacheinfo; 112 113 /* 114 * Cache control statistics. 115 */ 116 struct cachestats { 117 int cs_npgflush; /* # page flushes */ 118 int cs_nsgflush; /* # seg flushes */ 119 int cs_ncxflush; /* # context flushes */ 120 int cs_nraflush; /* # range flushes */ 121 #ifdef notyet 122 int cs_ra[65]; /* pages/range */ 123 #endif 124 }; 125