1 /* $NetBSD: cbsc.c,v 1.35 2019/01/08 19:41:09 jdolecek Exp $ */
2
3 /*
4 * Copyright (c) 1997 Michael L. Hitch
5 * Copyright (c) 1982, 1990 The Regents of the University of California.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 */
33
34 #ifdef __m68k__
35 #include "opt_m68k_arch.h"
36 #endif
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: cbsc.c,v 1.35 2019/01/08 19:41:09 jdolecek Exp $");
40
41 #include <sys/types.h>
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/errno.h>
46 #include <sys/ioctl.h>
47 #include <sys/device.h>
48 #include <sys/buf.h>
49 #include <sys/proc.h>
50 #include <sys/queue.h>
51
52 #include <dev/scsipi/scsi_all.h>
53 #include <dev/scsipi/scsipi_all.h>
54 #include <dev/scsipi/scsiconf.h>
55 #include <dev/scsipi/scsi_message.h>
56
57 #include <machine/cpu.h>
58
59 #include <dev/ic/ncr53c9xreg.h>
60 #include <dev/ic/ncr53c9xvar.h>
61
62 #include <amiga/amiga/isr.h>
63 #include <amiga/dev/cbscvar.h>
64 #include <amiga/dev/zbusvar.h>
65
66 #ifdef __powerpc__
67 #define badaddr(a) badaddr_read(a, 2, NULL)
68 #endif
69
70 int cbscmatch(device_t, cfdata_t, void *);
71 void cbscattach(device_t, device_t, void *);
72
73 /* Linkup to the rest of the kernel */
74 CFATTACH_DECL_NEW(cbsc, sizeof(struct cbsc_softc),
75 cbscmatch, cbscattach, NULL, NULL);
76
77 /*
78 * Functions and the switch for the MI code.
79 */
80 uint8_t cbsc_read_reg(struct ncr53c9x_softc *, int);
81 void cbsc_write_reg(struct ncr53c9x_softc *, int, uint8_t);
82 int cbsc_dma_isintr(struct ncr53c9x_softc *);
83 void cbsc_dma_reset(struct ncr53c9x_softc *);
84 int cbsc_dma_intr(struct ncr53c9x_softc *);
85 int cbsc_dma_setup(struct ncr53c9x_softc *, uint8_t **,
86 size_t *, int, size_t *);
87 void cbsc_dma_go(struct ncr53c9x_softc *);
88 void cbsc_dma_stop(struct ncr53c9x_softc *);
89 int cbsc_dma_isactive(struct ncr53c9x_softc *);
90
91 struct ncr53c9x_glue cbsc_glue = {
92 cbsc_read_reg,
93 cbsc_write_reg,
94 cbsc_dma_isintr,
95 cbsc_dma_reset,
96 cbsc_dma_intr,
97 cbsc_dma_setup,
98 cbsc_dma_go,
99 cbsc_dma_stop,
100 cbsc_dma_isactive,
101 NULL,
102 };
103
104 /* Maximum DMA transfer length to reduce impact on high-speed serial input */
105 u_long cbsc_max_dma = 1024;
106 extern int ser_open_speed;
107
108 u_long cbsc_cnt_pio = 0; /* number of PIO transfers */
109 u_long cbsc_cnt_dma = 0; /* number of DMA transfers */
110 u_long cbsc_cnt_dma2 = 0; /* number of DMA transfers broken up */
111 u_long cbsc_cnt_dma3 = 0; /* number of pages combined */
112
113 #ifdef DEBUG
114 struct {
115 uint8_t hardbits;
116 uint8_t status;
117 uint8_t xx;
118 uint8_t yy;
119 } cbsc_trace[128];
120 int cbsc_trace_ptr = 0;
121 int cbsc_trace_enable = 1;
122 void cbsc_dump(void);
123 #endif
124
125 /*
126 * if we are a Phase5 CyberSCSI [mark I?]
127 */
128 int
cbscmatch(device_t parent,cfdata_t cf,void * aux)129 cbscmatch(device_t parent, cfdata_t cf, void *aux)
130 {
131 struct zbus_args *zap;
132 volatile uint8_t *regs;
133
134 zap = aux;
135 if (zap->manid != 0x2140)
136 return 0; /* It's not Phase5 */
137 if (zap->prodid != 12 && zap->prodid != 11)
138 return 0; /* Not CyberStorm MKI SCSI */
139 if (zap->prodid == 11 && iszthreepa(zap->pa))
140 return 0; /* Fastlane Z3! */
141 regs = &((volatile uint8_t *)zap->va)[0xf400];
142 if (badaddr((void *)__UNVOLATILE(regs)))
143 return 0;
144 regs[NCR_CFG1 * 4] = 0;
145 regs[NCR_CFG1 * 4] = NCRCFG1_PARENB | 7;
146 delay(5);
147 if (regs[NCR_CFG1 * 4] != (NCRCFG1_PARENB | 7))
148 return 0;
149 return 1;
150 }
151
152 /*
153 * Attach this instance, and then all the sub-devices
154 */
155 void
cbscattach(device_t parent,device_t self,void * aux)156 cbscattach(device_t parent, device_t self, void *aux)
157 {
158 struct cbsc_softc *csc = device_private(self);
159 struct ncr53c9x_softc *sc = &csc->sc_ncr53c9x;
160 struct zbus_args *zap;
161 extern u_long scsi_nosync;
162 extern int shift_nosync;
163 extern int ncr53c9x_debug;
164
165 /*
166 * Set up the glue for MI code early; we use some of it here.
167 */
168 sc->sc_dev = self;
169 sc->sc_glue = &cbsc_glue;
170
171 /*
172 * Save the regs
173 */
174 zap = aux;
175 csc->sc_reg = &((volatile uint8_t *)zap->va)[0xf400];
176 csc->sc_dmabase = &csc->sc_reg[0x400];
177
178 sc->sc_freq = 40; /* Clocked at 40 MHz */
179
180 aprint_normal(": address %p", csc->sc_reg);
181
182 sc->sc_id = 7;
183
184 /*
185 * It is necessary to try to load the 2nd config register here,
186 * to find out what rev the FAS chip is, else the ncr53c9x_reset
187 * will not set up the defaults correctly.
188 */
189 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
190 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
191 sc->sc_cfg3 = 0x08 /*FCLK*/ | NCRESPCFG3_FSCSI | NCRESPCFG3_CDB;
192 sc->sc_rev = NCR_VARIANT_FAS216;
193
194 /*
195 * This is the value used to start sync negotiations
196 * Note that the NCR register "SYNCTP" is programmed
197 * in "clocks per byte", and has a minimum value of 4.
198 * The SCSI period used in negotiation is one-fourth
199 * of the time (in nanoseconds) needed to transfer one byte.
200 * Since the chip's clock is given in MHz, we have the following
201 * formula: 4 * period = (1000 / freq) * 4
202 */
203 sc->sc_minsync = 1000 / sc->sc_freq;
204
205 /*
206 * get flags from -I argument and set cf_flags.
207 * NOTE: low 8 bits are to disable disconnect, and the next
208 * 8 bits are to disable sync.
209 */
210 device_cfdata(self)->cf_flags |= (scsi_nosync >> shift_nosync)
211 & 0xffff;
212 shift_nosync += 16;
213
214 /* Use next 16 bits of -I argument to set ncr53c9x_debug flags */
215 ncr53c9x_debug |= (scsi_nosync >> shift_nosync) & 0xffff;
216 shift_nosync += 16;
217
218 #if 1
219 if (((scsi_nosync >> shift_nosync) & 0xff00) == 0xff00)
220 sc->sc_minsync = 0;
221 #endif
222
223 /* Really no limit, but since we want to fit into the TCR... */
224 sc->sc_maxxfer = 64 * 1024;
225
226 /*
227 * Configure interrupts.
228 */
229 csc->sc_isr.isr_intr = ncr53c9x_intr;
230 csc->sc_isr.isr_arg = sc;
231 csc->sc_isr.isr_ipl = 2;
232 add_isr(&csc->sc_isr);
233
234 /*
235 * Now try to attach all the sub-devices
236 */
237 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
238 sc->sc_adapter.adapt_minphys = minphys;
239 ncr53c9x_attach(sc);
240 }
241
242 /*
243 * Glue functions.
244 */
245
246 uint8_t
cbsc_read_reg(struct ncr53c9x_softc * sc,int reg)247 cbsc_read_reg(struct ncr53c9x_softc *sc, int reg)
248 {
249 struct cbsc_softc *csc = (struct cbsc_softc *)sc;
250
251 return csc->sc_reg[reg * 4];
252 }
253
254 void
cbsc_write_reg(struct ncr53c9x_softc * sc,int reg,uint8_t val)255 cbsc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val)
256 {
257 struct cbsc_softc *csc = (struct cbsc_softc *)sc;
258 uint8_t v = val;
259
260 csc->sc_reg[reg * 4] = v;
261 #ifdef DEBUG
262 if (cbsc_trace_enable/* && sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL*/ &&
263 reg == NCR_CMD/* && csc->sc_active*/) {
264 cbsc_trace[(cbsc_trace_ptr - 1) & 127].yy = v;
265 /* printf(" cmd %x", v);*/
266 }
267 #endif
268 }
269
270 int
cbsc_dma_isintr(struct ncr53c9x_softc * sc)271 cbsc_dma_isintr(struct ncr53c9x_softc *sc)
272 {
273 struct cbsc_softc *csc = (struct cbsc_softc *)sc;
274
275 if ((csc->sc_reg[NCR_STAT * 4] & NCRSTAT_INT) == 0)
276 return 0;
277
278 if (sc->sc_state == NCR_CONNECTED)
279 csc->sc_portbits |= CBSC_PB_LED;
280 else
281 csc->sc_portbits &= ~CBSC_PB_LED;
282 csc->sc_reg[0x802] = csc->sc_portbits;
283
284 if ((csc->sc_reg[0x802] & CBSC_HB_CREQ) == 0)
285 return 0;
286 #ifdef DEBUG
287 if (/*sc->sc_nexus && sc->sc_nexus->xs->xs_control & XS_CTL_POLL &&*/ cbsc_trace_enable) {
288 cbsc_trace[cbsc_trace_ptr].status = csc->sc_reg[NCR_STAT * 4];
289 cbsc_trace[cbsc_trace_ptr].xx = csc->sc_reg[NCR_CMD * 4];
290 cbsc_trace[cbsc_trace_ptr].yy = csc->sc_active;
291 cbsc_trace_ptr = (cbsc_trace_ptr + 1) & 127;
292 }
293 #endif
294 return 1;
295 }
296
297 void
cbsc_dma_reset(struct ncr53c9x_softc * sc)298 cbsc_dma_reset(struct ncr53c9x_softc *sc)
299 {
300 struct cbsc_softc *csc = (struct cbsc_softc *)sc;
301
302 csc->sc_active = 0;
303 }
304
305 int
cbsc_dma_intr(struct ncr53c9x_softc * sc)306 cbsc_dma_intr(struct ncr53c9x_softc *sc)
307 {
308 register struct cbsc_softc *csc = (struct cbsc_softc *)sc;
309 register int cnt;
310
311 NCR_DMA(("cbsc_dma_intr: cnt %d int %x stat %x fifo %d ",
312 csc->sc_dmasize, sc->sc_espintr, sc->sc_espstat,
313 csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF));
314 if (csc->sc_active == 0) {
315 printf("cbsc_intr--inactive DMA\n");
316 return -1;
317 }
318
319 /* update sc_dmaaddr and sc_pdmalen */
320 cnt = csc->sc_reg[NCR_TCL * 4];
321 cnt += csc->sc_reg[NCR_TCM * 4] << 8;
322 cnt += csc->sc_reg[NCR_TCH * 4] << 16;
323 if (!csc->sc_datain) {
324 cnt += csc->sc_reg[NCR_FFLAG * 4] & NCRFIFO_FF;
325 csc->sc_reg[NCR_CMD * 4] = NCRCMD_FLUSH;
326 }
327 cnt = csc->sc_dmasize - cnt; /* number of bytes transferred */
328 NCR_DMA(("DMA xferred %d\n", cnt));
329 if (csc->sc_xfr_align) {
330 memcpy(*csc->sc_dmaaddr, csc->sc_alignbuf, cnt);
331 csc->sc_xfr_align = 0;
332 }
333 *csc->sc_dmaaddr += cnt;
334 *csc->sc_pdmalen -= cnt;
335 csc->sc_active = 0;
336 return 0;
337 }
338
339 int
cbsc_dma_setup(struct ncr53c9x_softc * sc,uint8_t ** addr,size_t * len,int datain,size_t * dmasize)340 cbsc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len,
341 int datain, size_t *dmasize)
342 {
343 struct cbsc_softc *csc = (struct cbsc_softc *)sc;
344 paddr_t pa;
345 uint8_t *ptr;
346 size_t xfer;
347
348 csc->sc_dmaaddr = addr;
349 csc->sc_pdmalen = len;
350 csc->sc_datain = datain;
351 csc->sc_dmasize = *dmasize;
352 /*
353 * DMA can be nasty for high-speed serial input, so limit the
354 * size of this DMA operation if the serial port is running at
355 * a high speed (higher than 19200 for now - should be adjusted
356 * based on CPU type and speed?).
357 * XXX - add serial speed check XXX
358 */
359 if (ser_open_speed > 19200 && cbsc_max_dma != 0 &&
360 csc->sc_dmasize > cbsc_max_dma)
361 csc->sc_dmasize = cbsc_max_dma;
362 ptr = *addr; /* Kernel virtual address */
363 pa = kvtop(ptr); /* Physical address of DMA */
364 xfer = uimin(csc->sc_dmasize, PAGE_SIZE - (pa & (PAGE_SIZE - 1)));
365 csc->sc_xfr_align = 0;
366 /*
367 * If output and unaligned, stuff odd byte into FIFO
368 */
369 if (datain == 0 && (int)ptr & 1) {
370 NCR_DMA(("cbsc_dma_setup: align byte written to fifo\n"));
371 pa++;
372 xfer--; /* XXXX CHECK THIS !!!! XXXX */
373 csc->sc_reg[NCR_FIFO * 4] = *ptr++;
374 }
375 /*
376 * If unaligned address, read unaligned bytes into alignment buffer
377 */
378 else if ((int)ptr & 1) {
379 pa = kvtop((void *)&csc->sc_alignbuf);
380 xfer = csc->sc_dmasize = uimin(xfer, sizeof(csc->sc_alignbuf));
381 NCR_DMA(("cbsc_dma_setup: align read by %d bytes\n", xfer));
382 csc->sc_xfr_align = 1;
383 }
384 ++cbsc_cnt_dma; /* number of DMA operations */
385
386 while (xfer < csc->sc_dmasize) {
387 if ((pa + xfer) != kvtop(*addr + xfer))
388 break;
389 if ((csc->sc_dmasize - xfer) < PAGE_SIZE)
390 xfer = csc->sc_dmasize;
391 else
392 xfer += PAGE_SIZE;
393 ++cbsc_cnt_dma3;
394 }
395 if (xfer != *len)
396 ++cbsc_cnt_dma2;
397
398 csc->sc_dmasize = xfer;
399 *dmasize = csc->sc_dmasize;
400 csc->sc_pa = pa;
401 #if defined(M68040) || defined(M68060)
402 if (mmutype == MMU_68040) {
403 if (csc->sc_xfr_align) {
404 dma_cachectl(csc->sc_alignbuf,
405 sizeof(csc->sc_alignbuf));
406 }
407 else
408 dma_cachectl(*csc->sc_dmaaddr, csc->sc_dmasize);
409 }
410 #endif
411
412 if (csc->sc_datain)
413 pa &= ~1;
414 else
415 pa |= 1;
416 csc->sc_dmabase[0] = (uint8_t)(pa >> 24);
417 csc->sc_dmabase[2] = (uint8_t)(pa >> 16);
418 csc->sc_dmabase[4] = (uint8_t)(pa >> 8);
419 csc->sc_dmabase[6] = (uint8_t)(pa);
420 if (csc->sc_datain)
421 csc->sc_portbits &= ~CBSC_PB_WRITE;
422 else
423 csc->sc_portbits |= CBSC_PB_WRITE;
424 csc->sc_reg[0x802] = csc->sc_portbits;
425 csc->sc_active = 1;
426 return 0;
427 }
428
429 void
cbsc_dma_go(struct ncr53c9x_softc * sc)430 cbsc_dma_go(struct ncr53c9x_softc *sc)
431 {
432 }
433
434 void
cbsc_dma_stop(struct ncr53c9x_softc * sc)435 cbsc_dma_stop(struct ncr53c9x_softc *sc)
436 {
437 }
438
439 int
cbsc_dma_isactive(struct ncr53c9x_softc * sc)440 cbsc_dma_isactive(struct ncr53c9x_softc *sc)
441 {
442 struct cbsc_softc *csc = (struct cbsc_softc *)sc;
443
444 return csc->sc_active;
445 }
446
447 #ifdef DEBUG
448 void
cbsc_dump(void)449 cbsc_dump(void)
450 {
451 int i;
452
453 i = cbsc_trace_ptr;
454 printf("cbsc_trace dump: ptr %x\n", cbsc_trace_ptr);
455 do {
456 if (cbsc_trace[i].hardbits == 0) {
457 i = (i + 1) & 127;
458 continue;
459 }
460 printf("%02x%02x%02x%02x(", cbsc_trace[i].hardbits,
461 cbsc_trace[i].status, cbsc_trace[i].xx, cbsc_trace[i].yy);
462 if (cbsc_trace[i].status & NCRSTAT_INT)
463 printf("NCRINT/");
464 if (cbsc_trace[i].status & NCRSTAT_TC)
465 printf("NCRTC/");
466 switch(cbsc_trace[i].status & NCRSTAT_PHASE) {
467 case 0:
468 printf("dataout"); break;
469 case 1:
470 printf("datain"); break;
471 case 2:
472 printf("cmdout"); break;
473 case 3:
474 printf("status"); break;
475 case 6:
476 printf("msgout"); break;
477 case 7:
478 printf("msgin"); break;
479 default:
480 printf("phase%d?", cbsc_trace[i].status & NCRSTAT_PHASE);
481 }
482 printf(") ");
483 i = (i + 1) & 127;
484 } while (i != cbsc_trace_ptr);
485 printf("\n");
486 }
487 #endif
488