1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 *
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_bios.c 255572 2013-09-14 17:22:34Z dumbbell $
29 */
30
31 #include <drm/drmP.h>
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "atom.h"
35
36 #include <linux/slab.h>
37 /*
38 * BIOS.
39 */
40
41 /* If you boot an IGP board with a discrete card as the primary,
42 * the IGP rom is not accessible via the rom bar as the IGP rom is
43 * part of the system bios. On boot, the system bios puts a
44 * copy of the igp rom at the start of vram if a discrete card is
45 * present.
46 */
igp_read_bios_from_vram(struct radeon_device * rdev)47 static bool igp_read_bios_from_vram(struct radeon_device *rdev)
48 {
49 uint8_t __iomem *bios;
50 resource_size_t vram_base;
51 resource_size_t size = 256 * 1024; /* ??? */
52
53 if (!(rdev->flags & RADEON_IS_IGP))
54 if (!radeon_card_posted(rdev))
55 return false;
56
57 rdev->bios = NULL;
58 vram_base = pci_resource_start(rdev->pdev, 0);
59 bios = ioremap(vram_base, size);
60 if (!bios) {
61 return false;
62 }
63
64 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
65 iounmap(bios);
66 return false;
67 }
68 rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
69 if (rdev->bios == NULL) {
70 iounmap(bios);
71 return false;
72 }
73 memcpy_fromio(rdev->bios, bios, size);
74 iounmap(bios);
75 return true;
76 }
77
radeon_read_bios(struct radeon_device * rdev)78 static bool radeon_read_bios(struct radeon_device *rdev)
79 {
80 uint8_t __iomem *bios, val1, val2;
81 size_t size;
82 device_t vga_dev = device_get_parent(rdev->dev->bsddev);
83
84 rdev->bios = NULL;
85 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
86 bios = vga_pci_map_bios(vga_dev, &size);
87 if (!bios) {
88 return false;
89 }
90
91 val1 = readb(&bios[0]);
92 val2 = readb(&bios[1]);
93
94 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
95 vga_pci_unmap_bios(vga_dev, bios);
96 return false;
97 }
98 rdev->bios = kzalloc(size, GFP_KERNEL);
99 if (rdev->bios == NULL) {
100 vga_pci_unmap_bios(vga_dev, bios);
101 return false;
102 }
103 memcpy_fromio(rdev->bios, bios, size);
104 vga_pci_unmap_bios(vga_dev, bios);
105 return true;
106 }
107
radeon_read_platform_bios(struct radeon_device * rdev)108 static bool radeon_read_platform_bios(struct radeon_device *rdev)
109 {
110 uint8_t __iomem *bios;
111 size_t size;
112
113 rdev->bios = NULL;
114
115 #if 0
116 // XXX: FIXME
117 bios = pci_platform_rom(rdev->pdev, &size);
118 #else
119 size = 0;
120 bios = NULL;
121 #endif
122 if (!bios) {
123 return false;
124 }
125
126 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
127 return false;
128 }
129 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
130 if (rdev->bios == NULL) {
131 return false;
132 }
133
134 return true;
135 }
136
137 #ifdef CONFIG_ACPI
138 /* ATRM is used to get the BIOS on the discrete cards in
139 * dual-gpu systems.
140 */
141 /* retrieve the ROM in 4k blocks */
142 #define ATRM_BIOS_PAGE 4096
143 /**
144 * radeon_atrm_call - fetch a chunk of the vbios
145 *
146 * @atrm_handle: acpi ATRM handle
147 * @bios: vbios image pointer
148 * @offset: offset of vbios image data to fetch
149 * @len: length of vbios image data to fetch
150 *
151 * Executes ATRM to fetch a chunk of the discrete
152 * vbios image on PX systems (all asics).
153 * Returns the length of the buffer fetched.
154 */
radeon_atrm_call(ACPI_HANDLE atrm_handle,uint8_t * bios,int offset,int len)155 static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios,
156 int offset, int len)
157 {
158 ACPI_STATUS status;
159 ACPI_OBJECT atrm_arg_elements[2], *obj;
160 ACPI_OBJECT_LIST atrm_arg;
161 ACPI_BUFFER buffer = { ACPI_ALLOCATE_BUFFER, NULL};
162
163 atrm_arg.Count = 2;
164 atrm_arg.Pointer = &atrm_arg_elements[0];
165
166 atrm_arg_elements[0].Type = ACPI_TYPE_INTEGER;
167 atrm_arg_elements[0].Integer.Value = offset;
168
169 atrm_arg_elements[1].Type = ACPI_TYPE_INTEGER;
170 atrm_arg_elements[1].Integer.Value = len;
171
172 status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer);
173 if (ACPI_FAILURE(status)) {
174 printk("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
175 return -ENODEV;
176 }
177
178 obj = (ACPI_OBJECT *)buffer.Pointer;
179 memcpy(bios+offset, obj->Buffer.Pointer, obj->Buffer.Length);
180 len = obj->Buffer.Length;
181 AcpiOsFree(buffer.Pointer);
182 return len;
183 }
184
radeon_atrm_get_bios(struct radeon_device * rdev)185 static bool radeon_atrm_get_bios(struct radeon_device *rdev)
186 {
187 int ret;
188 int size = 256 * 1024;
189 int i;
190 device_t dev;
191 ACPI_HANDLE dhandle, atrm_handle;
192 ACPI_STATUS status;
193 bool found = false;
194
195 DRM_INFO("%s: ===> Try ATRM...\n", __func__);
196
197 /* ATRM is for the discrete card only */
198 if (rdev->flags & RADEON_IS_IGP) {
199 DRM_INFO("%s: IGP card detected, skipping this method...\n",
200 __func__);
201 return false;
202 }
203
204 #ifdef DUMBBELL_WIP
205 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
206 #endif /* DUMBBELL_WIP */
207 if ((dev = pci_find_class(PCIC_DISPLAY, PCIS_DISPLAY_VGA)) != NULL) {
208 DRM_INFO("%s: pci_find_class() found: %d:%d:%d:%d, vendor=%04x, device=%04x\n",
209 __func__,
210 pci_get_domain(dev),
211 pci_get_bus(dev),
212 pci_get_slot(dev),
213 pci_get_function(dev),
214 pci_get_vendor(dev),
215 pci_get_device(dev));
216 DRM_INFO("%s: Get ACPI device handle\n", __func__);
217 dhandle = acpi_get_handle(dev);
218 #ifdef DUMBBELL_WIP
219 if (!dhandle)
220 continue;
221 #endif /* DUMBBELL_WIP */
222 if (!dhandle)
223 return false;
224
225 DRM_INFO("%s: Get ACPI handle for \"ATRM\"\n", __func__);
226 status = AcpiGetHandle(dhandle, "ATRM", &atrm_handle);
227 if (!ACPI_FAILURE(status)) {
228 found = true;
229 #ifdef DUMBBELL_WIP
230 break;
231 #endif /* DUMBBELL_WIP */
232 } else {
233 DRM_INFO("%s: Failed to get \"ATRM\" handle: %s\n",
234 __func__, AcpiFormatException(status));
235 }
236 }
237
238 if (!found)
239 return false;
240
241 rdev->bios = kmalloc(size, M_DRM, M_WAITOK);
242 if (!rdev->bios) {
243 DRM_ERROR("Unable to allocate bios\n");
244 return false;
245 }
246
247 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
248 DRM_INFO("%s: Call radeon_atrm_call()\n", __func__);
249 ret = radeon_atrm_call(atrm_handle,
250 rdev->bios,
251 (i * ATRM_BIOS_PAGE),
252 ATRM_BIOS_PAGE);
253 if (ret < ATRM_BIOS_PAGE)
254 break;
255 }
256
257 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
258 if (i == 0) {
259 DRM_INFO("%s: Incorrect BIOS size\n", __func__);
260 } else {
261 DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
262 __func__, rdev->bios[0], rdev->bios[1]);
263 }
264 kfree(rdev->bios);
265 return false;
266 }
267 return true;
268 }
269 #else
270 static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
271 {
272 return false;
273 }
274 #endif
275
276 static bool ni_read_disabled_bios(struct radeon_device *rdev)
277 {
278 u32 bus_cntl;
279 u32 d1vga_control;
280 u32 d2vga_control;
281 u32 vga_render_control;
282 u32 rom_cntl;
283 bool r;
284
285 DRM_INFO("%s: ===> Try disabled BIOS (ni)...\n", __func__);
286
287 bus_cntl = RREG32(R600_BUS_CNTL);
288 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
289 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
290 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
291 rom_cntl = RREG32(R600_ROM_CNTL);
292
293 /* enable the rom */
294 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
295 if (!ASIC_IS_NODCE(rdev)) {
296 /* Disable VGA mode */
297 WREG32(AVIVO_D1VGA_CONTROL,
298 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
299 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
300 WREG32(AVIVO_D2VGA_CONTROL,
301 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
302 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
303 WREG32(AVIVO_VGA_RENDER_CONTROL,
304 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
305 }
306 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
307
308 r = radeon_read_bios(rdev);
309
310 /* restore regs */
311 WREG32(R600_BUS_CNTL, bus_cntl);
312 if (!ASIC_IS_NODCE(rdev)) {
313 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
314 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
315 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
316 }
317 WREG32(R600_ROM_CNTL, rom_cntl);
318 return r;
319 }
320
321 static bool r700_read_disabled_bios(struct radeon_device *rdev)
322 {
323 uint32_t viph_control;
324 uint32_t bus_cntl;
325 uint32_t d1vga_control;
326 uint32_t d2vga_control;
327 uint32_t vga_render_control;
328 uint32_t rom_cntl;
329 uint32_t cg_spll_func_cntl = 0;
330 uint32_t cg_spll_status;
331 bool r;
332
333 DRM_INFO("%s: ===> Try disabled BIOS (r700)...\n", __func__);
334
335 viph_control = RREG32(RADEON_VIPH_CONTROL);
336 bus_cntl = RREG32(R600_BUS_CNTL);
337 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
338 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
339 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
340 rom_cntl = RREG32(R600_ROM_CNTL);
341
342 /* disable VIP */
343 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
344 /* enable the rom */
345 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
346 /* Disable VGA mode */
347 WREG32(AVIVO_D1VGA_CONTROL,
348 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
349 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
350 WREG32(AVIVO_D2VGA_CONTROL,
351 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
352 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
353 WREG32(AVIVO_VGA_RENDER_CONTROL,
354 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
355
356 if (rdev->family == CHIP_RV730) {
357 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
358
359 /* enable bypass mode */
360 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
361 R600_SPLL_BYPASS_EN));
362
363 /* wait for SPLL_CHG_STATUS to change to 1 */
364 cg_spll_status = 0;
365 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
366 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
367
368 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
369 } else
370 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
371
372 r = radeon_read_bios(rdev);
373
374 /* restore regs */
375 if (rdev->family == CHIP_RV730) {
376 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
377
378 /* wait for SPLL_CHG_STATUS to change to 1 */
379 cg_spll_status = 0;
380 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
381 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
382 }
383 WREG32(RADEON_VIPH_CONTROL, viph_control);
384 WREG32(R600_BUS_CNTL, bus_cntl);
385 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
386 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
387 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
388 WREG32(R600_ROM_CNTL, rom_cntl);
389 return r;
390 }
391
392 static bool r600_read_disabled_bios(struct radeon_device *rdev)
393 {
394 uint32_t viph_control;
395 uint32_t bus_cntl;
396 uint32_t d1vga_control;
397 uint32_t d2vga_control;
398 uint32_t vga_render_control;
399 uint32_t rom_cntl;
400 uint32_t general_pwrmgt;
401 uint32_t low_vid_lower_gpio_cntl;
402 uint32_t medium_vid_lower_gpio_cntl;
403 uint32_t high_vid_lower_gpio_cntl;
404 uint32_t ctxsw_vid_lower_gpio_cntl;
405 uint32_t lower_gpio_enable;
406 bool r;
407
408 DRM_INFO("%s: ===> Try disabled BIOS (r600)...\n", __func__);
409
410 viph_control = RREG32(RADEON_VIPH_CONTROL);
411 bus_cntl = RREG32(R600_BUS_CNTL);
412 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
413 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
414 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
415 rom_cntl = RREG32(R600_ROM_CNTL);
416 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
417 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
418 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
419 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
420 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
421 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
422
423 /* disable VIP */
424 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
425 /* enable the rom */
426 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
427 /* Disable VGA mode */
428 WREG32(AVIVO_D1VGA_CONTROL,
429 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
430 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
431 WREG32(AVIVO_D2VGA_CONTROL,
432 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
433 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
434 WREG32(AVIVO_VGA_RENDER_CONTROL,
435 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
436
437 WREG32(R600_ROM_CNTL,
438 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
439 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
440 R600_SCK_OVERWRITE));
441
442 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
443 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
444 (low_vid_lower_gpio_cntl & ~0x400));
445 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
446 (medium_vid_lower_gpio_cntl & ~0x400));
447 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
448 (high_vid_lower_gpio_cntl & ~0x400));
449 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
450 (ctxsw_vid_lower_gpio_cntl & ~0x400));
451 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
452
453 r = radeon_read_bios(rdev);
454
455 /* restore regs */
456 WREG32(RADEON_VIPH_CONTROL, viph_control);
457 WREG32(R600_BUS_CNTL, bus_cntl);
458 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
459 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
460 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
461 WREG32(R600_ROM_CNTL, rom_cntl);
462 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
463 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
464 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
465 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
466 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
467 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
468 return r;
469 }
470
471 static bool avivo_read_disabled_bios(struct radeon_device *rdev)
472 {
473 uint32_t seprom_cntl1;
474 uint32_t viph_control;
475 uint32_t bus_cntl;
476 uint32_t d1vga_control;
477 uint32_t d2vga_control;
478 uint32_t vga_render_control;
479 uint32_t gpiopad_a;
480 uint32_t gpiopad_en;
481 uint32_t gpiopad_mask;
482 bool r;
483
484 DRM_INFO("%s: ===> Try disabled BIOS (avivo)...\n", __func__);
485
486 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
487 viph_control = RREG32(RADEON_VIPH_CONTROL);
488 bus_cntl = RREG32(RV370_BUS_CNTL);
489 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
490 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
491 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
492 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
493 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
494 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
495
496 WREG32(RADEON_SEPROM_CNTL1,
497 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
498 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
499 WREG32(RADEON_GPIOPAD_A, 0);
500 WREG32(RADEON_GPIOPAD_EN, 0);
501 WREG32(RADEON_GPIOPAD_MASK, 0);
502
503 /* disable VIP */
504 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
505
506 /* enable the rom */
507 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
508
509 /* Disable VGA mode */
510 WREG32(AVIVO_D1VGA_CONTROL,
511 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
512 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
513 WREG32(AVIVO_D2VGA_CONTROL,
514 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
515 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
516 WREG32(AVIVO_VGA_RENDER_CONTROL,
517 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
518
519 r = radeon_read_bios(rdev);
520
521 /* restore regs */
522 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
523 WREG32(RADEON_VIPH_CONTROL, viph_control);
524 WREG32(RV370_BUS_CNTL, bus_cntl);
525 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
526 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
527 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
528 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
529 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
530 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
531 return r;
532 }
533
534 static bool legacy_read_disabled_bios(struct radeon_device *rdev)
535 {
536 uint32_t seprom_cntl1;
537 uint32_t viph_control;
538 uint32_t bus_cntl;
539 uint32_t crtc_gen_cntl;
540 uint32_t crtc2_gen_cntl;
541 uint32_t crtc_ext_cntl;
542 uint32_t fp2_gen_cntl;
543 bool r;
544
545 DRM_INFO("%s: ===> Try disabled BIOS (legacy)...\n", __func__);
546
547 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
548 viph_control = RREG32(RADEON_VIPH_CONTROL);
549 if (rdev->flags & RADEON_IS_PCIE)
550 bus_cntl = RREG32(RV370_BUS_CNTL);
551 else
552 bus_cntl = RREG32(RADEON_BUS_CNTL);
553 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
554 crtc2_gen_cntl = 0;
555 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
556 fp2_gen_cntl = 0;
557
558 #define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159
559
560 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
561 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
562 }
563
564 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
565 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
566 }
567
568 WREG32(RADEON_SEPROM_CNTL1,
569 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
570 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
571
572 /* disable VIP */
573 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
574
575 /* enable the rom */
576 if (rdev->flags & RADEON_IS_PCIE)
577 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
578 else
579 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
580
581 /* Turn off mem requests and CRTC for both controllers */
582 WREG32(RADEON_CRTC_GEN_CNTL,
583 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
584 (RADEON_CRTC_DISP_REQ_EN_B |
585 RADEON_CRTC_EXT_DISP_EN)));
586 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
587 WREG32(RADEON_CRTC2_GEN_CNTL,
588 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
589 RADEON_CRTC2_DISP_REQ_EN_B));
590 }
591 /* Turn off CRTC */
592 WREG32(RADEON_CRTC_EXT_CNTL,
593 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
594 (RADEON_CRTC_SYNC_TRISTAT |
595 RADEON_CRTC_DISPLAY_DIS)));
596
597 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
598 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
599 }
600
601 r = radeon_read_bios(rdev);
602
603 /* restore regs */
604 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
605 WREG32(RADEON_VIPH_CONTROL, viph_control);
606 if (rdev->flags & RADEON_IS_PCIE)
607 WREG32(RV370_BUS_CNTL, bus_cntl);
608 else
609 WREG32(RADEON_BUS_CNTL, bus_cntl);
610 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
611 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
612 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
613 }
614 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
615 if (rdev->ddev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
616 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
617 }
618 return r;
619 }
620
621 static bool radeon_read_disabled_bios(struct radeon_device *rdev)
622 {
623 if (rdev->flags & RADEON_IS_IGP)
624 return igp_read_bios_from_vram(rdev);
625 else if (rdev->family >= CHIP_BARTS)
626 return ni_read_disabled_bios(rdev);
627 else if (rdev->family >= CHIP_RV770)
628 return r700_read_disabled_bios(rdev);
629 else if (rdev->family >= CHIP_R600)
630 return r600_read_disabled_bios(rdev);
631 else if (rdev->family >= CHIP_RS600)
632 return avivo_read_disabled_bios(rdev);
633 else
634 return legacy_read_disabled_bios(rdev);
635 }
636
637 #ifdef CONFIG_ACPI
638 static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
639 {
640 bool ret = false;
641 ACPI_TABLE_HEADER *hdr;
642 ACPI_SIZE tbl_size;
643 UEFI_ACPI_VFCT *vfct;
644 GOP_VBIOS_CONTENT *vbios;
645 VFCT_IMAGE_HEADER *vhdr;
646 ACPI_STATUS status;
647
648 DRM_INFO("%s: ===> Try VFCT...\n", __func__);
649
650 DRM_INFO("%s: Get \"VFCT\" ACPI table\n", __func__);
651 status = AcpiGetTable("VFCT", 1, &hdr);
652 if (!ACPI_SUCCESS(status)) {
653 DRM_INFO("%s: Failed to get \"VFCT\" table: %s\n",
654 __func__, AcpiFormatException(status));
655 return false;
656 }
657 tbl_size = hdr->Length;
658 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
659 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
660 goto out_unmap;
661 }
662
663 vfct = (UEFI_ACPI_VFCT *)hdr;
664 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
665 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
666 goto out_unmap;
667 }
668
669 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
670 vhdr = &vbios->VbiosHeader;
671 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
672 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
673 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
674
675 if (vhdr->PCIBus != rdev->pdev->bus->number ||
676 vhdr->PCIDevice != rdev->ddev->pci_slot ||
677 vhdr->PCIFunction != rdev->ddev->pci_func ||
678 vhdr->VendorID != rdev->pdev->vendor ||
679 vhdr->DeviceID != rdev->pdev->device) {
680 DRM_INFO("ACPI VFCT table is not for this card\n");
681 goto out_unmap;
682 }
683
684 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
685 DRM_ERROR("ACPI VFCT image truncated\n");
686 goto out_unmap;
687 }
688
689 rdev->bios = kmalloc(vhdr->ImageLength, M_DRM, M_WAITOK);
690 memcpy(rdev->bios, &vbios->VbiosContent, vhdr->ImageLength);
691 ret = !!rdev->bios;
692
693 out_unmap:
694 return ret;
695 }
696 #else
697 static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
698 {
699 return false;
700 }
701 #endif
702
703 bool radeon_get_bios(struct radeon_device *rdev)
704 {
705 bool r;
706 uint16_t tmp;
707
708 r = radeon_atrm_get_bios(rdev);
709 if (r == false)
710 r = radeon_acpi_vfct_bios(rdev);
711 if (r == false)
712 r = igp_read_bios_from_vram(rdev);
713 if (r == false)
714 r = radeon_read_bios(rdev);
715 if (r == false)
716 r = radeon_read_disabled_bios(rdev);
717 if (r == false)
718 r = radeon_read_platform_bios(rdev);
719 if (r == false || rdev->bios == NULL) {
720 DRM_ERROR("Unable to locate a BIOS ROM\n");
721 rdev->bios = NULL;
722 return false;
723 }
724 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
725 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
726 goto free_bios;
727 }
728
729 tmp = RBIOS16(0x18);
730 if (RBIOS8(tmp + 0x14) != 0x0) {
731 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
732 goto free_bios;
733 }
734
735 rdev->bios_header_start = RBIOS16(0x48);
736 if (!rdev->bios_header_start) {
737 goto free_bios;
738 }
739 tmp = rdev->bios_header_start + 4;
740 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
741 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
742 rdev->is_atom_bios = true;
743 } else {
744 rdev->is_atom_bios = false;
745 }
746
747 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
748 return true;
749 free_bios:
750 kfree(rdev->bios);
751 rdev->bios = NULL;
752 return false;
753 }
754