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/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-pcduino3/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-pine64/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-pinebook/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-orangepi-pc2/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-orangepi-plus-2e/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]
/dports/sysutils/u-boot-orangepi-one/u-boot-2021.07/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h44 #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) argument
46 #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) argument
47 #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) argument
49 #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) argument
51 #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) argument
53 #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) argument
55 #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) argument
57 #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) argument
59 #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) argument
73 #define SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) (5 + (ch) * 2) argument
[all …]

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