1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RADEON_H__
29 #define __RADEON_H__
30
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
63 #include <asm/byteorder.h>
64 #include <linux/atomic.h>
65 #include <linux/wait.h>
66 #include <linux/list.h>
67 #include <linux/kref.h>
68 #include <linux/device.h>
69 #include <linux/log2.h>
70 #include <linux/notifier.h>
71 #include <linux/printk.h>
72 #include <linux/rwsem.h>
73
74 #include <ttm/ttm_bo_api.h>
75 #include <ttm/ttm_bo_driver.h>
76 #include <ttm/ttm_placement.h>
77 #include <ttm/ttm_module.h>
78 #include <ttm/ttm_execbuf_util.h>
79
80 #include "radeon_family.h"
81 #include "radeon_mode.h"
82 #include "radeon_reg.h"
83
84 /*
85 * Modules parameters.
86 */
87 extern int radeon_no_wb;
88 extern int radeon_modeset;
89 extern int radeon_dynclks;
90 extern int radeon_r4xx_atom;
91 extern int radeon_agpmode;
92 extern int radeon_vram_limit;
93 extern int radeon_gart_size;
94 extern int radeon_benchmarking;
95 extern int radeon_testing;
96 extern int radeon_connector_table;
97 extern int radeon_tv;
98 extern int radeon_audio;
99 extern int radeon_disp_priority;
100 extern int radeon_hw_i2c;
101 extern int radeon_pcie_gen2;
102 extern int radeon_msi;
103 extern int radeon_lockup_timeout;
104 extern int radeon_fastfb;
105 extern int radeon_dpm;
106 extern int radeon_aspm;
107 extern int radeon_runtime_pm;
108 extern int radeon_hard_reset;
109
110 /*
111 * Copy from radeon_drv.h so we don't have to include both and have conflicting
112 * symbol;
113 */
114 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
115 #define RADEON_FENCE_JIFFIES_TIMEOUT (DRM_HZ / 2)
116 /* RADEON_IB_POOL_SIZE must be a power of 2 */
117 #define RADEON_IB_POOL_SIZE 16
118 #define RADEON_DEBUGFS_MAX_COMPONENTS 32
119 #define RADEONFB_CONN_LIMIT 4
120 #define RADEON_BIOS_NUM_SCRATCH 8
121
122 /* fence seq are set to this number when signaled */
123 #define RADEON_FENCE_SIGNALED_SEQ 0LL
124
125 /* internal ring indices */
126 /* r1xx+ has gfx CP ring */
127 #define RADEON_RING_TYPE_GFX_INDEX 0
128
129 /* cayman has 2 compute CP rings */
130 #define CAYMAN_RING_TYPE_CP1_INDEX 1
131 #define CAYMAN_RING_TYPE_CP2_INDEX 2
132
133 /* R600+ has an async dma ring */
134 #define R600_RING_TYPE_DMA_INDEX 3
135 /* cayman add a second async dma ring */
136 #define CAYMAN_RING_TYPE_DMA1_INDEX 4
137
138 /* R600+ */
139 #define R600_RING_TYPE_UVD_INDEX 5
140
141 /* TN+ */
142 #define TN_RING_TYPE_VCE1_INDEX 6
143 #define TN_RING_TYPE_VCE2_INDEX 7
144
145 /* max number of rings */
146 #define RADEON_NUM_RINGS 8
147
148 /* number of hw syncs before falling back on blocking */
149 #define RADEON_NUM_SYNCS 4
150
151 /* number of hw syncs before falling back on blocking */
152 #define RADEON_NUM_SYNCS 4
153
154 /* hardcode those limit for now */
155 #define RADEON_VA_IB_OFFSET (1 << 20)
156 #define RADEON_VA_RESERVED_SIZE (8 << 20)
157 #define RADEON_IB_VM_MAX_SIZE (64 << 10)
158
159 /* hard reset data */
160 #define RADEON_ASIC_RESET_DATA 0x39d5e86b
161
162 /* reset flags */
163 #define RADEON_RESET_GFX (1 << 0)
164 #define RADEON_RESET_COMPUTE (1 << 1)
165 #define RADEON_RESET_DMA (1 << 2)
166 #define RADEON_RESET_CP (1 << 3)
167 #define RADEON_RESET_GRBM (1 << 4)
168 #define RADEON_RESET_DMA1 (1 << 5)
169 #define RADEON_RESET_RLC (1 << 6)
170 #define RADEON_RESET_SEM (1 << 7)
171 #define RADEON_RESET_IH (1 << 8)
172 #define RADEON_RESET_VMC (1 << 9)
173 #define RADEON_RESET_MC (1 << 10)
174 #define RADEON_RESET_DISPLAY (1 << 11)
175
176 /* CG block flags */
177 #define RADEON_CG_BLOCK_GFX (1 << 0)
178 #define RADEON_CG_BLOCK_MC (1 << 1)
179 #define RADEON_CG_BLOCK_SDMA (1 << 2)
180 #define RADEON_CG_BLOCK_UVD (1 << 3)
181 #define RADEON_CG_BLOCK_VCE (1 << 4)
182 #define RADEON_CG_BLOCK_HDP (1 << 5)
183 #define RADEON_CG_BLOCK_BIF (1 << 6)
184
185 /* CG flags */
186 #define RADEON_CG_SUPPORT_GFX_MGCG (1 << 0)
187 #define RADEON_CG_SUPPORT_GFX_MGLS (1 << 1)
188 #define RADEON_CG_SUPPORT_GFX_CGCG (1 << 2)
189 #define RADEON_CG_SUPPORT_GFX_CGLS (1 << 3)
190 #define RADEON_CG_SUPPORT_GFX_CGTS (1 << 4)
191 #define RADEON_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
192 #define RADEON_CG_SUPPORT_GFX_CP_LS (1 << 6)
193 #define RADEON_CG_SUPPORT_GFX_RLC_LS (1 << 7)
194 #define RADEON_CG_SUPPORT_MC_LS (1 << 8)
195 #define RADEON_CG_SUPPORT_MC_MGCG (1 << 9)
196 #define RADEON_CG_SUPPORT_SDMA_LS (1 << 10)
197 #define RADEON_CG_SUPPORT_SDMA_MGCG (1 << 11)
198 #define RADEON_CG_SUPPORT_BIF_LS (1 << 12)
199 #define RADEON_CG_SUPPORT_UVD_MGCG (1 << 13)
200 #define RADEON_CG_SUPPORT_VCE_MGCG (1 << 14)
201 #define RADEON_CG_SUPPORT_HDP_LS (1 << 15)
202 #define RADEON_CG_SUPPORT_HDP_MGCG (1 << 16)
203
204 /* PG flags */
205 #define RADEON_PG_SUPPORT_GFX_PG (1 << 0)
206 #define RADEON_PG_SUPPORT_GFX_SMG (1 << 1)
207 #define RADEON_PG_SUPPORT_GFX_DMG (1 << 2)
208 #define RADEON_PG_SUPPORT_UVD (1 << 3)
209 #define RADEON_PG_SUPPORT_VCE (1 << 4)
210 #define RADEON_PG_SUPPORT_CP (1 << 5)
211 #define RADEON_PG_SUPPORT_GDS (1 << 6)
212 #define RADEON_PG_SUPPORT_RLC_SMU_HS (1 << 7)
213 #define RADEON_PG_SUPPORT_SDMA (1 << 8)
214 #define RADEON_PG_SUPPORT_ACP (1 << 9)
215 #define RADEON_PG_SUPPORT_SAMU (1 << 10)
216
217 /* max cursor sizes (in pixels) */
218 #define CURSOR_WIDTH 64
219 #define CURSOR_HEIGHT 64
220
221 #define CIK_CURSOR_WIDTH 128
222 #define CIK_CURSOR_HEIGHT 128
223
224 /*
225 * Errata workarounds.
226 */
227 enum radeon_pll_errata {
228 CHIP_ERRATA_R300_CG = 0x00000001,
229 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
230 CHIP_ERRATA_PLL_DELAY = 0x00000004
231 };
232
233
234 struct radeon_device;
235
236 #ifdef __NetBSD__
237 extern struct radeon_device *radeon_device_private(device_t);
238 #endif
239
240 /*
241 * BIOS.
242 */
243 bool radeon_get_bios(struct radeon_device *rdev);
244
245 /*
246 * Dummy page
247 */
248 struct radeon_dummy_page {
249 #ifdef __NetBSD__
250 bus_dma_segment_t rdp_seg;
251 bus_dmamap_t rdp_map;
252 #else
253 struct page *page;
254 #endif
255 dma_addr_t addr;
256 };
257 int radeon_dummy_page_init(struct radeon_device *rdev);
258 void radeon_dummy_page_fini(struct radeon_device *rdev);
259
260
261 /*
262 * Clocks
263 */
264 struct radeon_clock {
265 struct radeon_pll p1pll;
266 struct radeon_pll p2pll;
267 struct radeon_pll dcpll;
268 struct radeon_pll spll;
269 struct radeon_pll mpll;
270 /* 10 Khz units */
271 uint32_t default_mclk;
272 uint32_t default_sclk;
273 uint32_t default_dispclk;
274 uint32_t current_dispclk;
275 uint32_t dp_extclk;
276 uint32_t max_pixel_clock;
277 };
278
279 /*
280 * Power management
281 */
282 int radeon_pm_init(struct radeon_device *rdev);
283 int radeon_pm_late_init(struct radeon_device *rdev);
284 void radeon_pm_fini(struct radeon_device *rdev);
285 void radeon_pm_compute_clocks(struct radeon_device *rdev);
286 void radeon_pm_suspend(struct radeon_device *rdev);
287 void radeon_pm_resume(struct radeon_device *rdev);
288 void radeon_combios_get_power_modes(struct radeon_device *rdev);
289 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
290 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
291 u8 clock_type,
292 u32 clock,
293 bool strobe_mode,
294 struct atom_clock_dividers *dividers);
295 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
296 u32 clock,
297 bool strobe_mode,
298 struct atom_mpll_param *mpll_param);
299 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
300 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
301 u16 voltage_level, u8 voltage_type,
302 u32 *gpio_value, u32 *gpio_mask);
303 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
304 u32 eng_clock, u32 mem_clock);
305 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
306 u8 voltage_type, u16 *voltage_step);
307 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
308 u16 voltage_id, u16 *voltage);
309 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
310 u16 *voltage,
311 u16 leakage_idx);
312 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
313 u16 *leakage_id);
314 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
315 u16 *vddc, u16 *vddci,
316 u16 virtual_voltage_id,
317 u16 vbios_voltage_id);
318 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
319 u8 voltage_type,
320 u16 nominal_voltage,
321 u16 *true_voltage);
322 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
323 u8 voltage_type, u16 *min_voltage);
324 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
325 u8 voltage_type, u16 *max_voltage);
326 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
327 u8 voltage_type, u8 voltage_mode,
328 struct atom_voltage_table *voltage_table);
329 bool radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
330 u8 voltage_type, u8 voltage_mode);
331 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
332 u32 mem_clock);
333 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
334 u32 mem_clock);
335 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
336 u8 module_index,
337 struct atom_mc_reg_table *reg_table);
338 int radeon_atom_get_memory_info(struct radeon_device *rdev,
339 u8 module_index, struct atom_memory_info *mem_info);
340 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
341 bool gddr5, u8 module_index,
342 struct atom_memory_clock_range_table *mclk_range_table);
343 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
344 u16 voltage_id, u16 *voltage);
345 void rs690_pm_info(struct radeon_device *rdev);
346 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
347 unsigned *bankh, unsigned *mtaspect,
348 unsigned *tile_split);
349
350 /*
351 * Fences.
352 */
353 struct radeon_fence_driver {
354 uint32_t scratch_reg;
355 uint64_t gpu_addr;
356 volatile uint32_t *cpu_addr;
357 /* sync_seq is protected by ring emission lock */
358 uint64_t sync_seq[RADEON_NUM_RINGS];
359 atomic64_t last_seq;
360 bool initialized;
361 };
362
363 struct radeon_fence {
364 struct radeon_device *rdev;
365 struct kref kref;
366 /* protected by radeon_fence.lock */
367 uint64_t seq;
368 /* RB, DMA, etc. */
369 unsigned ring;
370 };
371
372 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
373 int radeon_fence_driver_init(struct radeon_device *rdev);
374 void radeon_fence_driver_fini(struct radeon_device *rdev);
375 void radeon_fence_driver_force_completion(struct radeon_device *rdev);
376 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
377 void radeon_fence_process(struct radeon_device *rdev, int ring);
378 bool radeon_fence_signaled(struct radeon_fence *fence);
379 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
380 int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
381 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring);
382 int radeon_fence_wait_any(struct radeon_device *rdev,
383 struct radeon_fence **fences,
384 bool intr);
385 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
386 void radeon_fence_unref(struct radeon_fence **fence);
387 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
388 bool radeon_fence_need_sync(struct radeon_fence *fence, int ring);
389 void radeon_fence_note_sync(struct radeon_fence *fence, int ring);
radeon_fence_later(struct radeon_fence * a,struct radeon_fence * b)390 static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
391 struct radeon_fence *b)
392 {
393 if (!a) {
394 return b;
395 }
396
397 if (!b) {
398 return a;
399 }
400
401 BUG_ON(a->ring != b->ring);
402
403 if (a->seq > b->seq) {
404 return a;
405 } else {
406 return b;
407 }
408 }
409
radeon_fence_is_earlier(struct radeon_fence * a,struct radeon_fence * b)410 static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
411 struct radeon_fence *b)
412 {
413 if (!a) {
414 return false;
415 }
416
417 if (!b) {
418 return true;
419 }
420
421 BUG_ON(a->ring != b->ring);
422
423 return a->seq < b->seq;
424 }
425
426 /*
427 * Tiling registers
428 */
429 struct radeon_surface_reg {
430 struct radeon_bo *bo;
431 };
432
433 #define RADEON_GEM_MAX_SURFACES 8
434
435 /*
436 * TTM.
437 */
438 struct radeon_mman {
439 struct ttm_bo_global_ref bo_global_ref;
440 struct drm_global_reference mem_global_ref;
441 struct ttm_bo_device bdev;
442 bool mem_global_referenced;
443 bool initialized;
444
445 #if defined(CONFIG_DEBUG_FS)
446 struct dentry *vram;
447 struct dentry *gtt;
448 #endif
449 };
450
451 /* bo virtual address in a specific vm */
452 struct radeon_bo_va {
453 /* protected by bo being reserved */
454 struct list_head bo_list;
455 uint64_t soffset;
456 uint64_t eoffset;
457 uint32_t flags;
458 bool valid;
459 unsigned ref_count;
460
461 /* protected by vm mutex */
462 struct list_head vm_list;
463
464 /* constant after initialization */
465 struct radeon_vm *vm;
466 struct radeon_bo *bo;
467 };
468
469 struct radeon_bo {
470 /* Protected by gem.mutex */
471 struct list_head list;
472 /* Protected by tbo.reserved */
473 u32 initial_domain;
474 u32 placements[3];
475 struct ttm_placement placement;
476 struct ttm_buffer_object tbo;
477 struct ttm_bo_kmap_obj kmap;
478 unsigned pin_count;
479 void *kptr;
480 u32 tiling_flags;
481 u32 pitch;
482 int surface_reg;
483 /* list of all virtual address to which this bo
484 * is associated to
485 */
486 struct list_head va;
487 /* Constant after initialization */
488 struct radeon_device *rdev;
489 struct drm_gem_object gem_base;
490
491 struct ttm_bo_kmap_obj dma_buf_vmap;
492 #ifndef __NetBSD__ /* XXX pid??? */
493 pid_t pid;
494 #endif
495 };
496 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
497
498 int radeon_gem_debugfs_init(struct radeon_device *rdev);
499
500 /* sub-allocation manager, it has to be protected by another lock.
501 * By conception this is an helper for other part of the driver
502 * like the indirect buffer or semaphore, which both have their
503 * locking.
504 *
505 * Principe is simple, we keep a list of sub allocation in offset
506 * order (first entry has offset == 0, last entry has the highest
507 * offset).
508 *
509 * When allocating new object we first check if there is room at
510 * the end total_size - (last_object_offset + last_object_size) >=
511 * alloc_size. If so we allocate new object there.
512 *
513 * When there is not enough room at the end, we start waiting for
514 * each sub object until we reach object_offset+object_size >=
515 * alloc_size, this object then become the sub object we return.
516 *
517 * Alignment can't be bigger than page size.
518 *
519 * Hole are not considered for allocation to keep things simple.
520 * Assumption is that there won't be hole (all object on same
521 * alignment).
522 */
523 struct radeon_sa_manager {
524 #ifdef __NetBSD__
525 spinlock_t wq_lock;
526 drm_waitqueue_t wq;
527 #else
528 wait_queue_head_t wq;
529 #endif
530 struct radeon_bo *bo;
531 struct list_head *hole;
532 struct list_head flist[RADEON_NUM_RINGS];
533 struct list_head olist;
534 unsigned size;
535 uint64_t gpu_addr;
536 void *cpu_ptr;
537 uint32_t domain;
538 uint32_t align;
539 };
540
541 struct radeon_sa_bo;
542
543 /* sub-allocation buffer */
544 struct radeon_sa_bo {
545 struct list_head olist;
546 struct list_head flist;
547 struct radeon_sa_manager *manager;
548 unsigned soffset;
549 unsigned eoffset;
550 struct radeon_fence *fence;
551 };
552
553 /*
554 * GEM objects.
555 */
556 struct radeon_gem {
557 struct mutex mutex;
558 struct list_head objects;
559 };
560
561 int radeon_gem_init(struct radeon_device *rdev);
562 void radeon_gem_fini(struct radeon_device *rdev);
563 int radeon_gem_object_create(struct radeon_device *rdev, int size,
564 int alignment, int initial_domain,
565 bool discardable, bool kernel,
566 struct drm_gem_object **obj);
567
568 int radeon_mode_dumb_create(struct drm_file *file_priv,
569 struct drm_device *dev,
570 struct drm_mode_create_dumb *args);
571 int radeon_mode_dumb_mmap(struct drm_file *filp,
572 struct drm_device *dev,
573 uint32_t handle, uint64_t *offset_p);
574
575 /*
576 * Semaphores.
577 */
578 struct radeon_semaphore {
579 struct radeon_sa_bo *sa_bo;
580 signed waiters;
581 uint64_t gpu_addr;
582 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
583 };
584
585 int radeon_semaphore_create(struct radeon_device *rdev,
586 struct radeon_semaphore **semaphore);
587 bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
588 struct radeon_semaphore *semaphore);
589 bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
590 struct radeon_semaphore *semaphore);
591 void radeon_semaphore_sync_to(struct radeon_semaphore *semaphore,
592 struct radeon_fence *fence);
593 int radeon_semaphore_sync_rings(struct radeon_device *rdev,
594 struct radeon_semaphore *semaphore,
595 int waiting_ring);
596 void radeon_semaphore_free(struct radeon_device *rdev,
597 struct radeon_semaphore **semaphore,
598 struct radeon_fence *fence);
599
600 /*
601 * GART structures, functions & helpers
602 */
603 struct radeon_mc;
604
605 #define RADEON_GPU_PAGE_SIZE 4096
606 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
607 #define RADEON_GPU_PAGE_SHIFT 12
608 #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK)
609
610 struct radeon_gart {
611 #ifdef __NetBSD__
612 bus_dma_segment_t rg_table_seg;
613 bus_dmamap_t rg_table_map;
614 #endif
615 dma_addr_t table_addr;
616 struct radeon_bo *robj;
617 void *ptr;
618 unsigned num_gpu_pages;
619 unsigned num_cpu_pages;
620 unsigned table_size;
621 struct page **pages;
622 dma_addr_t *pages_addr;
623 bool ready;
624 };
625
626 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
627 void radeon_gart_table_ram_free(struct radeon_device *rdev);
628 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
629 void radeon_gart_table_vram_free(struct radeon_device *rdev);
630 int radeon_gart_table_vram_pin(struct radeon_device *rdev);
631 void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
632 int radeon_gart_init(struct radeon_device *rdev);
633 void radeon_gart_fini(struct radeon_device *rdev);
634 #ifdef __NetBSD__
635 void radeon_gart_unbind(struct radeon_device *rdev, unsigned gpu_start,
636 unsigned npages);
637 int radeon_gart_bind(struct radeon_device *rdev, unsigned gpu_start,
638 unsigned npages, struct page **pages,
639 bus_dmamap_t dmamap);
640 #else
641 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
642 int pages);
643 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
644 int pages, struct page **pagelist,
645 dma_addr_t *dma_addr);
646 #endif
647 void radeon_gart_restore(struct radeon_device *rdev);
648
649
650 /*
651 * GPU MC structures, functions & helpers
652 */
653 struct radeon_mc {
654 resource_size_t aper_size;
655 resource_size_t aper_base;
656 resource_size_t agp_base;
657 /* for some chips with <= 32MB we need to lie
658 * about vram size near mc fb location */
659 u64 mc_vram_size;
660 u64 visible_vram_size;
661 u64 gtt_size;
662 u64 gtt_start;
663 u64 gtt_end;
664 u64 vram_start;
665 u64 vram_end;
666 unsigned vram_width;
667 u64 real_vram_size;
668 int vram_mtrr;
669 bool vram_is_ddr;
670 bool igp_sideport_enabled;
671 u64 gtt_base_align;
672 u64 mc_mask;
673 };
674
675 bool radeon_combios_sideport_present(struct radeon_device *rdev);
676 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
677
678 /*
679 * GPU scratch registers structures, functions & helpers
680 */
681 struct radeon_scratch {
682 unsigned num_reg;
683 uint32_t reg_base;
684 bool free[32];
685 uint32_t reg[32];
686 };
687
688 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
689 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
690
691 /*
692 * GPU doorbell structures, functions & helpers
693 */
694 #define RADEON_MAX_DOORBELLS 1024 /* Reserve at most 1024 doorbell slots for radeon-owned rings. */
695
696 struct radeon_doorbell {
697 /* doorbell mmio */
698 resource_size_t base;
699 resource_size_t size;
700 #ifdef __NetBSD__
701 bus_space_tag_t bst;
702 bus_space_handle_t bsh;
703 #else
704 u32 __iomem *ptr;
705 #endif
706 u32 num_doorbells; /* Number of doorbells actually reserved for radeon. */
707 #ifdef __NetBSD__
708 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, CHAR_BIT*sizeof(unsigned long))];
709 #else
710 unsigned long used[DIV_ROUND_UP(RADEON_MAX_DOORBELLS, BITS_PER_LONG)];
711 #endif
712 };
713
714 int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
715 void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
716
717 /*
718 * IRQS.
719 */
720
721 struct radeon_unpin_work {
722 struct work_struct work;
723 struct radeon_device *rdev;
724 int crtc_id;
725 struct radeon_fence *fence;
726 struct drm_pending_vblank_event *event;
727 struct radeon_bo *old_rbo;
728 u64 new_crtc_base;
729 };
730
731 struct r500_irq_stat_regs {
732 u32 disp_int;
733 u32 hdmi0_status;
734 };
735
736 struct r600_irq_stat_regs {
737 u32 disp_int;
738 u32 disp_int_cont;
739 u32 disp_int_cont2;
740 u32 d1grph_int;
741 u32 d2grph_int;
742 u32 hdmi0_status;
743 u32 hdmi1_status;
744 };
745
746 struct evergreen_irq_stat_regs {
747 u32 disp_int;
748 u32 disp_int_cont;
749 u32 disp_int_cont2;
750 u32 disp_int_cont3;
751 u32 disp_int_cont4;
752 u32 disp_int_cont5;
753 u32 d1grph_int;
754 u32 d2grph_int;
755 u32 d3grph_int;
756 u32 d4grph_int;
757 u32 d5grph_int;
758 u32 d6grph_int;
759 u32 afmt_status1;
760 u32 afmt_status2;
761 u32 afmt_status3;
762 u32 afmt_status4;
763 u32 afmt_status5;
764 u32 afmt_status6;
765 };
766
767 struct cik_irq_stat_regs {
768 u32 disp_int;
769 u32 disp_int_cont;
770 u32 disp_int_cont2;
771 u32 disp_int_cont3;
772 u32 disp_int_cont4;
773 u32 disp_int_cont5;
774 u32 disp_int_cont6;
775 u32 d1grph_int;
776 u32 d2grph_int;
777 u32 d3grph_int;
778 u32 d4grph_int;
779 u32 d5grph_int;
780 u32 d6grph_int;
781 };
782
783 union radeon_irq_stat_regs {
784 struct r500_irq_stat_regs r500;
785 struct r600_irq_stat_regs r600;
786 struct evergreen_irq_stat_regs evergreen;
787 struct cik_irq_stat_regs cik;
788 };
789
790 #define RADEON_MAX_HPD_PINS 7
791 #define RADEON_MAX_CRTCS 6
792 #define RADEON_MAX_AFMT_BLOCKS 7
793
794 struct radeon_irq {
795 bool installed;
796 spinlock_t lock;
797 atomic_t ring_int[RADEON_NUM_RINGS];
798 bool crtc_vblank_int[RADEON_MAX_CRTCS];
799 atomic_t pflip[RADEON_MAX_CRTCS];
800 #ifdef __NetBSD__
801 spinlock_t vblank_lock;
802 drm_waitqueue_t vblank_queue;
803 #else
804 wait_queue_head_t vblank_queue;
805 #endif
806 bool hpd[RADEON_MAX_HPD_PINS];
807 bool afmt[RADEON_MAX_AFMT_BLOCKS];
808 union radeon_irq_stat_regs stat_regs;
809 bool dpm_thermal;
810 };
811
812 int radeon_irq_kms_init(struct radeon_device *rdev);
813 void radeon_irq_kms_fini(struct radeon_device *rdev);
814 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring);
815 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring);
816 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
817 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
818 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block);
819 void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block);
820 void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
821 void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask);
822
823 /*
824 * CP & rings.
825 */
826
827 struct radeon_ib {
828 struct radeon_sa_bo *sa_bo;
829 uint32_t length_dw;
830 uint64_t gpu_addr;
831 uint32_t *ptr;
832 int ring;
833 struct radeon_fence *fence;
834 struct radeon_vm *vm;
835 bool is_const_ib;
836 struct radeon_semaphore *semaphore;
837 };
838
839 struct radeon_ring {
840 struct radeon_bo *ring_obj;
841 volatile uint32_t *ring;
842 unsigned rptr_offs;
843 unsigned rptr_save_reg;
844 u64 next_rptr_gpu_addr;
845 volatile u32 *next_rptr_cpu_addr;
846 unsigned wptr;
847 unsigned wptr_old;
848 unsigned ring_size;
849 unsigned ring_free_dw;
850 int count_dw;
851 atomic_t last_rptr;
852 atomic64_t last_activity;
853 uint64_t gpu_addr;
854 uint32_t align_mask;
855 uint32_t ptr_mask;
856 bool ready;
857 u32 nop;
858 u32 idx;
859 u64 last_semaphore_signal_addr;
860 u64 last_semaphore_wait_addr;
861 /* for CIK queues */
862 u32 me;
863 u32 pipe;
864 u32 queue;
865 struct radeon_bo *mqd_obj;
866 u32 doorbell_index;
867 unsigned wptr_offs;
868 };
869
870 struct radeon_mec {
871 struct radeon_bo *hpd_eop_obj;
872 u64 hpd_eop_gpu_addr;
873 u32 num_pipe;
874 u32 num_mec;
875 u32 num_queue;
876 };
877
878 /*
879 * VM
880 */
881
882 /* maximum number of VMIDs */
883 #define RADEON_NUM_VM 16
884
885 /* defines number of bits in page table versus page directory,
886 * a page is 4KB so we have 12 bits offset, 9 bits in the page
887 * table and the remaining 19 bits are in the page directory */
888 #define RADEON_VM_BLOCK_SIZE 9
889
890 /* number of entries in page table */
891 #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE)
892
893 /* PTBs (Page Table Blocks) need to be aligned to 32K */
894 #define RADEON_VM_PTB_ALIGN_SIZE 32768
895 #define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1)
896 #define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK)
897
898 #define R600_PTE_VALID (1 << 0)
899 #define R600_PTE_SYSTEM (1 << 1)
900 #define R600_PTE_SNOOPED (1 << 2)
901 #define R600_PTE_READABLE (1 << 5)
902 #define R600_PTE_WRITEABLE (1 << 6)
903
904 struct radeon_vm_pt {
905 struct radeon_bo *bo;
906 uint64_t addr;
907 };
908
909 struct radeon_vm {
910 struct list_head va;
911 unsigned id;
912
913 /* contains the page directory */
914 struct radeon_bo *page_directory;
915 uint64_t pd_gpu_addr;
916 unsigned max_pde_used;
917
918 /* array of page tables, one for each page directory entry */
919 struct radeon_vm_pt *page_tables;
920
921 struct mutex mutex;
922 /* last fence for cs using this vm */
923 struct radeon_fence *fence;
924 /* last flush or NULL if we still need to flush */
925 struct radeon_fence *last_flush;
926 /* last use of vmid */
927 struct radeon_fence *last_id_use;
928 };
929
930 struct radeon_vm_manager {
931 struct radeon_fence *active[RADEON_NUM_VM];
932 uint32_t max_pfn;
933 /* number of VMIDs */
934 unsigned nvm;
935 /* vram base address for page table entry */
936 u64 vram_base_offset;
937 /* is vm enabled? */
938 bool enabled;
939 };
940
941 /*
942 * file private structure
943 */
944 struct radeon_fpriv {
945 struct radeon_vm vm;
946 };
947
948 /*
949 * R6xx+ IH ring
950 */
951 struct r600_ih {
952 struct radeon_bo *ring_obj;
953 volatile uint32_t *ring;
954 unsigned rptr;
955 unsigned ring_size;
956 uint64_t gpu_addr;
957 uint32_t ptr_mask;
958 atomic_t lock;
959 bool enabled;
960 };
961
962 /*
963 * RLC stuff
964 */
965 #include "clearstate_defs.h"
966
967 struct radeon_rlc {
968 /* for power gating */
969 struct radeon_bo *save_restore_obj;
970 uint64_t save_restore_gpu_addr;
971 volatile uint32_t *sr_ptr;
972 const u32 *reg_list;
973 u32 reg_list_size;
974 /* for clear state */
975 struct radeon_bo *clear_state_obj;
976 uint64_t clear_state_gpu_addr;
977 volatile uint32_t *cs_ptr;
978 const struct cs_section_def *cs_data;
979 u32 clear_state_size;
980 /* for cp tables */
981 struct radeon_bo *cp_table_obj;
982 uint64_t cp_table_gpu_addr;
983 volatile uint32_t *cp_table_ptr;
984 u32 cp_table_size;
985 };
986
987 int radeon_ib_get(struct radeon_device *rdev, int ring,
988 struct radeon_ib *ib, struct radeon_vm *vm,
989 unsigned size);
990 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
991 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
992 struct radeon_ib *const_ib);
993 int radeon_ib_pool_init(struct radeon_device *rdev);
994 void radeon_ib_pool_fini(struct radeon_device *rdev);
995 int radeon_ib_ring_tests(struct radeon_device *rdev);
996 /* Ring access between begin & end cannot sleep */
997 bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,
998 struct radeon_ring *ring);
999 void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
1000 int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1001 int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
1002 void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
1003 void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
1004 void radeon_ring_undo(struct radeon_ring *ring);
1005 void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
1006 int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
1007 void radeon_ring_lockup_update(struct radeon_device *rdev,
1008 struct radeon_ring *ring);
1009 bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
1010 unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,
1011 uint32_t **data);
1012 int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
1013 unsigned size, uint32_t *data);
1014 int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
1015 unsigned rptr_offs, u32 nop);
1016 void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
1017
1018
1019 /* r600 async dma */
1020 void r600_dma_stop(struct radeon_device *rdev);
1021 int r600_dma_resume(struct radeon_device *rdev);
1022 void r600_dma_fini(struct radeon_device *rdev);
1023
1024 void cayman_dma_stop(struct radeon_device *rdev);
1025 int cayman_dma_resume(struct radeon_device *rdev);
1026 void cayman_dma_fini(struct radeon_device *rdev);
1027
1028 /*
1029 * CS.
1030 */
1031 struct radeon_cs_reloc {
1032 struct drm_gem_object *gobj;
1033 struct radeon_bo *robj;
1034 struct ttm_validate_buffer tv;
1035 uint64_t gpu_offset;
1036 unsigned domain;
1037 unsigned alt_domain;
1038 uint32_t tiling_flags;
1039 uint32_t handle;
1040 };
1041
1042 struct radeon_cs_chunk {
1043 uint32_t chunk_id;
1044 uint32_t length_dw;
1045 uint32_t *kdata;
1046 void __user *user_ptr;
1047 };
1048
1049 struct radeon_cs_parser {
1050 struct device *dev;
1051 struct radeon_device *rdev;
1052 struct drm_file *filp;
1053 /* chunks */
1054 unsigned nchunks;
1055 struct radeon_cs_chunk *chunks;
1056 uint64_t *chunks_array;
1057 /* IB */
1058 unsigned idx;
1059 /* relocations */
1060 unsigned nrelocs;
1061 struct radeon_cs_reloc *relocs;
1062 struct radeon_cs_reloc **relocs_ptr;
1063 struct radeon_cs_reloc *vm_bos;
1064 struct list_head validated;
1065 unsigned dma_reloc_idx;
1066 /* indices of various chunks */
1067 int chunk_ib_idx;
1068 int chunk_relocs_idx;
1069 int chunk_flags_idx;
1070 int chunk_const_ib_idx;
1071 struct radeon_ib ib;
1072 struct radeon_ib const_ib;
1073 void *track;
1074 unsigned family;
1075 int parser_error;
1076 u32 cs_flags;
1077 u32 ring;
1078 s32 priority;
1079 struct ww_acquire_ctx ticket;
1080 };
1081
radeon_get_ib_value(struct radeon_cs_parser * p,int idx)1082 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1083 {
1084 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
1085
1086 if (ibc->kdata)
1087 return ibc->kdata[idx];
1088 return p->ib.ptr[idx];
1089 }
1090
1091
1092 struct radeon_cs_packet {
1093 unsigned idx;
1094 unsigned type;
1095 unsigned reg;
1096 unsigned opcode;
1097 int count;
1098 unsigned one_reg_wr;
1099 };
1100
1101 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
1102 struct radeon_cs_packet *pkt,
1103 unsigned idx, unsigned reg);
1104 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
1105 struct radeon_cs_packet *pkt);
1106
1107
1108 /*
1109 * AGP
1110 */
1111 int radeon_agp_init(struct radeon_device *rdev);
1112 void radeon_agp_resume(struct radeon_device *rdev);
1113 void radeon_agp_suspend(struct radeon_device *rdev);
1114 void radeon_agp_fini(struct radeon_device *rdev);
1115
1116
1117 /*
1118 * Writeback
1119 */
1120 struct radeon_wb {
1121 struct radeon_bo *wb_obj;
1122 volatile uint32_t *wb;
1123 uint64_t gpu_addr;
1124 bool enabled;
1125 bool use_event;
1126 };
1127
1128 #define RADEON_WB_SCRATCH_OFFSET 0
1129 #define RADEON_WB_RING0_NEXT_RPTR 256
1130 #define RADEON_WB_CP_RPTR_OFFSET 1024
1131 #define RADEON_WB_CP1_RPTR_OFFSET 1280
1132 #define RADEON_WB_CP2_RPTR_OFFSET 1536
1133 #define R600_WB_DMA_RPTR_OFFSET 1792
1134 #define R600_WB_IH_WPTR_OFFSET 2048
1135 #define CAYMAN_WB_DMA1_RPTR_OFFSET 2304
1136 #define R600_WB_EVENT_OFFSET 3072
1137 #define CIK_WB_CP1_WPTR_OFFSET 3328
1138 #define CIK_WB_CP2_WPTR_OFFSET 3584
1139
1140 /**
1141 * struct radeon_pm - power management datas
1142 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
1143 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
1144 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
1145 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
1146 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
1147 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
1148 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
1149 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
1150 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
1151 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
1152 * @needed_bandwidth: current bandwidth needs
1153 *
1154 * It keeps track of various data needed to take powermanagement decision.
1155 * Bandwidth need is used to determine minimun clock of the GPU and memory.
1156 * Equation between gpu/memory clock and available bandwidth is hw dependent
1157 * (type of memory, bus size, efficiency, ...)
1158 */
1159
1160 enum radeon_pm_method {
1161 PM_METHOD_PROFILE,
1162 PM_METHOD_DYNPM,
1163 PM_METHOD_DPM,
1164 };
1165
1166 enum radeon_dynpm_state {
1167 DYNPM_STATE_DISABLED,
1168 DYNPM_STATE_MINIMUM,
1169 DYNPM_STATE_PAUSED,
1170 DYNPM_STATE_ACTIVE,
1171 DYNPM_STATE_SUSPENDED,
1172 };
1173 enum radeon_dynpm_action {
1174 DYNPM_ACTION_NONE,
1175 DYNPM_ACTION_MINIMUM,
1176 DYNPM_ACTION_DOWNCLOCK,
1177 DYNPM_ACTION_UPCLOCK,
1178 DYNPM_ACTION_DEFAULT
1179 };
1180
1181 enum radeon_voltage_type {
1182 VOLTAGE_NONE = 0,
1183 VOLTAGE_GPIO,
1184 VOLTAGE_VDDC,
1185 VOLTAGE_SW
1186 };
1187
1188 enum radeon_pm_state_type {
1189 /* not used for dpm */
1190 POWER_STATE_TYPE_DEFAULT,
1191 POWER_STATE_TYPE_POWERSAVE,
1192 /* user selectable states */
1193 POWER_STATE_TYPE_BATTERY,
1194 POWER_STATE_TYPE_BALANCED,
1195 POWER_STATE_TYPE_PERFORMANCE,
1196 /* internal states */
1197 POWER_STATE_TYPE_INTERNAL_UVD,
1198 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1199 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1200 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1201 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1202 POWER_STATE_TYPE_INTERNAL_BOOT,
1203 POWER_STATE_TYPE_INTERNAL_THERMAL,
1204 POWER_STATE_TYPE_INTERNAL_ACPI,
1205 POWER_STATE_TYPE_INTERNAL_ULV,
1206 POWER_STATE_TYPE_INTERNAL_3DPERF,
1207 };
1208
1209 enum radeon_pm_profile_type {
1210 PM_PROFILE_DEFAULT,
1211 PM_PROFILE_AUTO,
1212 PM_PROFILE_LOW,
1213 PM_PROFILE_MID,
1214 PM_PROFILE_HIGH,
1215 };
1216
1217 #define PM_PROFILE_DEFAULT_IDX 0
1218 #define PM_PROFILE_LOW_SH_IDX 1
1219 #define PM_PROFILE_MID_SH_IDX 2
1220 #define PM_PROFILE_HIGH_SH_IDX 3
1221 #define PM_PROFILE_LOW_MH_IDX 4
1222 #define PM_PROFILE_MID_MH_IDX 5
1223 #define PM_PROFILE_HIGH_MH_IDX 6
1224 #define PM_PROFILE_MAX 7
1225
1226 struct radeon_pm_profile {
1227 int dpms_off_ps_idx;
1228 int dpms_on_ps_idx;
1229 int dpms_off_cm_idx;
1230 int dpms_on_cm_idx;
1231 };
1232
1233 enum radeon_int_thermal_type {
1234 THERMAL_TYPE_NONE,
1235 THERMAL_TYPE_EXTERNAL,
1236 THERMAL_TYPE_EXTERNAL_GPIO,
1237 THERMAL_TYPE_RV6XX,
1238 THERMAL_TYPE_RV770,
1239 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1240 THERMAL_TYPE_EVERGREEN,
1241 THERMAL_TYPE_SUMO,
1242 THERMAL_TYPE_NI,
1243 THERMAL_TYPE_SI,
1244 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1245 THERMAL_TYPE_CI,
1246 THERMAL_TYPE_KV,
1247 };
1248
1249 struct radeon_voltage {
1250 enum radeon_voltage_type type;
1251 /* gpio voltage */
1252 struct radeon_gpio_rec gpio;
1253 u32 delay; /* delay in usec from voltage drop to sclk change */
1254 bool active_high; /* voltage drop is active when bit is high */
1255 /* VDDC voltage */
1256 u8 vddc_id; /* index into vddc voltage table */
1257 u8 vddci_id; /* index into vddci voltage table */
1258 bool vddci_enabled;
1259 /* r6xx+ sw */
1260 u16 voltage;
1261 /* evergreen+ vddci */
1262 u16 vddci;
1263 };
1264
1265 /* clock mode flags */
1266 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
1267
1268 struct radeon_pm_clock_info {
1269 /* memory clock */
1270 u32 mclk;
1271 /* engine clock */
1272 u32 sclk;
1273 /* voltage info */
1274 struct radeon_voltage voltage;
1275 /* standardized clock flags */
1276 u32 flags;
1277 };
1278
1279 /* state flags */
1280 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
1281
1282 struct radeon_power_state {
1283 enum radeon_pm_state_type type;
1284 struct radeon_pm_clock_info *clock_info;
1285 /* number of valid clock modes in this power state */
1286 int num_clock_modes;
1287 struct radeon_pm_clock_info *default_clock_mode;
1288 /* standardized state flags */
1289 u32 flags;
1290 u32 misc; /* vbios specific flags */
1291 u32 misc2; /* vbios specific flags */
1292 int pcie_lanes; /* pcie lanes */
1293 };
1294
1295 /*
1296 * Some modes are overclocked by very low value, accept them
1297 */
1298 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
1299
1300 enum radeon_dpm_auto_throttle_src {
1301 RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL,
1302 RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1303 };
1304
1305 enum radeon_dpm_event_src {
1306 RADEON_DPM_EVENT_SRC_ANALOG = 0,
1307 RADEON_DPM_EVENT_SRC_EXTERNAL = 1,
1308 RADEON_DPM_EVENT_SRC_DIGITAL = 2,
1309 RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1310 RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1311 };
1312
1313 #define RADEON_MAX_VCE_LEVELS 6
1314
1315 enum radeon_vce_level {
1316 RADEON_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1317 RADEON_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1318 RADEON_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1319 RADEON_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1320 RADEON_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1321 RADEON_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1322 };
1323
1324 struct radeon_ps {
1325 u32 caps; /* vbios flags */
1326 u32 class; /* vbios flags */
1327 u32 class2; /* vbios flags */
1328 /* UVD clocks */
1329 u32 vclk;
1330 u32 dclk;
1331 /* VCE clocks */
1332 u32 evclk;
1333 u32 ecclk;
1334 bool vce_active;
1335 enum radeon_vce_level vce_level;
1336 /* asic priv */
1337 void *ps_priv;
1338 };
1339
1340 struct radeon_dpm_thermal {
1341 /* thermal interrupt work */
1342 struct work_struct work;
1343 /* low temperature threshold */
1344 int min_temp;
1345 /* high temperature threshold */
1346 int max_temp;
1347 /* was interrupt low to high or high to low */
1348 bool high_to_low;
1349 };
1350
1351 enum radeon_clk_action
1352 {
1353 RADEON_SCLK_UP = 1,
1354 RADEON_SCLK_DOWN
1355 };
1356
1357 struct radeon_blacklist_clocks
1358 {
1359 u32 sclk;
1360 u32 mclk;
1361 enum radeon_clk_action action;
1362 };
1363
1364 struct radeon_clock_and_voltage_limits {
1365 u32 sclk;
1366 u32 mclk;
1367 u16 vddc;
1368 u16 vddci;
1369 };
1370
1371 struct radeon_clock_array {
1372 u32 count;
1373 u32 *values;
1374 };
1375
1376 struct radeon_clock_voltage_dependency_entry {
1377 u32 clk;
1378 u16 v;
1379 };
1380
1381 struct radeon_clock_voltage_dependency_table {
1382 u32 count;
1383 struct radeon_clock_voltage_dependency_entry *entries;
1384 };
1385
1386 union radeon_cac_leakage_entry {
1387 struct {
1388 u16 vddc;
1389 u32 leakage;
1390 };
1391 struct {
1392 u16 vddc1;
1393 u16 vddc2;
1394 u16 vddc3;
1395 };
1396 };
1397
1398 struct radeon_cac_leakage_table {
1399 u32 count;
1400 union radeon_cac_leakage_entry *entries;
1401 };
1402
1403 struct radeon_phase_shedding_limits_entry {
1404 u16 voltage;
1405 u32 sclk;
1406 u32 mclk;
1407 };
1408
1409 struct radeon_phase_shedding_limits_table {
1410 u32 count;
1411 struct radeon_phase_shedding_limits_entry *entries;
1412 };
1413
1414 struct radeon_uvd_clock_voltage_dependency_entry {
1415 u32 vclk;
1416 u32 dclk;
1417 u16 v;
1418 };
1419
1420 struct radeon_uvd_clock_voltage_dependency_table {
1421 u8 count;
1422 struct radeon_uvd_clock_voltage_dependency_entry *entries;
1423 };
1424
1425 struct radeon_vce_clock_voltage_dependency_entry {
1426 u32 ecclk;
1427 u32 evclk;
1428 u16 v;
1429 };
1430
1431 struct radeon_vce_clock_voltage_dependency_table {
1432 u8 count;
1433 struct radeon_vce_clock_voltage_dependency_entry *entries;
1434 };
1435
1436 struct radeon_ppm_table {
1437 u8 ppm_design;
1438 u16 cpu_core_number;
1439 u32 platform_tdp;
1440 u32 small_ac_platform_tdp;
1441 u32 platform_tdc;
1442 u32 small_ac_platform_tdc;
1443 u32 apu_tdp;
1444 u32 dgpu_tdp;
1445 u32 dgpu_ulv_power;
1446 u32 tj_max;
1447 };
1448
1449 struct radeon_cac_tdp_table {
1450 u16 tdp;
1451 u16 configurable_tdp;
1452 u16 tdc;
1453 u16 battery_power_limit;
1454 u16 small_power_limit;
1455 u16 low_cac_leakage;
1456 u16 high_cac_leakage;
1457 u16 maximum_power_delivery_limit;
1458 };
1459
1460 struct radeon_dpm_dynamic_state {
1461 struct radeon_clock_voltage_dependency_table vddc_dependency_on_sclk;
1462 struct radeon_clock_voltage_dependency_table vddci_dependency_on_mclk;
1463 struct radeon_clock_voltage_dependency_table vddc_dependency_on_mclk;
1464 struct radeon_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1465 struct radeon_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1466 struct radeon_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1467 struct radeon_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1468 struct radeon_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1469 struct radeon_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1470 struct radeon_clock_array valid_sclk_values;
1471 struct radeon_clock_array valid_mclk_values;
1472 struct radeon_clock_and_voltage_limits max_clock_voltage_on_dc;
1473 struct radeon_clock_and_voltage_limits max_clock_voltage_on_ac;
1474 u32 mclk_sclk_ratio;
1475 u32 sclk_mclk_delta;
1476 u16 vddc_vddci_delta;
1477 u16 min_vddc_for_pcie_gen2;
1478 struct radeon_cac_leakage_table cac_leakage_table;
1479 struct radeon_phase_shedding_limits_table phase_shedding_limits_table;
1480 struct radeon_ppm_table *ppm_table;
1481 struct radeon_cac_tdp_table *cac_tdp_table;
1482 };
1483
1484 struct radeon_dpm_fan {
1485 u16 t_min;
1486 u16 t_med;
1487 u16 t_high;
1488 u16 pwm_min;
1489 u16 pwm_med;
1490 u16 pwm_high;
1491 u8 t_hyst;
1492 u32 cycle_delay;
1493 u16 t_max;
1494 bool ucode_fan_control;
1495 };
1496
1497 enum radeon_pcie_gen {
1498 RADEON_PCIE_GEN1 = 0,
1499 RADEON_PCIE_GEN2 = 1,
1500 RADEON_PCIE_GEN3 = 2,
1501 RADEON_PCIE_GEN_INVALID = 0xffff
1502 };
1503
1504 enum radeon_dpm_forced_level {
1505 RADEON_DPM_FORCED_LEVEL_AUTO = 0,
1506 RADEON_DPM_FORCED_LEVEL_LOW = 1,
1507 RADEON_DPM_FORCED_LEVEL_HIGH = 2,
1508 };
1509
1510 struct radeon_vce_state {
1511 /* vce clocks */
1512 u32 evclk;
1513 u32 ecclk;
1514 /* gpu clocks */
1515 u32 sclk;
1516 u32 mclk;
1517 u8 clk_idx;
1518 u8 pstate;
1519 };
1520
1521 struct radeon_dpm {
1522 struct radeon_ps *ps;
1523 /* number of valid power states */
1524 int num_ps;
1525 /* current power state that is active */
1526 struct radeon_ps *current_ps;
1527 /* requested power state */
1528 struct radeon_ps *requested_ps;
1529 /* boot up power state */
1530 struct radeon_ps *boot_ps;
1531 /* default uvd power state */
1532 struct radeon_ps *uvd_ps;
1533 /* vce requirements */
1534 struct radeon_vce_state vce_states[RADEON_MAX_VCE_LEVELS];
1535 enum radeon_vce_level vce_level;
1536 enum radeon_pm_state_type state;
1537 enum radeon_pm_state_type user_state;
1538 u32 platform_caps;
1539 u32 voltage_response_time;
1540 u32 backbias_response_time;
1541 void *priv;
1542 u32 new_active_crtcs;
1543 int new_active_crtc_count;
1544 u32 current_active_crtcs;
1545 int current_active_crtc_count;
1546 struct radeon_dpm_dynamic_state dyn_state;
1547 struct radeon_dpm_fan fan;
1548 u32 tdp_limit;
1549 u32 near_tdp_limit;
1550 u32 near_tdp_limit_adjusted;
1551 u32 sq_ramping_threshold;
1552 u32 cac_leakage;
1553 u16 tdp_od_limit;
1554 u32 tdp_adjustment;
1555 u16 load_line_slope;
1556 bool power_control;
1557 bool ac_power;
1558 /* special states active */
1559 bool thermal_active;
1560 bool uvd_active;
1561 bool vce_active;
1562 /* thermal handling */
1563 struct radeon_dpm_thermal thermal;
1564 /* forced levels */
1565 enum radeon_dpm_forced_level forced_level;
1566 /* track UVD streams */
1567 unsigned sd;
1568 unsigned hd;
1569 };
1570
1571 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable);
1572 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable);
1573
1574 struct radeon_pm {
1575 struct mutex mutex;
1576 /* write locked while reprogramming mclk */
1577 struct rw_semaphore mclk_lock;
1578 u32 active_crtcs;
1579 int active_crtc_count;
1580 int req_vblank;
1581 bool vblank_sync;
1582 fixed20_12 max_bandwidth;
1583 fixed20_12 igp_sideport_mclk;
1584 fixed20_12 igp_system_mclk;
1585 fixed20_12 igp_ht_link_clk;
1586 fixed20_12 igp_ht_link_width;
1587 fixed20_12 k8_bandwidth;
1588 fixed20_12 sideport_bandwidth;
1589 fixed20_12 ht_bandwidth;
1590 fixed20_12 core_bandwidth;
1591 fixed20_12 sclk;
1592 fixed20_12 mclk;
1593 fixed20_12 needed_bandwidth;
1594 struct radeon_power_state *power_state;
1595 /* number of valid power states */
1596 int num_power_states;
1597 int current_power_state_index;
1598 int current_clock_mode_index;
1599 int requested_power_state_index;
1600 int requested_clock_mode_index;
1601 int default_power_state_index;
1602 u32 current_sclk;
1603 u32 current_mclk;
1604 u16 current_vddc;
1605 u16 current_vddci;
1606 u32 default_sclk;
1607 u32 default_mclk;
1608 u16 default_vddc;
1609 u16 default_vddci;
1610 struct radeon_i2c_chan *i2c_bus;
1611 /* selected pm method */
1612 enum radeon_pm_method pm_method;
1613 /* dynpm power management */
1614 struct delayed_work dynpm_idle_work;
1615 enum radeon_dynpm_state dynpm_state;
1616 enum radeon_dynpm_action dynpm_planned_action;
1617 unsigned long dynpm_action_timeout;
1618 bool dynpm_can_upclock;
1619 bool dynpm_can_downclock;
1620 /* profile-based power management */
1621 enum radeon_pm_profile_type profile;
1622 int profile_index;
1623 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
1624 /* internal thermal controller on rv6xx+ */
1625 enum radeon_int_thermal_type int_thermal_type;
1626 struct device *int_hwmon_dev;
1627 /* dpm */
1628 bool dpm_enabled;
1629 struct radeon_dpm dpm;
1630 };
1631
1632 int radeon_pm_get_type_index(struct radeon_device *rdev,
1633 enum radeon_pm_state_type ps_type,
1634 int instance);
1635 /*
1636 * UVD
1637 */
1638 #define RADEON_MAX_UVD_HANDLES 10
1639 #define RADEON_UVD_STACK_SIZE (1024*1024)
1640 #define RADEON_UVD_HEAP_SIZE (1024*1024)
1641
1642 struct radeon_uvd {
1643 struct radeon_bo *vcpu_bo;
1644 void *cpu_addr;
1645 uint64_t gpu_addr;
1646 void *saved_bo;
1647 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1648 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1649 unsigned img_size[RADEON_MAX_UVD_HANDLES];
1650 struct delayed_work idle_work;
1651 };
1652
1653 int radeon_uvd_init(struct radeon_device *rdev);
1654 void radeon_uvd_fini(struct radeon_device *rdev);
1655 int radeon_uvd_suspend(struct radeon_device *rdev);
1656 int radeon_uvd_resume(struct radeon_device *rdev);
1657 int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring,
1658 uint32_t handle, struct radeon_fence **fence);
1659 int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
1660 uint32_t handle, struct radeon_fence **fence);
1661 void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1662 void radeon_uvd_free_handles(struct radeon_device *rdev,
1663 struct drm_file *filp);
1664 int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1665 void radeon_uvd_note_usage(struct radeon_device *rdev);
1666 int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
1667 unsigned vclk, unsigned dclk,
1668 unsigned vco_min, unsigned vco_max,
1669 unsigned fb_factor, unsigned fb_mask,
1670 unsigned pd_min, unsigned pd_max,
1671 unsigned pd_even,
1672 unsigned *optimal_fb_div,
1673 unsigned *optimal_vclk_div,
1674 unsigned *optimal_dclk_div);
1675 int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
1676 unsigned cg_upll_func_cntl);
1677
1678 /*
1679 * VCE
1680 */
1681 #define RADEON_MAX_VCE_HANDLES 16
1682 #define RADEON_VCE_STACK_SIZE (1024*1024)
1683 #define RADEON_VCE_HEAP_SIZE (4*1024*1024)
1684
1685 struct radeon_vce {
1686 struct radeon_bo *vcpu_bo;
1687 uint64_t gpu_addr;
1688 unsigned fw_version;
1689 unsigned fb_version;
1690 atomic_t handles[RADEON_MAX_VCE_HANDLES];
1691 struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
1692 unsigned img_size[RADEON_MAX_VCE_HANDLES];
1693 struct delayed_work idle_work;
1694 };
1695
1696 int radeon_vce_init(struct radeon_device *rdev);
1697 void radeon_vce_fini(struct radeon_device *rdev);
1698 int radeon_vce_suspend(struct radeon_device *rdev);
1699 int radeon_vce_resume(struct radeon_device *rdev);
1700 int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
1701 uint32_t handle, struct radeon_fence **fence);
1702 int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
1703 uint32_t handle, struct radeon_fence **fence);
1704 void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
1705 void radeon_vce_note_usage(struct radeon_device *rdev);
1706 int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi, unsigned size);
1707 int radeon_vce_cs_parse(struct radeon_cs_parser *p);
1708 bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
1709 struct radeon_ring *ring,
1710 struct radeon_semaphore *semaphore,
1711 bool emit_wait);
1712 void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
1713 void radeon_vce_fence_emit(struct radeon_device *rdev,
1714 struct radeon_fence *fence);
1715 int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
1716 int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
1717
1718 struct r600_audio_pin {
1719 int channels;
1720 int rate;
1721 int bits_per_sample;
1722 u8 status_bits;
1723 u8 category_code;
1724 u32 offset;
1725 bool connected;
1726 u32 id;
1727 };
1728
1729 struct r600_audio {
1730 bool enabled;
1731 struct r600_audio_pin pin[RADEON_MAX_AFMT_BLOCKS];
1732 int num_pins;
1733 };
1734
1735 /*
1736 * Benchmarking
1737 */
1738 void radeon_benchmark(struct radeon_device *rdev, int test_number);
1739
1740
1741 /*
1742 * Testing
1743 */
1744 void radeon_test_moves(struct radeon_device *rdev);
1745 void radeon_test_ring_sync(struct radeon_device *rdev,
1746 struct radeon_ring *cpA,
1747 struct radeon_ring *cpB);
1748 void radeon_test_syncing(struct radeon_device *rdev);
1749
1750
1751 /*
1752 * Debugfs
1753 */
1754 struct radeon_debugfs {
1755 struct drm_info_list *files;
1756 unsigned num_files;
1757 };
1758
1759 int radeon_debugfs_add_files(struct radeon_device *rdev,
1760 struct drm_info_list *files,
1761 unsigned nfiles);
1762 int radeon_debugfs_fence_init(struct radeon_device *rdev);
1763
1764 /*
1765 * ASIC ring specific functions.
1766 */
1767 struct radeon_asic_ring {
1768 /* ring read/write ptr handling */
1769 u32 (*get_rptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1770 u32 (*get_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1771 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring);
1772
1773 /* validating and patching of IBs */
1774 int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
1775 int (*cs_parse)(struct radeon_cs_parser *p);
1776
1777 /* command emmit functions */
1778 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
1779 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
1780 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1781 struct radeon_semaphore *semaphore, bool emit_wait);
1782 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
1783
1784 /* testing functions */
1785 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1786 int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
1787 bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
1788
1789 /* deprecated */
1790 void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp);
1791 };
1792
1793 /*
1794 * ASIC specific functions.
1795 */
1796 struct radeon_asic {
1797 int (*init)(struct radeon_device *rdev);
1798 void (*fini)(struct radeon_device *rdev);
1799 int (*resume)(struct radeon_device *rdev);
1800 int (*suspend)(struct radeon_device *rdev);
1801 void (*vga_set_state)(struct radeon_device *rdev, bool state);
1802 int (*asic_reset)(struct radeon_device *rdev);
1803 /* ioctl hw specific callback. Some hw might want to perform special
1804 * operation on specific ioctl. For instance on wait idle some hw
1805 * might want to perform and HDP flush through MMIO as it seems that
1806 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1807 * through ring.
1808 */
1809 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
1810 /* check if 3D engine is idle */
1811 bool (*gui_idle)(struct radeon_device *rdev);
1812 /* wait for mc_idle */
1813 int (*mc_wait_for_idle)(struct radeon_device *rdev);
1814 /* get the reference clock */
1815 u32 (*get_xclk)(struct radeon_device *rdev);
1816 /* get the gpu clock counter */
1817 uint64_t (*get_gpu_clock_counter)(struct radeon_device *rdev);
1818 /* gart */
1819 struct {
1820 void (*tlb_flush)(struct radeon_device *rdev);
1821 int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
1822 } gart;
1823 struct {
1824 int (*init)(struct radeon_device *rdev);
1825 void (*fini)(struct radeon_device *rdev);
1826 void (*set_page)(struct radeon_device *rdev,
1827 struct radeon_ib *ib,
1828 uint64_t pe,
1829 uint64_t addr, unsigned count,
1830 uint32_t incr, uint32_t flags);
1831 } vm;
1832 /* ring specific callbacks */
1833 struct radeon_asic_ring *ring[RADEON_NUM_RINGS];
1834 /* irqs */
1835 struct {
1836 int (*set)(struct radeon_device *rdev);
1837 int (*process)(struct radeon_device *rdev);
1838 } irq;
1839 /* displays */
1840 struct {
1841 /* display watermarks */
1842 void (*bandwidth_update)(struct radeon_device *rdev);
1843 /* get frame count */
1844 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
1845 /* wait for vblank */
1846 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1847 /* set backlight level */
1848 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1849 /* get backlight level */
1850 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1851 /* audio callbacks */
1852 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1853 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1854 } display;
1855 /* copy functions for bo handling */
1856 struct {
1857 int (*blit)(struct radeon_device *rdev,
1858 uint64_t src_offset,
1859 uint64_t dst_offset,
1860 unsigned num_gpu_pages,
1861 struct radeon_fence **fence);
1862 u32 blit_ring_index;
1863 int (*dma)(struct radeon_device *rdev,
1864 uint64_t src_offset,
1865 uint64_t dst_offset,
1866 unsigned num_gpu_pages,
1867 struct radeon_fence **fence);
1868 u32 dma_ring_index;
1869 /* method used for bo copy */
1870 int (*copy)(struct radeon_device *rdev,
1871 uint64_t src_offset,
1872 uint64_t dst_offset,
1873 unsigned num_gpu_pages,
1874 struct radeon_fence **fence);
1875 /* ring used for bo copies */
1876 u32 copy_ring_index;
1877 } copy;
1878 /* surfaces */
1879 struct {
1880 int (*set_reg)(struct radeon_device *rdev, int reg,
1881 uint32_t tiling_flags, uint32_t pitch,
1882 uint32_t offset, uint32_t obj_size);
1883 void (*clear_reg)(struct radeon_device *rdev, int reg);
1884 } surface;
1885 /* hotplug detect */
1886 struct {
1887 void (*init)(struct radeon_device *rdev);
1888 void (*fini)(struct radeon_device *rdev);
1889 bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1890 void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
1891 } hpd;
1892 /* static power management */
1893 struct {
1894 void (*misc)(struct radeon_device *rdev);
1895 void (*prepare)(struct radeon_device *rdev);
1896 void (*finish)(struct radeon_device *rdev);
1897 void (*init_profile)(struct radeon_device *rdev);
1898 void (*get_dynpm_state)(struct radeon_device *rdev);
1899 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
1900 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
1901 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
1902 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
1903 int (*get_pcie_lanes)(struct radeon_device *rdev);
1904 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
1905 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
1906 int (*set_uvd_clocks)(struct radeon_device *rdev, u32 vclk, u32 dclk);
1907 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
1908 int (*get_temperature)(struct radeon_device *rdev);
1909 } pm;
1910 /* dynamic power management */
1911 struct {
1912 int (*init)(struct radeon_device *rdev);
1913 void (*setup_asic)(struct radeon_device *rdev);
1914 int (*enable)(struct radeon_device *rdev);
1915 int (*late_enable)(struct radeon_device *rdev);
1916 void (*disable)(struct radeon_device *rdev);
1917 int (*pre_set_power_state)(struct radeon_device *rdev);
1918 int (*set_power_state)(struct radeon_device *rdev);
1919 void (*post_set_power_state)(struct radeon_device *rdev);
1920 void (*display_configuration_changed)(struct radeon_device *rdev);
1921 void (*fini)(struct radeon_device *rdev);
1922 u32 (*get_sclk)(struct radeon_device *rdev, bool low);
1923 u32 (*get_mclk)(struct radeon_device *rdev, bool low);
1924 void (*print_power_state)(struct radeon_device *rdev, struct radeon_ps *ps);
1925 void (*debugfs_print_current_performance_level)(struct radeon_device *rdev, struct seq_file *m);
1926 int (*force_performance_level)(struct radeon_device *rdev, enum radeon_dpm_forced_level level);
1927 bool (*vblank_too_short)(struct radeon_device *rdev);
1928 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
1929 void (*enable_bapm)(struct radeon_device *rdev, bool enable);
1930 } dpm;
1931 /* pageflipping */
1932 struct {
1933 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1934 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1935 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1936 } pflip;
1937 };
1938
1939 /*
1940 * Asic structures
1941 */
1942 struct r100_asic {
1943 const unsigned *reg_safe_bm;
1944 unsigned reg_safe_bm_size;
1945 u32 hdp_cntl;
1946 };
1947
1948 struct r300_asic {
1949 const unsigned *reg_safe_bm;
1950 unsigned reg_safe_bm_size;
1951 u32 resync_scratch;
1952 u32 hdp_cntl;
1953 };
1954
1955 struct r600_asic {
1956 unsigned max_pipes;
1957 unsigned max_tile_pipes;
1958 unsigned max_simds;
1959 unsigned max_backends;
1960 unsigned max_gprs;
1961 unsigned max_threads;
1962 unsigned max_stack_entries;
1963 unsigned max_hw_contexts;
1964 unsigned max_gs_threads;
1965 unsigned sx_max_export_size;
1966 unsigned sx_max_export_pos_size;
1967 unsigned sx_max_export_smx_size;
1968 unsigned sq_num_cf_insts;
1969 unsigned tiling_nbanks;
1970 unsigned tiling_npipes;
1971 unsigned tiling_group_size;
1972 unsigned tile_config;
1973 unsigned backend_map;
1974 };
1975
1976 struct rv770_asic {
1977 unsigned max_pipes;
1978 unsigned max_tile_pipes;
1979 unsigned max_simds;
1980 unsigned max_backends;
1981 unsigned max_gprs;
1982 unsigned max_threads;
1983 unsigned max_stack_entries;
1984 unsigned max_hw_contexts;
1985 unsigned max_gs_threads;
1986 unsigned sx_max_export_size;
1987 unsigned sx_max_export_pos_size;
1988 unsigned sx_max_export_smx_size;
1989 unsigned sq_num_cf_insts;
1990 unsigned sx_num_of_sets;
1991 unsigned sc_prim_fifo_size;
1992 unsigned sc_hiz_tile_fifo_size;
1993 unsigned sc_earlyz_tile_fifo_fize;
1994 unsigned tiling_nbanks;
1995 unsigned tiling_npipes;
1996 unsigned tiling_group_size;
1997 unsigned tile_config;
1998 unsigned backend_map;
1999 };
2000
2001 struct evergreen_asic {
2002 unsigned num_ses;
2003 unsigned max_pipes;
2004 unsigned max_tile_pipes;
2005 unsigned max_simds;
2006 unsigned max_backends;
2007 unsigned max_gprs;
2008 unsigned max_threads;
2009 unsigned max_stack_entries;
2010 unsigned max_hw_contexts;
2011 unsigned max_gs_threads;
2012 unsigned sx_max_export_size;
2013 unsigned sx_max_export_pos_size;
2014 unsigned sx_max_export_smx_size;
2015 unsigned sq_num_cf_insts;
2016 unsigned sx_num_of_sets;
2017 unsigned sc_prim_fifo_size;
2018 unsigned sc_hiz_tile_fifo_size;
2019 unsigned sc_earlyz_tile_fifo_size;
2020 unsigned tiling_nbanks;
2021 unsigned tiling_npipes;
2022 unsigned tiling_group_size;
2023 unsigned tile_config;
2024 unsigned backend_map;
2025 };
2026
2027 struct cayman_asic {
2028 unsigned max_shader_engines;
2029 unsigned max_pipes_per_simd;
2030 unsigned max_tile_pipes;
2031 unsigned max_simds_per_se;
2032 unsigned max_backends_per_se;
2033 unsigned max_texture_channel_caches;
2034 unsigned max_gprs;
2035 unsigned max_threads;
2036 unsigned max_gs_threads;
2037 unsigned max_stack_entries;
2038 unsigned sx_num_of_sets;
2039 unsigned sx_max_export_size;
2040 unsigned sx_max_export_pos_size;
2041 unsigned sx_max_export_smx_size;
2042 unsigned max_hw_contexts;
2043 unsigned sq_num_cf_insts;
2044 unsigned sc_prim_fifo_size;
2045 unsigned sc_hiz_tile_fifo_size;
2046 unsigned sc_earlyz_tile_fifo_size;
2047
2048 unsigned num_shader_engines;
2049 unsigned num_shader_pipes_per_simd;
2050 unsigned num_tile_pipes;
2051 unsigned num_simds_per_se;
2052 unsigned num_backends_per_se;
2053 unsigned backend_disable_mask_per_asic;
2054 unsigned backend_map;
2055 unsigned num_texture_channel_caches;
2056 unsigned mem_max_burst_length_bytes;
2057 unsigned mem_row_size_in_kb;
2058 unsigned shader_engine_tile_size;
2059 unsigned num_gpus;
2060 unsigned multi_gpu_tile_size;
2061
2062 unsigned tile_config;
2063 };
2064
2065 struct si_asic {
2066 unsigned max_shader_engines;
2067 unsigned max_tile_pipes;
2068 unsigned max_cu_per_sh;
2069 unsigned max_sh_per_se;
2070 unsigned max_backends_per_se;
2071 unsigned max_texture_channel_caches;
2072 unsigned max_gprs;
2073 unsigned max_gs_threads;
2074 unsigned max_hw_contexts;
2075 unsigned sc_prim_fifo_size_frontend;
2076 unsigned sc_prim_fifo_size_backend;
2077 unsigned sc_hiz_tile_fifo_size;
2078 unsigned sc_earlyz_tile_fifo_size;
2079
2080 unsigned num_tile_pipes;
2081 unsigned backend_enable_mask;
2082 unsigned backend_disable_mask_per_asic;
2083 unsigned backend_map;
2084 unsigned num_texture_channel_caches;
2085 unsigned mem_max_burst_length_bytes;
2086 unsigned mem_row_size_in_kb;
2087 unsigned shader_engine_tile_size;
2088 unsigned num_gpus;
2089 unsigned multi_gpu_tile_size;
2090
2091 unsigned tile_config;
2092 uint32_t tile_mode_array[32];
2093 };
2094
2095 struct cik_asic {
2096 unsigned max_shader_engines;
2097 unsigned max_tile_pipes;
2098 unsigned max_cu_per_sh;
2099 unsigned max_sh_per_se;
2100 unsigned max_backends_per_se;
2101 unsigned max_texture_channel_caches;
2102 unsigned max_gprs;
2103 unsigned max_gs_threads;
2104 unsigned max_hw_contexts;
2105 unsigned sc_prim_fifo_size_frontend;
2106 unsigned sc_prim_fifo_size_backend;
2107 unsigned sc_hiz_tile_fifo_size;
2108 unsigned sc_earlyz_tile_fifo_size;
2109
2110 unsigned num_tile_pipes;
2111 unsigned backend_enable_mask;
2112 unsigned backend_disable_mask_per_asic;
2113 unsigned backend_map;
2114 unsigned num_texture_channel_caches;
2115 unsigned mem_max_burst_length_bytes;
2116 unsigned mem_row_size_in_kb;
2117 unsigned shader_engine_tile_size;
2118 unsigned num_gpus;
2119 unsigned multi_gpu_tile_size;
2120
2121 unsigned tile_config;
2122 uint32_t tile_mode_array[32];
2123 uint32_t macrotile_mode_array[16];
2124 };
2125
2126 union radeon_asic_config {
2127 struct r300_asic r300;
2128 struct r100_asic r100;
2129 struct r600_asic r600;
2130 struct rv770_asic rv770;
2131 struct evergreen_asic evergreen;
2132 struct cayman_asic cayman;
2133 struct si_asic si;
2134 struct cik_asic cik;
2135 };
2136
2137 /*
2138 * asic initizalization from radeon_asic.c
2139 */
2140 void radeon_agp_disable(struct radeon_device *rdev);
2141 int radeon_asic_init(struct radeon_device *rdev);
2142
2143
2144 /*
2145 * IOCTL.
2146 */
2147 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
2148 struct drm_file *filp);
2149 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
2150 struct drm_file *filp);
2151 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
2152 struct drm_file *file_priv);
2153 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
2154 struct drm_file *file_priv);
2155 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2156 struct drm_file *file_priv);
2157 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
2158 struct drm_file *file_priv);
2159 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2160 struct drm_file *filp);
2161 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
2162 struct drm_file *filp);
2163 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
2164 struct drm_file *filp);
2165 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
2166 struct drm_file *filp);
2167 int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
2168 struct drm_file *filp);
2169 int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
2170 struct drm_file *filp);
2171 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
2172 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2173 struct drm_file *filp);
2174 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2175 struct drm_file *filp);
2176
2177 /* VRAM scratch page for HDP bug, default vram page */
2178 struct r600_vram_scratch {
2179 struct radeon_bo *robj;
2180 volatile uint32_t *ptr;
2181 u64 gpu_addr;
2182 };
2183
2184 /*
2185 * ACPI
2186 */
2187 struct radeon_atif_notification_cfg {
2188 bool enabled;
2189 int command_code;
2190 };
2191
2192 struct radeon_atif_notifications {
2193 bool display_switch;
2194 bool expansion_mode_change;
2195 bool thermal_state;
2196 bool forced_power_state;
2197 bool system_power_state;
2198 bool display_conf_change;
2199 bool px_gfx_switch;
2200 bool brightness_change;
2201 bool dgpu_display_event;
2202 };
2203
2204 struct radeon_atif_functions {
2205 bool system_params;
2206 bool sbios_requests;
2207 bool select_active_disp;
2208 bool lid_state;
2209 bool get_tv_standard;
2210 bool set_tv_standard;
2211 bool get_panel_expansion_mode;
2212 bool set_panel_expansion_mode;
2213 bool temperature_change;
2214 bool graphics_device_types;
2215 };
2216
2217 struct radeon_atif {
2218 struct radeon_atif_notifications notifications;
2219 struct radeon_atif_functions functions;
2220 struct radeon_atif_notification_cfg notification_cfg;
2221 struct radeon_encoder *encoder_for_bl;
2222 };
2223
2224 struct radeon_atcs_functions {
2225 bool get_ext_state;
2226 bool pcie_perf_req;
2227 bool pcie_dev_rdy;
2228 bool pcie_bus_width;
2229 };
2230
2231 struct radeon_atcs {
2232 struct radeon_atcs_functions functions;
2233 };
2234
2235 /*
2236 * Core structure, functions and helpers.
2237 */
2238 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
2239 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
2240
2241 struct radeon_device {
2242 struct device *dev;
2243 struct drm_device *ddev;
2244 struct pci_dev *pdev;
2245 struct rw_semaphore exclusive_lock;
2246 /* ASIC */
2247 union radeon_asic_config config;
2248 enum radeon_family family;
2249 unsigned long flags;
2250 int usec_timeout;
2251 enum radeon_pll_errata pll_errata;
2252 int num_gb_pipes;
2253 int num_z_pipes;
2254 int disp_priority;
2255 /* BIOS */
2256 uint8_t *bios;
2257 bool is_atom_bios;
2258 uint16_t bios_header_start;
2259 struct radeon_bo *stollen_vga_memory;
2260 /* Register mmio */
2261 #ifndef __NetBSD__
2262 resource_size_t rmmio_base;
2263 resource_size_t rmmio_size;
2264 #endif
2265 /* protects concurrent MM_INDEX/DATA based register access */
2266 spinlock_t mmio_idx_lock;
2267 /* protects concurrent SMC based register access */
2268 spinlock_t smc_idx_lock;
2269 /* protects concurrent PLL register access */
2270 spinlock_t pll_idx_lock;
2271 /* protects concurrent MC register access */
2272 spinlock_t mc_idx_lock;
2273 /* protects concurrent PCIE register access */
2274 spinlock_t pcie_idx_lock;
2275 /* protects concurrent PCIE_PORT register access */
2276 spinlock_t pciep_idx_lock;
2277 /* protects concurrent PIF register access */
2278 spinlock_t pif_idx_lock;
2279 /* protects concurrent CG register access */
2280 spinlock_t cg_idx_lock;
2281 /* protects concurrent UVD register access */
2282 spinlock_t uvd_idx_lock;
2283 /* protects concurrent RCU register access */
2284 spinlock_t rcu_idx_lock;
2285 /* protects concurrent DIDT register access */
2286 spinlock_t didt_idx_lock;
2287 /* protects concurrent ENDPOINT (audio) register access */
2288 spinlock_t end_idx_lock;
2289 #ifdef __NetBSD__
2290 bus_space_tag_t rmmio_bst;
2291 bus_space_handle_t rmmio_bsh;
2292 bus_addr_t rmmio_addr;
2293 bus_size_t rmmio_size;
2294 #else
2295 void __iomem *rmmio;
2296 #endif
2297 radeon_rreg_t mc_rreg;
2298 radeon_wreg_t mc_wreg;
2299 radeon_rreg_t pll_rreg;
2300 radeon_wreg_t pll_wreg;
2301 uint32_t pcie_reg_mask;
2302 radeon_rreg_t pciep_rreg;
2303 radeon_wreg_t pciep_wreg;
2304 /* io port */
2305 #ifdef __NetBSD__
2306 bus_space_tag_t rio_mem_bst;
2307 bus_space_handle_t rio_mem_bsh;
2308 bus_size_t rio_mem_size;
2309 #else
2310 void __iomem *rio_mem;
2311 resource_size_t rio_mem_size;
2312 #endif
2313 struct radeon_clock clock;
2314 struct radeon_mc mc;
2315 struct radeon_gart gart;
2316 struct radeon_mode_info mode_info;
2317 struct radeon_scratch scratch;
2318 struct radeon_doorbell doorbell;
2319 struct radeon_mman mman;
2320 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
2321 #ifdef __NetBSD__
2322 spinlock_t fence_lock;
2323 drm_waitqueue_t fence_queue;
2324 #else
2325 wait_queue_head_t fence_queue;
2326 #endif
2327 struct mutex ring_lock;
2328 struct radeon_ring ring[RADEON_NUM_RINGS];
2329 bool ib_pool_ready;
2330 struct radeon_sa_manager ring_tmp_bo;
2331 struct radeon_irq irq;
2332 struct radeon_asic *asic;
2333 struct radeon_gem gem;
2334 struct radeon_pm pm;
2335 struct radeon_uvd uvd;
2336 struct radeon_vce vce;
2337 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
2338 struct radeon_wb wb;
2339 struct radeon_dummy_page dummy_page;
2340 bool shutdown;
2341 bool suspend;
2342 bool need_dma32;
2343 bool accel_working;
2344 bool fastfb_working; /* IGP feature*/
2345 bool needs_reset;
2346 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
2347 const struct firmware *me_fw; /* all family ME firmware */
2348 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
2349 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
2350 const struct firmware *mc_fw; /* NI MC firmware */
2351 const struct firmware *ce_fw; /* SI CE firmware */
2352 const struct firmware *mec_fw; /* CIK MEC firmware */
2353 const struct firmware *sdma_fw; /* CIK SDMA firmware */
2354 const struct firmware *smc_fw; /* SMC firmware */
2355 const struct firmware *uvd_fw; /* UVD firmware */
2356 const struct firmware *vce_fw; /* VCE firmware */
2357 struct r600_vram_scratch vram_scratch;
2358 int msi_enabled; /* msi enabled */
2359 struct r600_ih ih; /* r6/700 interrupt ring */
2360 struct radeon_rlc rlc;
2361 struct radeon_mec mec;
2362 struct work_struct hotplug_work;
2363 struct work_struct audio_work;
2364 struct work_struct reset_work;
2365 int num_crtc; /* number of crtcs */
2366 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
2367 bool has_uvd;
2368 struct r600_audio audio; /* audio stuff */
2369 struct notifier_block acpi_nb;
2370 /* only one userspace can use Hyperz features or CMASK at a time */
2371 struct drm_file *hyperz_filp;
2372 struct drm_file *cmask_filp;
2373 /* i2c buses */
2374 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
2375 /* debugfs */
2376 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
2377 unsigned debugfs_count;
2378 /* virtual memory */
2379 struct radeon_vm_manager vm_manager;
2380 struct mutex gpu_clock_mutex;
2381 /* memory stats */
2382 atomic64_t vram_usage;
2383 atomic64_t gtt_usage;
2384 atomic64_t num_bytes_moved;
2385 /* ACPI interface */
2386 struct radeon_atif atif;
2387 struct radeon_atcs atcs;
2388 /* srbm instance registers */
2389 struct mutex srbm_mutex;
2390 /* clock, powergating flags */
2391 u32 cg_flags;
2392 u32 pg_flags;
2393
2394 struct dev_pm_domain vga_pm_domain;
2395 bool have_disp_power_ref;
2396 };
2397
2398 bool radeon_is_px(struct drm_device *dev);
2399 int radeon_device_init(struct radeon_device *rdev,
2400 struct drm_device *ddev,
2401 struct pci_dev *pdev,
2402 uint32_t flags);
2403 void radeon_device_fini(struct radeon_device *rdev);
2404 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
2405
2406 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
2407 bool always_indirect);
2408 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
2409 bool always_indirect);
2410 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
2411 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
2412
2413 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index);
2414 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v);
2415
2416 /*
2417 * Cast helper
2418 */
2419 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
2420
2421 /*
2422 * Registers read & write functions.
2423 */
2424 #ifdef __NetBSD__
2425 #define RREG8(r) bus_space_read_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r))
2426 #define WREG8(r, v) bus_space_write_1(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v))
2427 #define RREG16(r) bus_space_read_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r))
2428 #define WREG16(r, v) bus_space_write_2(rdev->rmmio_bst, rdev->rmmio_bsh, (r), (v))
2429 #else
2430 #define RREG8(reg) readb((rdev->rmmio) + (reg))
2431 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
2432 #define RREG16(reg) readw((rdev->rmmio) + (reg))
2433 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
2434 #endif
2435 #define RREG32(reg) r100_mm_rreg(rdev, (reg), false)
2436 #define RREG32_IDX(reg) r100_mm_rreg(rdev, (reg), true)
2437 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg), false))
2438 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v), false)
2439 #define WREG32_IDX(reg, v) r100_mm_wreg(rdev, (reg), (v), true)
2440 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2441 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2442 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
2443 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
2444 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
2445 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
2446 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
2447 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
2448 #define RREG32_PCIE_PORT(reg) rdev->pciep_rreg(rdev, (reg))
2449 #define WREG32_PCIE_PORT(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
2450 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg))
2451 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v))
2452 #define RREG32_RCU(reg) r600_rcu_rreg(rdev, (reg))
2453 #define WREG32_RCU(reg, v) r600_rcu_wreg(rdev, (reg), (v))
2454 #define RREG32_CG(reg) eg_cg_rreg(rdev, (reg))
2455 #define WREG32_CG(reg, v) eg_cg_wreg(rdev, (reg), (v))
2456 #define RREG32_PIF_PHY0(reg) eg_pif_phy0_rreg(rdev, (reg))
2457 #define WREG32_PIF_PHY0(reg, v) eg_pif_phy0_wreg(rdev, (reg), (v))
2458 #define RREG32_PIF_PHY1(reg) eg_pif_phy1_rreg(rdev, (reg))
2459 #define WREG32_PIF_PHY1(reg, v) eg_pif_phy1_wreg(rdev, (reg), (v))
2460 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg))
2461 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v))
2462 #define RREG32_DIDT(reg) cik_didt_rreg(rdev, (reg))
2463 #define WREG32_DIDT(reg, v) cik_didt_wreg(rdev, (reg), (v))
2464 #define WREG32_P(reg, val, mask) \
2465 do { \
2466 uint32_t tmp_ = RREG32(reg); \
2467 tmp_ &= (mask); \
2468 tmp_ |= ((val) & ~(mask)); \
2469 WREG32(reg, tmp_); \
2470 } while (0)
2471 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2472 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2473 #define WREG32_PLL_P(reg, val, mask) \
2474 do { \
2475 uint32_t tmp_ = RREG32_PLL(reg); \
2476 tmp_ &= (mask); \
2477 tmp_ |= ((val) & ~(mask)); \
2478 WREG32_PLL(reg, tmp_); \
2479 } while (0)
2480 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg), false))
2481 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
2482 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
2483
2484 #define RDOORBELL32(index) cik_mm_rdoorbell(rdev, (index))
2485 #define WDOORBELL32(index, v) cik_mm_wdoorbell(rdev, (index), (v))
2486
2487 /*
2488 * Indirect registers accessor
2489 */
rv370_pcie_rreg(struct radeon_device * rdev,uint32_t reg)2490 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
2491 {
2492 unsigned long flags;
2493 uint32_t r;
2494
2495 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2496 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2497 r = RREG32(RADEON_PCIE_DATA);
2498 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2499 return r;
2500 }
2501
rv370_pcie_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)2502 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2503 {
2504 unsigned long flags;
2505
2506 spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
2507 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
2508 WREG32(RADEON_PCIE_DATA, (v));
2509 spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
2510 }
2511
tn_smc_rreg(struct radeon_device * rdev,u32 reg)2512 static inline u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
2513 {
2514 unsigned long flags;
2515 u32 r;
2516
2517 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2518 WREG32(TN_SMC_IND_INDEX_0, (reg));
2519 r = RREG32(TN_SMC_IND_DATA_0);
2520 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2521 return r;
2522 }
2523
tn_smc_wreg(struct radeon_device * rdev,u32 reg,u32 v)2524 static inline void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2525 {
2526 unsigned long flags;
2527
2528 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
2529 WREG32(TN_SMC_IND_INDEX_0, (reg));
2530 WREG32(TN_SMC_IND_DATA_0, (v));
2531 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
2532 }
2533
r600_rcu_rreg(struct radeon_device * rdev,u32 reg)2534 static inline u32 r600_rcu_rreg(struct radeon_device *rdev, u32 reg)
2535 {
2536 unsigned long flags;
2537 u32 r;
2538
2539 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2540 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2541 r = RREG32(R600_RCU_DATA);
2542 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2543 return r;
2544 }
2545
r600_rcu_wreg(struct radeon_device * rdev,u32 reg,u32 v)2546 static inline void r600_rcu_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2547 {
2548 unsigned long flags;
2549
2550 spin_lock_irqsave(&rdev->rcu_idx_lock, flags);
2551 WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));
2552 WREG32(R600_RCU_DATA, (v));
2553 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags);
2554 }
2555
eg_cg_rreg(struct radeon_device * rdev,u32 reg)2556 static inline u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg)
2557 {
2558 unsigned long flags;
2559 u32 r;
2560
2561 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2562 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2563 r = RREG32(EVERGREEN_CG_IND_DATA);
2564 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2565 return r;
2566 }
2567
eg_cg_wreg(struct radeon_device * rdev,u32 reg,u32 v)2568 static inline void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2569 {
2570 unsigned long flags;
2571
2572 spin_lock_irqsave(&rdev->cg_idx_lock, flags);
2573 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));
2574 WREG32(EVERGREEN_CG_IND_DATA, (v));
2575 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags);
2576 }
2577
eg_pif_phy0_rreg(struct radeon_device * rdev,u32 reg)2578 static inline u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg)
2579 {
2580 unsigned long flags;
2581 u32 r;
2582
2583 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2584 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2585 r = RREG32(EVERGREEN_PIF_PHY0_DATA);
2586 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2587 return r;
2588 }
2589
eg_pif_phy0_wreg(struct radeon_device * rdev,u32 reg,u32 v)2590 static inline void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2591 {
2592 unsigned long flags;
2593
2594 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2595 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));
2596 WREG32(EVERGREEN_PIF_PHY0_DATA, (v));
2597 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2598 }
2599
eg_pif_phy1_rreg(struct radeon_device * rdev,u32 reg)2600 static inline u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg)
2601 {
2602 unsigned long flags;
2603 u32 r;
2604
2605 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2606 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2607 r = RREG32(EVERGREEN_PIF_PHY1_DATA);
2608 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2609 return r;
2610 }
2611
eg_pif_phy1_wreg(struct radeon_device * rdev,u32 reg,u32 v)2612 static inline void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2613 {
2614 unsigned long flags;
2615
2616 spin_lock_irqsave(&rdev->pif_idx_lock, flags);
2617 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));
2618 WREG32(EVERGREEN_PIF_PHY1_DATA, (v));
2619 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags);
2620 }
2621
r600_uvd_ctx_rreg(struct radeon_device * rdev,u32 reg)2622 static inline u32 r600_uvd_ctx_rreg(struct radeon_device *rdev, u32 reg)
2623 {
2624 unsigned long flags;
2625 u32 r;
2626
2627 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2628 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2629 r = RREG32(R600_UVD_CTX_DATA);
2630 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2631 return r;
2632 }
2633
r600_uvd_ctx_wreg(struct radeon_device * rdev,u32 reg,u32 v)2634 static inline void r600_uvd_ctx_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2635 {
2636 unsigned long flags;
2637
2638 spin_lock_irqsave(&rdev->uvd_idx_lock, flags);
2639 WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));
2640 WREG32(R600_UVD_CTX_DATA, (v));
2641 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags);
2642 }
2643
2644
cik_didt_rreg(struct radeon_device * rdev,u32 reg)2645 static inline u32 cik_didt_rreg(struct radeon_device *rdev, u32 reg)
2646 {
2647 unsigned long flags;
2648 u32 r;
2649
2650 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2651 WREG32(CIK_DIDT_IND_INDEX, (reg));
2652 r = RREG32(CIK_DIDT_IND_DATA);
2653 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2654 return r;
2655 }
2656
cik_didt_wreg(struct radeon_device * rdev,u32 reg,u32 v)2657 static inline void cik_didt_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2658 {
2659 unsigned long flags;
2660
2661 spin_lock_irqsave(&rdev->didt_idx_lock, flags);
2662 WREG32(CIK_DIDT_IND_INDEX, (reg));
2663 WREG32(CIK_DIDT_IND_DATA, (v));
2664 spin_unlock_irqrestore(&rdev->didt_idx_lock, flags);
2665 }
2666
2667 void r100_pll_errata_after_index(struct radeon_device *rdev);
2668
2669
2670 /*
2671 * ASICs helpers.
2672 */
2673 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
2674 (rdev->pdev->device == 0x5969))
2675 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
2676 (rdev->family == CHIP_RV200) || \
2677 (rdev->family == CHIP_RS100) || \
2678 (rdev->family == CHIP_RS200) || \
2679 (rdev->family == CHIP_RV250) || \
2680 (rdev->family == CHIP_RV280) || \
2681 (rdev->family == CHIP_RS300))
2682 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
2683 (rdev->family == CHIP_RV350) || \
2684 (rdev->family == CHIP_R350) || \
2685 (rdev->family == CHIP_RV380) || \
2686 (rdev->family == CHIP_R420) || \
2687 (rdev->family == CHIP_R423) || \
2688 (rdev->family == CHIP_RV410) || \
2689 (rdev->family == CHIP_RS400) || \
2690 (rdev->family == CHIP_RS480))
2691 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
2692 (rdev->ddev->pdev->device == 0x9443) || \
2693 (rdev->ddev->pdev->device == 0x944B) || \
2694 (rdev->ddev->pdev->device == 0x9506) || \
2695 (rdev->ddev->pdev->device == 0x9509) || \
2696 (rdev->ddev->pdev->device == 0x950F) || \
2697 (rdev->ddev->pdev->device == 0x689C) || \
2698 (rdev->ddev->pdev->device == 0x689D))
2699 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
2700 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
2701 (rdev->family == CHIP_RS690) || \
2702 (rdev->family == CHIP_RS740) || \
2703 (rdev->family >= CHIP_R600))
2704 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
2705 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
2706 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
2707 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
2708 (rdev->flags & RADEON_IS_IGP))
2709 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
2710 #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
2711 #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
2712 (rdev->flags & RADEON_IS_IGP))
2713 #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
2714 #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
2715 #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
2716 #define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
2717 #define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
2718 #define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI) || \
2719 (rdev->family == CHIP_MULLINS))
2720
2721 #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
2722 (rdev->ddev->pdev->device == 0x6850) || \
2723 (rdev->ddev->pdev->device == 0x6858) || \
2724 (rdev->ddev->pdev->device == 0x6859) || \
2725 (rdev->ddev->pdev->device == 0x6840) || \
2726 (rdev->ddev->pdev->device == 0x6841) || \
2727 (rdev->ddev->pdev->device == 0x6842) || \
2728 (rdev->ddev->pdev->device == 0x6843))
2729
2730 /*
2731 * BIOS helpers.
2732 */
2733 #define RBIOS8(i) (rdev->bios[i])
2734 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2735 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2736
2737 int radeon_combios_init(struct radeon_device *rdev);
2738 void radeon_combios_fini(struct radeon_device *rdev);
2739 int radeon_atombios_init(struct radeon_device *rdev);
2740 void radeon_atombios_fini(struct radeon_device *rdev);
2741
2742
2743 /*
2744 * RING helpers.
2745 */
2746 #if DRM_DEBUG_CODE == 0
radeon_ring_write(struct radeon_ring * ring,uint32_t v)2747 static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2748 {
2749 ring->ring[ring->wptr++] = v;
2750 ring->wptr &= ring->ptr_mask;
2751 ring->count_dw--;
2752 ring->ring_free_dw--;
2753 }
2754 #else
2755 /* With debugging this is just too big to inline */
2756 void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
2757 #endif
2758
2759 /*
2760 * ASICs macro.
2761 */
2762 #define radeon_init(rdev) (rdev)->asic->init((rdev))
2763 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
2764 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
2765 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
2766 #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)]->cs_parse((p))
2767 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
2768 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
2769 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev))
2770 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
2771 #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
2772 #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
2773 #define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
2774 #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_start((rdev), (cp))
2775 #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ring_test((rdev), (cp))
2776 #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)]->ib_test((rdev), (cp))
2777 #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2778 #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2779 #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2780 #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm))
2781 #define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2782 #define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2783 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
2784 #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev))
2785 #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev))
2786 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
2787 #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
2788 #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
2789 #define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
2790 #define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
2791 #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)]->emit_fence((rdev), (fence))
2792 #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
2793 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
2794 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f))
2795 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f))
2796 #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index
2797 #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index
2798 #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index
2799 #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev))
2800 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e))
2801 #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev))
2802 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e))
2803 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev))
2804 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l))
2805 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e))
2806 #define radeon_set_uvd_clocks(rdev, v, d) (rdev)->asic->pm.set_uvd_clocks((rdev), (v), (d))
2807 #define radeon_set_vce_clocks(rdev, ev, ec) (rdev)->asic->pm.set_vce_clocks((rdev), (ev), (ec))
2808 #define radeon_get_temperature(rdev) (rdev)->asic->pm.get_temperature((rdev))
2809 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s)))
2810 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r)))
2811 #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))
2812 #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev))
2813 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev))
2814 #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h))
2815 #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h))
2816 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
2817 #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev))
2818 #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev))
2819 #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev))
2820 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev))
2821 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev))
2822 #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc))
2823 #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base))
2824 #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc))
2825 #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))
2826 #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev))
2827 #define radeon_get_xclk(rdev) (rdev)->asic->get_xclk((rdev))
2828 #define radeon_get_gpu_clock_counter(rdev) (rdev)->asic->get_gpu_clock_counter((rdev))
2829 #define radeon_dpm_init(rdev) rdev->asic->dpm.init((rdev))
2830 #define radeon_dpm_setup_asic(rdev) rdev->asic->dpm.setup_asic((rdev))
2831 #define radeon_dpm_enable(rdev) rdev->asic->dpm.enable((rdev))
2832 #define radeon_dpm_late_enable(rdev) rdev->asic->dpm.late_enable((rdev))
2833 #define radeon_dpm_disable(rdev) rdev->asic->dpm.disable((rdev))
2834 #define radeon_dpm_pre_set_power_state(rdev) rdev->asic->dpm.pre_set_power_state((rdev))
2835 #define radeon_dpm_set_power_state(rdev) rdev->asic->dpm.set_power_state((rdev))
2836 #define radeon_dpm_post_set_power_state(rdev) rdev->asic->dpm.post_set_power_state((rdev))
2837 #define radeon_dpm_display_configuration_changed(rdev) rdev->asic->dpm.display_configuration_changed((rdev))
2838 #define radeon_dpm_fini(rdev) rdev->asic->dpm.fini((rdev))
2839 #define radeon_dpm_get_sclk(rdev, l) rdev->asic->dpm.get_sclk((rdev), (l))
2840 #define radeon_dpm_get_mclk(rdev, l) rdev->asic->dpm.get_mclk((rdev), (l))
2841 #define radeon_dpm_print_power_state(rdev, ps) rdev->asic->dpm.print_power_state((rdev), (ps))
2842 #define radeon_dpm_debugfs_print_current_performance_level(rdev, m) rdev->asic->dpm.debugfs_print_current_performance_level((rdev), (m))
2843 #define radeon_dpm_force_performance_level(rdev, l) rdev->asic->dpm.force_performance_level((rdev), (l))
2844 #define radeon_dpm_vblank_too_short(rdev) rdev->asic->dpm.vblank_too_short((rdev))
2845 #define radeon_dpm_powergate_uvd(rdev, g) rdev->asic->dpm.powergate_uvd((rdev), (g))
2846 #define radeon_dpm_enable_bapm(rdev, e) rdev->asic->dpm.enable_bapm((rdev), (e))
2847
2848 /* Common functions */
2849 /* AGP */
2850 extern int radeon_gpu_reset(struct radeon_device *rdev);
2851 extern void radeon_pci_config_reset(struct radeon_device *rdev);
2852 extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
2853 extern void radeon_agp_disable(struct radeon_device *rdev);
2854 extern int radeon_modeset_init(struct radeon_device *rdev);
2855 extern void radeon_modeset_fini(struct radeon_device *rdev);
2856 extern bool radeon_card_posted(struct radeon_device *rdev);
2857 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
2858 extern void radeon_update_display_priority(struct radeon_device *rdev);
2859 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
2860 extern void radeon_scratch_init(struct radeon_device *rdev);
2861 extern void radeon_wb_fini(struct radeon_device *rdev);
2862 extern int radeon_wb_init(struct radeon_device *rdev);
2863 extern void radeon_wb_disable(struct radeon_device *rdev);
2864 extern void radeon_surface_init(struct radeon_device *rdev);
2865 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
2866 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
2867 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
2868 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
2869 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
2870 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
2871 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
2872 extern int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2873 extern int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2874 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
2875 extern void radeon_program_register_sequence(struct radeon_device *rdev,
2876 const u32 *registers,
2877 const u32 array_size);
2878
2879 /*
2880 * vm
2881 */
2882 int radeon_vm_manager_init(struct radeon_device *rdev);
2883 void radeon_vm_manager_fini(struct radeon_device *rdev);
2884 int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2885 void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2886 struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev,
2887 struct radeon_vm *vm,
2888 struct list_head *head);
2889 struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2890 struct radeon_vm *vm, int ring);
2891 void radeon_vm_flush(struct radeon_device *rdev,
2892 struct radeon_vm *vm,
2893 int ring);
2894 void radeon_vm_fence(struct radeon_device *rdev,
2895 struct radeon_vm *vm,
2896 struct radeon_fence *fence);
2897 uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr);
2898 int radeon_vm_update_page_directory(struct radeon_device *rdev,
2899 struct radeon_vm *vm);
2900 int radeon_vm_bo_update(struct radeon_device *rdev,
2901 struct radeon_vm *vm,
2902 struct radeon_bo *bo,
2903 struct ttm_mem_reg *mem);
2904 void radeon_vm_bo_invalidate(struct radeon_device *rdev,
2905 struct radeon_bo *bo);
2906 struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm,
2907 struct radeon_bo *bo);
2908 struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev,
2909 struct radeon_vm *vm,
2910 struct radeon_bo *bo);
2911 int radeon_vm_bo_set_addr(struct radeon_device *rdev,
2912 struct radeon_bo_va *bo_va,
2913 uint64_t offset,
2914 uint32_t flags);
2915 int radeon_vm_bo_rmv(struct radeon_device *rdev,
2916 struct radeon_bo_va *bo_va);
2917
2918 /* audio */
2919 void r600_audio_update_hdmi(struct work_struct *work);
2920 struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
2921 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
2922 void r600_audio_enable(struct radeon_device *rdev,
2923 struct r600_audio_pin *pin,
2924 bool enable);
2925 void dce6_audio_enable(struct radeon_device *rdev,
2926 struct r600_audio_pin *pin,
2927 bool enable);
2928
2929 /*
2930 * R600 vram scratch functions
2931 */
2932 int r600_vram_scratch_init(struct radeon_device *rdev);
2933 void r600_vram_scratch_fini(struct radeon_device *rdev);
2934
2935 /*
2936 * r600 cs checking helper
2937 */
2938 unsigned r600_mip_minify(unsigned size, unsigned level);
2939 bool r600_fmt_is_valid_color(u32 format);
2940 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
2941 int r600_fmt_get_blocksize(u32 format);
2942 int r600_fmt_get_nblocksx(u32 format, u32 w);
2943 int r600_fmt_get_nblocksy(u32 format, u32 h);
2944
2945 /*
2946 * r600 functions used by radeon_encoder.c
2947 */
2948 struct radeon_hdmi_acr {
2949 u32 clock;
2950
2951 int n_32khz;
2952 int cts_32khz;
2953
2954 int n_44_1khz;
2955 int cts_44_1khz;
2956
2957 int n_48khz;
2958 int cts_48khz;
2959
2960 };
2961
2962 extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2963
2964 extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2965 u32 tiling_pipe_num,
2966 u32 max_rb_num,
2967 u32 total_max_rb_num,
2968 u32 enabled_rb_mask);
2969
2970 /*
2971 * evergreen functions used by radeon_encoder.c
2972 */
2973
2974 extern int ni_init_microcode(struct radeon_device *rdev);
2975 extern int ni_mc_load_microcode(struct radeon_device *rdev);
2976
2977 /* radeon_acpi.c */
2978 #if defined(CONFIG_ACPI)
2979 extern int radeon_acpi_init(struct radeon_device *rdev);
2980 extern void radeon_acpi_fini(struct radeon_device *rdev);
2981 extern bool radeon_acpi_is_pcie_performance_request_supported(struct radeon_device *rdev);
2982 extern int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
2983 u8 perf_req, bool advertise);
2984 extern int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev);
2985 #else
radeon_acpi_init(struct radeon_device * rdev)2986 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
radeon_acpi_fini(struct radeon_device * rdev)2987 static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
2988 #endif
2989
2990 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
2991 struct radeon_cs_packet *pkt,
2992 unsigned idx);
2993 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
2994 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
2995 struct radeon_cs_packet *pkt);
2996 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
2997 struct radeon_cs_reloc **cs_reloc,
2998 int nomm);
2999 int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3000 uint32_t *vline_start_end,
3001 uint32_t *vline_status);
3002
3003 #include "radeon_object.h"
3004
3005 #endif
3006